From patchwork Fri Dec 20 19:02:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eneas U de Queiroz X-Patchwork-Id: 11306227 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F3961921 for ; Fri, 20 Dec 2019 19:03:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D12A5206D8 for ; Fri, 20 Dec 2019 19:03:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rPBICheQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727473AbfLTTDB (ORCPT ); Fri, 20 Dec 2019 14:03:01 -0500 Received: from mail-pj1-f68.google.com ([209.85.216.68]:34479 "EHLO mail-pj1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727390AbfLTTDB (ORCPT ); Fri, 20 Dec 2019 14:03:01 -0500 Received: by mail-pj1-f68.google.com with SMTP id s94so4197395pjc.1 for ; Fri, 20 Dec 2019 11:03:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Az4hfXTopX7SrfF1whWHLS+fjneINDp+zU6Cq6OOuU4=; b=rPBICheQoVAzsZ2tln0x+1e9/YenkBMqvTTvQ4+LtS6qG7ZaOVx2D9p5RkYNzux9jK nizzsKP+6Pzxl6f8MkQUUXQ6J2PiiQU/jZnEQj2umbVwYuQPU67Mds/e6/9WnRpHup/8 1kIi3xYAhAmSOrXPJPQp+lRMHpRoDbWtnrToQLugwLxrbCnYsV4gpGdxCA5MpeQfk75H auWeSk9zjw+7Msh6EFNHOrAsyVBkOB9mx100S1dOw91w1rZCkIG4YRGprbDqH8QEytGQ yR97LGTy93M3MCdQOSUV/BJfzElwI5lf1ZiodjvlDhyAbHf7rGEwRGpDSdHC+aJ+P/8o 05Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Az4hfXTopX7SrfF1whWHLS+fjneINDp+zU6Cq6OOuU4=; b=V+gC2ARDTkwNm6oErpsz31M+n6JFIOfiWC7IaZIfY3ZlWxHK1Py1UPQiAojO5R+9ZM NIc0V9b53c0GgGLA2tYcm+k673dP0Yd6+gHbmpbMzIW9Jt+QI/p7jlADG4VAYakLhTyN HxX1OTqD6jnStTxxkmPYcy1hOr/8E+5Y8/J1shHLO4JW4SCxbLx+6mbDvnW2m1zcmPSw RL/N/cpX0KIlD9aR5bWgOZmsumF8xPjLTZGc3ducsJFEzREgKwzfHrHD7WSB+56QH5YD Rz9nZP6K+z70gDIGN7LdelNZo7ocal9IjdiC3+p7QQCM73+Y0NhKk2Wq75bE7yR80xU/ HQCw== X-Gm-Message-State: APjAAAXBcKlrsMZYGmihYNjQjPDmb/8RjLdo1zcuIApMff/kreY4CpG2 rAjWowsxvA9OBWdpgYtOiPc= X-Google-Smtp-Source: APXvYqysOn0HgJF6hHXWiJEUMy3SFDH+X0kH3ZyIKABEsX74AwvpFD1erJKlJHvp5+SRvgeIjmfEzA== X-Received: by 2002:a17:90a:2004:: with SMTP id n4mr18027020pjc.20.1576868580484; Fri, 20 Dec 2019 11:03:00 -0800 (PST) Received: from gateway.troianet.com.br (ipv6.troianet.com.br. [2804:688:21:4::2]) by smtp.gmail.com with ESMTPSA id i4sm10833612pjw.28.2019.12.20.11.02.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 11:03:00 -0800 (PST) From: Eneas U de Queiroz To: Herbert Xu , "David S. Miller" , linux-crypto@vger.kernel.org Cc: Eneas U de Queiroz Subject: [PATCH 1/6] crypto: qce - fix ctr-aes-qce block, chunk sizes Date: Fri, 20 Dec 2019 16:02:13 -0300 Message-Id: <20191220190218.28884-2-cotequeiroz@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191220190218.28884-1-cotequeiroz@gmail.com> References: <20191220190218.28884-1-cotequeiroz@gmail.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Set blocksize of ctr-aes-qce to 1, so it can operate as a stream cipher, adding the definition for chucksize instead, where the underlying block size belongs. Signed-off-by: Eneas U de Queiroz --- drivers/crypto/qce/skcipher.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index fee07323f8f9..1f1f40a761fa 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -270,6 +270,7 @@ struct qce_skcipher_def { const char *name; const char *drv_name; unsigned int blocksize; + unsigned int chunksize; unsigned int ivsize; unsigned int min_keysize; unsigned int max_keysize; @@ -298,7 +299,8 @@ static const struct qce_skcipher_def skcipher_def[] = { .flags = QCE_ALG_AES | QCE_MODE_CTR, .name = "ctr(aes)", .drv_name = "ctr-aes-qce", - .blocksize = AES_BLOCK_SIZE, + .blocksize = 1, + .chunksize = AES_BLOCK_SIZE, .ivsize = AES_BLOCK_SIZE, .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, @@ -368,6 +370,7 @@ static int qce_skcipher_register_one(const struct qce_skcipher_def *def, def->drv_name); alg->base.cra_blocksize = def->blocksize; + alg->chunksize = def->chunksize; alg->ivsize = def->ivsize; alg->min_keysize = def->min_keysize; alg->max_keysize = def->max_keysize; From patchwork Fri Dec 20 19:02:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eneas U de Queiroz X-Patchwork-Id: 11306229 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B9EFF921 for ; Fri, 20 Dec 2019 19:03:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 97D9020866 for ; Fri, 20 Dec 2019 19:03:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qYLdb1Sq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727478AbfLTTDE (ORCPT ); Fri, 20 Dec 2019 14:03:04 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:37046 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727390AbfLTTDE (ORCPT ); Fri, 20 Dec 2019 14:03:04 -0500 Received: by mail-pl1-f196.google.com with SMTP id c23so4490428plz.4 for ; Fri, 20 Dec 2019 11:03:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8g79+8HxgAmptJNweOiWrmJikepmZeeltOX1+NbRKNU=; b=qYLdb1SqIvI20mscu3ddS7O2XmV2HUwMMTkwmie+LgySwl5IBiXyJ9GtAMROyx3uWj mPogga3yRYR8TyqsssX6dX2ChHx/Ao6z/WDRUR8yRhqOdzyD4qCNi7k1fDQKUxUQmkfW JVhHQ8Shn3sTih7QuQhCMOq9VnaW1JoEGVQRRqVsvXkyg7ZwT5kPGHNo+tYgFvipFrs2 aGhsgnfTpbNlnW5quKVsA4OpDBglasnPrRWyxDex1nK7jQfMt/EgfyqwtqgqE1btodWB K0sAheBFLUNHG/imNeHezW7SFbMcDAyNedubS8LDJ+jtV52iiskdqdopKBWUw56iJnJL k/bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8g79+8HxgAmptJNweOiWrmJikepmZeeltOX1+NbRKNU=; b=F6JbtbNCtucpvrFlMP3ibARAum1Ge3c8WvGDalX38DqK2gge+LBX86J7od38nth28v 01qShTAlrXXpjQf19ztLMESoStNsdaLMqOdAVVtuZoy6MMkFAmZ2/PaD92K6UtwkdK3U tImOqznDI2oHOo76aF32oJWJAbwdAbzNRTNYlEhWGMJPRJ/LgCbuHs3jm9iR0ZKUnYb0 +80/uYqQcCA+l0RLcTajBh6bWVoS7wf86zYi7F1FnGOb6EH5GbOin9ZI+wJCaG+xklCx 5J+axWs99AEmsvi2zoJ3zVg2uvuJ6oEl5Q6UG4WNGUHubJ10koYrgB7E7d+Z0+AMg2dS r4Iw== X-Gm-Message-State: APjAAAVP0SvyFm3YL1zjdt7Zd53bc9NObBSV93YekzxITS72SuBaapMC wjsGRyHVVd4shSMHseUlEWBa7h3j7yM= X-Google-Smtp-Source: APXvYqyDoILnucbpEjUmU+9KRQiGvsRoyA+YJ70Yyub5QifgISMAyr32OOm9bUyUZFeVb9XHKkD8Bw== X-Received: by 2002:a17:90a:ba91:: with SMTP id t17mr18176418pjr.74.1576868583267; Fri, 20 Dec 2019 11:03:03 -0800 (PST) Received: from gateway.troianet.com.br (ipv6.troianet.com.br. [2804:688:21:4::2]) by smtp.gmail.com with ESMTPSA id i4sm10833612pjw.28.2019.12.20.11.03.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 11:03:02 -0800 (PST) From: Eneas U de Queiroz To: Herbert Xu , "David S. Miller" , linux-crypto@vger.kernel.org Cc: Eneas U de Queiroz Subject: [PATCH 2/6] crypto: qce - fix xts-aes-qce key sizes Date: Fri, 20 Dec 2019 16:02:14 -0300 Message-Id: <20191220190218.28884-3-cotequeiroz@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191220190218.28884-1-cotequeiroz@gmail.com> References: <20191220190218.28884-1-cotequeiroz@gmail.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org XTS-mode uses two keys, so the keysizes should be doubled in skcipher_def, and halved when checking if it is AES-128/192/256. Signed-off-by: Eneas U de Queiroz --- drivers/crypto/qce/skcipher.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index 1f1f40a761fa..e4f6d87ba51d 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -154,12 +154,13 @@ static int qce_skcipher_setkey(struct crypto_skcipher *ablk, const u8 *key, { struct crypto_tfm *tfm = crypto_skcipher_tfm(ablk); struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + unsigned long flags = to_cipher_tmpl(ablk)->alg_flags; int ret; if (!key || !keylen) return -EINVAL; - switch (keylen) { + switch (IS_XTS(flags) ? keylen >> 1 : keylen) { case AES_KEYSIZE_128: case AES_KEYSIZE_256: break; @@ -213,13 +214,15 @@ static int qce_skcipher_crypt(struct skcipher_request *req, int encrypt) struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); struct qce_alg_template *tmpl = to_cipher_tmpl(tfm); + int keylen; int ret; rctx->flags = tmpl->alg_flags; rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT; + keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen; - if (IS_AES(rctx->flags) && ctx->enc_keylen != AES_KEYSIZE_128 && - ctx->enc_keylen != AES_KEYSIZE_256) { + if (IS_AES(rctx->flags) && keylen != AES_KEYSIZE_128 && + keylen != AES_KEYSIZE_256) { SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); skcipher_request_set_sync_tfm(subreq, ctx->fallback); @@ -311,8 +314,8 @@ static const struct qce_skcipher_def skcipher_def[] = { .drv_name = "xts-aes-qce", .blocksize = AES_BLOCK_SIZE, .ivsize = AES_BLOCK_SIZE, - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, + .min_keysize = AES_MIN_KEY_SIZE * 2, + .max_keysize = AES_MAX_KEY_SIZE * 2, }, { .flags = QCE_ALG_DES | QCE_MODE_ECB, From patchwork Fri Dec 20 19:02:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eneas U de Queiroz X-Patchwork-Id: 11306231 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C02A14B7 for ; Fri, 20 Dec 2019 19:03:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 196F0206D8 for ; Fri, 20 Dec 2019 19:03:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EA63CUhX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727482AbfLTTDG (ORCPT ); Fri, 20 Dec 2019 14:03:06 -0500 Received: from mail-pj1-f67.google.com ([209.85.216.67]:39931 "EHLO mail-pj1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727390AbfLTTDG (ORCPT ); Fri, 20 Dec 2019 14:03:06 -0500 Received: by mail-pj1-f67.google.com with SMTP id t101so4528779pjb.4 for ; Fri, 20 Dec 2019 11:03:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eN0GkTu09upu/xisGXDpo1R5jjFIfIXvHq6ACDD9fTw=; b=EA63CUhXF6tuqkDOKFS3HZPm53hh9kRUdGel9V8jPwn3vvJPWn0Js6CKU8eZeVFNxR EBIQ0vzqYGMxY/Xy55Zedc0qmvhFzQr8cdPlcIiWD0BiAcekVdsjWNwfMf7bSdNQA6Sf PW5LyNmJLgz8P0nuvNqgL7ZmL4/AnXpRcUQdXOKI9vZz5gUVMEsV5uIfQu9sDv2M4RVt iLGXyr1TYubEQdY/eLW/ax4y+QSUojjg7GprxgjMIy8HwKCaiNQu21bi3pMRhQxYSs1Q k427J1TyKA8Bo/aiJsTpSPqtVSmjmaAZ+hkBEdjG54Ez2aNNnlak1z0KhWofG/bjJ5oR u1hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eN0GkTu09upu/xisGXDpo1R5jjFIfIXvHq6ACDD9fTw=; b=eWUeDXbbfvc1WkCEiXJRAjnhhXDViWAm0VdWIQr3yIQtV0g1ltPDJvWzKAJU/ghuaX WksX6UgNz6aPCTHTUlQRPoCq+XazgfTyt04mTg4TDs3K+ZC/4D9r8rPYfznWkm14tnKr JQOEpTUkKim+DFSZxnQx6iWfw4Qye7FwZCmHgD94Zx7njqJYOj8nZlQoheC0nBJYN0eH LJeiElYnFUe263EseKkUofYdydBOuBhG2qx0EAf/UpobOMsRF0Pyrtnq7gRNnIacEvtm 9Y08bD7M4XCM3n4DnXgGxmxea8t33FaxeZZLx4yFKl4LbKO/XmwQPGqkSEyScgZ6N9WA X+nA== X-Gm-Message-State: APjAAAU8IEX9Wp/iWywknRT1gMiILswoSbWXGY+1+WqNQeaSb4L8gQnh xQ3qDD2wxFBrmvdzqjB3EQ8= X-Google-Smtp-Source: APXvYqwc0rOZfR5z7Vk7OUXs8TyP7KVcK/toUxT8ovxNm09CqNIKAe0YwjPeS2Mq/6uVFP9X2KrJNw== X-Received: by 2002:a17:90a:ec0f:: with SMTP id l15mr17202255pjy.39.1576868585719; Fri, 20 Dec 2019 11:03:05 -0800 (PST) Received: from gateway.troianet.com.br (ipv6.troianet.com.br. [2804:688:21:4::2]) by smtp.gmail.com with ESMTPSA id i4sm10833612pjw.28.2019.12.20.11.03.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 11:03:05 -0800 (PST) From: Eneas U de Queiroz To: Herbert Xu , "David S. Miller" , linux-crypto@vger.kernel.org Cc: Eneas U de Queiroz Subject: [PATCH 3/6] crypto: qce - save a sg table slot for result buf Date: Fri, 20 Dec 2019 16:02:15 -0300 Message-Id: <20191220190218.28884-4-cotequeiroz@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191220190218.28884-1-cotequeiroz@gmail.com> References: <20191220190218.28884-1-cotequeiroz@gmail.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org When ctr-aes-qce is used for gcm-mode, an extra sg entry for the authentication tag is present, causing trouble when the qce driver prepares the dst-results sg table for dma. It computes the number of entries needed with sg_nents_for_len, leaving out the tag entry. Then it creates a sg table with that number plus one, used to store a result buffer. When copying the sg table, there's no limit to the number of entries copied, so the extra slot is filled with the authentication tag sg. When the driver tries to add the result sg, the list is full, and it returns EINVAL. By limiting the number of sg entries copied to the dest table, the slot for the result buffer is guaranteed to be unused. Signed-off-by: Eneas U de Queiroz --- drivers/crypto/qce/dma.c | 6 ++++-- drivers/crypto/qce/dma.h | 3 ++- drivers/crypto/qce/skcipher.c | 4 ++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 40a59214d2e1..7da893dc00e7 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -47,7 +47,8 @@ void qce_dma_release(struct qce_dma_data *dma) } struct scatterlist * -qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl) +qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl, + int max_ents) { struct scatterlist *sg = sgt->sgl, *sg_last = NULL; @@ -60,12 +61,13 @@ qce_sgtable_add(struct sg_table *sgt, struct scatterlist *new_sgl) if (!sg) return ERR_PTR(-EINVAL); - while (new_sgl && sg) { + while (new_sgl && sg && max_ents) { sg_set_page(sg, sg_page(new_sgl), new_sgl->length, new_sgl->offset); sg_last = sg; sg = sg_next(sg); new_sgl = sg_next(new_sgl); + max_ents--; } return sg_last; diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 1e25a9e0e6f8..ed25a0d9829e 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -42,6 +42,7 @@ int qce_dma_prep_sgs(struct qce_dma_data *dma, struct scatterlist *sg_in, void qce_dma_issue_pending(struct qce_dma_data *dma); int qce_dma_terminate_all(struct qce_dma_data *dma); struct scatterlist * -qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add); +qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add, + int max_ents); #endif /* _DMA_H_ */ diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index e4f6d87ba51d..a9ae356bc2a7 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -95,13 +95,13 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req) sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ); - sg = qce_sgtable_add(&rctx->dst_tbl, req->dst); + sg = qce_sgtable_add(&rctx->dst_tbl, req->dst, rctx->dst_nents - 1); if (IS_ERR(sg)) { ret = PTR_ERR(sg); goto error_free; } - sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg); + sg = qce_sgtable_add(&rctx->dst_tbl, &rctx->result_sg, 1); if (IS_ERR(sg)) { ret = PTR_ERR(sg); goto error_free; From patchwork Fri Dec 20 19:02:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eneas U de Queiroz X-Patchwork-Id: 11306233 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CAD7814B7 for ; Fri, 20 Dec 2019 19:03:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A9AD420866 for ; Fri, 20 Dec 2019 19:03:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="czDZLiSP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727508AbfLTTDJ (ORCPT ); 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[2804:688:21:4::2]) by smtp.gmail.com with ESMTPSA id i4sm10833612pjw.28.2019.12.20.11.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 11:03:07 -0800 (PST) From: Eneas U de Queiroz To: Herbert Xu , "David S. Miller" , linux-crypto@vger.kernel.org Cc: Eneas U de Queiroz Subject: [PATCH 4/6] crypto: qce - update the skcipher IV Date: Fri, 20 Dec 2019 16:02:16 -0300 Message-Id: <20191220190218.28884-5-cotequeiroz@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191220190218.28884-1-cotequeiroz@gmail.com> References: <20191220190218.28884-1-cotequeiroz@gmail.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Update the IV after the completion of each cipher operation. Signed-off-by: Eneas U de Queiroz --- drivers/crypto/qce/skcipher.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index a9ae356bc2a7..d3852a61cb1d 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -21,6 +21,7 @@ static void qce_skcipher_done(void *data) struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req)); struct qce_device *qce = tmpl->qce; + struct qce_result_dump *result_buf = qce->dma.result_buf; enum dma_data_direction dir_src, dir_dst; u32 status; int error; @@ -45,6 +46,7 @@ static void qce_skcipher_done(void *data) if (error < 0) dev_dbg(qce->dev, "skcipher operation error (%x)\n", status); + memcpy(rctx->iv, result_buf->encr_cntr_iv, rctx->ivsize); qce->async_req_done(tmpl->qce, error); } From patchwork Fri Dec 20 19:02:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eneas U de Queiroz X-Patchwork-Id: 11306235 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9EB1A921 for ; Fri, 20 Dec 2019 19:03:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7D15A20866 for ; Fri, 20 Dec 2019 19:03:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GjOofQD/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727462AbfLTTDN (ORCPT ); Fri, 20 Dec 2019 14:03:13 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:42326 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727390AbfLTTDM (ORCPT ); Fri, 20 Dec 2019 14:03:12 -0500 Received: by mail-pf1-f193.google.com with SMTP id 4so5705439pfz.9 for ; Fri, 20 Dec 2019 11:03:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k9VHXoez7FZfV4pIIvUMPzblEmmwCwWAxaZpHU4B+7o=; b=GjOofQD/GmW4vYJvez9BqInw0uQfcV+qDSNSfuAXt+OQ+d8N3UQy2ZKwFrSn7c6x9B myzur66DozRkTCuDkKyCB07fdKoLwTxM3yzjIVJsNib19Q9yHEwVmiP0wQJTThlaqP9i QJCXP9FcpgCCDj4D2Km8063mAMJZGNInj6r/fcbJIu8CJeXivhbf4yiH6DEmKNj/Gen2 RWimY+zPu+gY/aBkLzC6cts/g2wxGYRxblS6FAx92TcC6WMiPw9+q1G5d5dtwDeHmeHE Y+8h9p+7f8tNqRiAkR+b9DjWryrJ/IP6r+7xpx7Gd/Xz+jN98DOOjJV6lYOUDq4mMdlU a3Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k9VHXoez7FZfV4pIIvUMPzblEmmwCwWAxaZpHU4B+7o=; b=m8MF568SRQQVPd1nYd64OqFGgF044hKxXDFcTiRkGSV3qv5kt5UaT+FH2yenQQ2Rm/ jxresQeyHlGYiPhn7CJcTrkDyslpJhhqUWyNqlEple7uXJGvWpOhfkQHWapgNW/LwsQ0 p3xHCkbloJe+/0Q54O8zRl1aTQAkm61AspSvJ3N8zhR+VRm4Wy49LXdSZRAMmZ9+a/y1 mGul9IMHe0pwJdE+iGqSlEW1aDJy6pTK4BpAIRHu6vGsMhDTM9oNFchwXAc6zap7V3t4 uQRwAVDsq4IcupPOyhJU2PCN7PcaFHq2T83eFDN5OYbr/NSWln/iK4YvF6jypRJH/1H2 5xvw== X-Gm-Message-State: APjAAAVgcNDQZiKMTfr7anYXybomMzUHBDshT1uNUnwFHkYeZ4K0rBSi tRAH5Sg41MhKqmOcBxOhJN2oQxvXzOc= X-Google-Smtp-Source: APXvYqwyJRqy9ByNaKLL4SnNmJ3K6ABI5BKC3KmNdi7gg6gBXU1tbmXnlYW3JBKKP3S4mEwBPndDXg== X-Received: by 2002:a62:2a12:: with SMTP id q18mr18410054pfq.203.1576868592064; Fri, 20 Dec 2019 11:03:12 -0800 (PST) Received: from gateway.troianet.com.br (ipv6.troianet.com.br. [2804:688:21:4::2]) by smtp.gmail.com with ESMTPSA id i4sm10833612pjw.28.2019.12.20.11.03.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 11:03:10 -0800 (PST) From: Eneas U de Queiroz To: Herbert Xu , "David S. Miller" , linux-crypto@vger.kernel.org Cc: Eneas U de Queiroz Subject: [PATCH 5/6] crypto: qce - initialize fallback only for AES Date: Fri, 20 Dec 2019 16:02:17 -0300 Message-Id: <20191220190218.28884-6-cotequeiroz@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191220190218.28884-1-cotequeiroz@gmail.com> References: <20191220190218.28884-1-cotequeiroz@gmail.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Adjust cra_flags to add CRYPTO_NEED_FALLBACK only for AES ciphers, where AES-192 is not handled by the qce hardware, and don't allocate & free the fallback skcipher for other algorithms. Signed-off-by: Eneas U de Queiroz --- drivers/crypto/qce/skcipher.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index d3852a61cb1d..4217b745f124 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -257,7 +257,14 @@ static int qce_skcipher_init(struct crypto_skcipher *tfm) memset(ctx, 0, sizeof(*ctx)); crypto_skcipher_set_reqsize(tfm, sizeof(struct qce_cipher_reqctx)); + return 0; +} +static int qce_skcipher_init_fallback(struct crypto_skcipher *tfm) +{ + struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); + + qce_skcipher_init(tfm); ctx->fallback = crypto_alloc_sync_skcipher(crypto_tfm_alg_name(&tfm->base), 0, CRYPTO_ALG_NEED_FALLBACK); return PTR_ERR_OR_ZERO(ctx->fallback); @@ -387,14 +394,18 @@ static int qce_skcipher_register_one(const struct qce_skcipher_def *def, alg->base.cra_priority = 300; alg->base.cra_flags = CRYPTO_ALG_ASYNC | - CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY; alg->base.cra_ctxsize = sizeof(struct qce_cipher_ctx); alg->base.cra_alignmask = 0; alg->base.cra_module = THIS_MODULE; - alg->init = qce_skcipher_init; - alg->exit = qce_skcipher_exit; + if (IS_AES(def->flags)) { + alg->base.cra_flags |= CRYPTO_ALG_NEED_FALLBACK; + alg->init = qce_skcipher_init_fallback; + alg->exit = qce_skcipher_exit; + } else { + alg->init = qce_skcipher_init; + } INIT_LIST_HEAD(&tmpl->entry); tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_SKCIPHER; From patchwork Fri Dec 20 19:02:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eneas U de Queiroz X-Patchwork-Id: 11306237 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9AC214B7 for ; Fri, 20 Dec 2019 19:03:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A4918206D8 for ; Fri, 20 Dec 2019 19:03:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="n+/iXGZ4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727422AbfLTTDQ (ORCPT ); Fri, 20 Dec 2019 14:03:16 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:39711 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727390AbfLTTDP (ORCPT ); Fri, 20 Dec 2019 14:03:15 -0500 Received: by mail-pf1-f196.google.com with SMTP id q10so5708400pfs.6 for ; Fri, 20 Dec 2019 11:03:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/ciyFGskHG1SVOrUGpNjo4zQNHcUJjfbyh0aLUktQAw=; b=n+/iXGZ4sP6q1qDCr0Gwoo69dsEa0uUX/hHwzace9UuAJtlSxHxI09fHFM1YQTed7v yjzv46o/PPE2a3iBo2+lUCdy6x2ZHP9tviCkbKAZ7Te1ByBHV6vXm6guum1xl6uXwF08 bcnvPEYhZtNlJQgMirIl6U/oKA/Zm4UIK3CP80hFHyrYiiYDwhLT42N0bKbnlWsyR2F1 01J1VOR8cZmZSekEkILvgf7wTSQyCIIuCO+7izRsNuvooQFRNUeF+m1T6a1Q/vt8J6gx cMbgeP+Zi3m65ZmPbm97h92IpbdmDCWLZffxu3YxDexrfi7VOTI3ADQNb9lUXsOcfMku G+yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/ciyFGskHG1SVOrUGpNjo4zQNHcUJjfbyh0aLUktQAw=; b=n+4CF8DClrGsmqW35gSARLQWz3p07BW/KN3l0OyzXU8C/V+jiOTIbMTDe3GVtRUC66 LQzgCaCLd1+ThQEWFREidWcomMmR4jOMdT4QnZTyxvRHOv5bxAADOFZb4pMiPKFgB+Q/ g/VGi9sfknHTbbaN+Bx+t9hY/w2Ko633i8jxCWLVKFPwiZ8a4xzWysoivPm+Z0o6BNiO CrIdeWnlUDaOiE9r+wTzEezNssv80mc5NgymFa4alulEypxuFPfLHVVH8WyT5X6hWAGE 1upRrG/9tIaa0WT+njeF8kcxPRiqY4S1zi3y9DjIuptx4E1deGPunM02KBP2MgheRHkB e6HA== X-Gm-Message-State: APjAAAW9vcXbjQOLWFWcFTRq2e7ugSB1jcLaOAjK/314VPhLLUgBIsQC ndAY24bXY434KOq4rKuNlGI= X-Google-Smtp-Source: APXvYqy+QXK5x/06IasSUpWjwnbH7zXd2M7JVraxzIaEDjSCTRkIolMa4OhsjoQpXtJiIVe2VMp0fQ== X-Received: by 2002:a63:504c:: with SMTP id q12mr16435236pgl.117.1576868594662; Fri, 20 Dec 2019 11:03:14 -0800 (PST) Received: from gateway.troianet.com.br (ipv6.troianet.com.br. [2804:688:21:4::2]) by smtp.gmail.com with ESMTPSA id i4sm10833612pjw.28.2019.12.20.11.03.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 11:03:14 -0800 (PST) From: Eneas U de Queiroz To: Herbert Xu , "David S. Miller" , linux-crypto@vger.kernel.org Cc: Eneas U de Queiroz Subject: [PATCH 6/6] crypto: qce - allow building only hashes/ciphers Date: Fri, 20 Dec 2019 16:02:18 -0300 Message-Id: <20191220190218.28884-7-cotequeiroz@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191220190218.28884-1-cotequeiroz@gmail.com> References: <20191220190218.28884-1-cotequeiroz@gmail.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Allow the user to choose whether to build support for all algorithms (default), hashes-only, or skciphers-only. The QCE engine does not appear to scale as well as the CPU to handle multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the QCE handles only 2 requests in parallel. Ipsec throughput seems to improve when disabling either family of algorithms, sharing the load with the CPU. Enabling skciphers-only appears to work best. Signed-off-by: Eneas U de Queiroz --- drivers/crypto/Kconfig | 63 +++++++++- drivers/crypto/qce/Makefile | 7 +- drivers/crypto/qce/common.c | 244 +++++++++++++++++++----------------- drivers/crypto/qce/core.c | 4 + 4 files changed, 193 insertions(+), 125 deletions(-) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index d02e79ac81c0..73a80232e69e 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -618,6 +618,14 @@ config CRYPTO_DEV_QCE tristate "Qualcomm crypto engine accelerator" depends on ARCH_QCOM || COMPILE_TEST depends on HAS_IOMEM + help + This driver supports Qualcomm crypto engine accelerator + hardware. To compile this driver as a module, choose M here. The + module will be called qcrypto. + +config CRYPTO_DEV_QCE_SKCIPHER + bool + depends on CRYPTO_DEV_QCE select CRYPTO_AES select CRYPTO_LIB_DES select CRYPTO_ECB @@ -625,10 +633,57 @@ config CRYPTO_DEV_QCE select CRYPTO_XTS select CRYPTO_CTR select CRYPTO_SKCIPHER - help - This driver supports Qualcomm crypto engine accelerator - hardware. To compile this driver as a module, choose M here. The - module will be called qcrypto. + +config CRYPTO_DEV_QCE_SHA + bool + depends on CRYPTO_DEV_QCE + +choice + prompt "Algorithms enabled for QCE acceleration" + default CRYPTO_DEV_QCE_ENABLE_ALL + depends on CRYPTO_DEV_QCE + help + This option allows to choose whether to build support for all algorihtms + (default), hashes-only, or skciphers-only. + + The QCE engine does not appear to scale as well as the CPU to handle + multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the + QCE handles only 2 requests in parallel. + + Ipsec throughput seems to improve when disabling either family of + algorithms, sharing the load with the CPU. Enabling skciphers-only + appears to work best. + + config CRYPTO_DEV_QCE_ENABLE_ALL + bool "All supported algorithms" + select CRYPTO_DEV_QCE_SKCIPHER + select CRYPTO_DEV_QCE_SHA + help + Enable all supported algorithms: + - AES (CBC, CTR, ECB, XTS) + - 3DES (CBC, ECB) + - DES (CBC, ECB) + - SHA1, HMAC-SHA1 + - SHA256, HMAC-SHA256 + + config CRYPTO_DEV_QCE_ENABLE_SKCIPHER + bool "Symmetric-key ciphers only" + select CRYPTO_DEV_QCE_SKCIPHER + help + Enable symmetric-key ciphers only: + - AES (CBC, CTR, ECB, XTS) + - 3DES (ECB, CBC) + - DES (ECB, CBC) + + config CRYPTO_DEV_QCE_ENABLE_SHA + bool "Hash/HMAC only" + select CRYPTO_DEV_QCE_SHA + help + Enable hashes/HMAC algorithms only: + - SHA1, HMAC-SHA1 + - SHA256, HMAC-SHA256 + +endchoice config CRYPTO_DEV_QCOM_RNG tristate "Qualcomm Random Number Generator Driver" diff --git a/drivers/crypto/qce/Makefile b/drivers/crypto/qce/Makefile index 8caa04e1ec43..14ade8a7d664 100644 --- a/drivers/crypto/qce/Makefile +++ b/drivers/crypto/qce/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o qcrypto-objs := core.o \ common.o \ - dma.o \ - sha.o \ - skcipher.o + dma.o + +qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SHA) += sha.o +qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) += skcipher.o diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index da1188abc9ba..629e7f34dc09 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -45,52 +45,56 @@ qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len) qce_write(qce, offset + i * sizeof(u32), 0); } -static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size) +static u32 qce_config_reg(struct qce_device *qce, int little) { - u32 cfg = 0; + u32 beats = (qce->burst_size >> 3) - 1; + u32 pipe_pair = qce->pipe_pair_id; + u32 config; - if (IS_AES(flags)) { - if (aes_key_size == AES_KEYSIZE_128) - cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT; - else if (aes_key_size == AES_KEYSIZE_256) - cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT; - } + config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK; + config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) | + BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT); + config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK; + config &= ~HIGH_SPD_EN_N_SHIFT; - if (IS_AES(flags)) - cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT; - else if (IS_DES(flags) || IS_3DES(flags)) - cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT; + if (little) + config |= BIT(LITTLE_ENDIAN_MODE_SHIFT); - if (IS_DES(flags)) - cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT; + return config; +} - if (IS_3DES(flags)) - cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT; +void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len) +{ + __be32 *d = dst; + const u8 *s = src; + unsigned int n; - switch (flags & QCE_MODE_MASK) { - case QCE_MODE_ECB: - cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT; - break; - case QCE_MODE_CBC: - cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT; - break; - case QCE_MODE_CTR: - cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT; - break; - case QCE_MODE_XTS: - cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT; - break; - case QCE_MODE_CCM: - cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT; - cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT; - break; - default: - return ~0; + n = len / sizeof(u32); + for (; n > 0; n--) { + *d = cpu_to_be32p((const __u32 *) s); + s += sizeof(__u32); + d++; } +} - return cfg; +static void qce_setup_config(struct qce_device *qce) +{ + u32 config; + + /* get big endianness */ + config = qce_config_reg(qce, 0); + + /* clear status */ + qce_write(qce, REG_STATUS, 0); + qce_write(qce, REG_CONFIG, config); +} + +static inline void qce_crypto_go(struct qce_device *qce) +{ + qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); } +#ifdef CONFIG_CRYPTO_DEV_QCE_SHA static u32 qce_auth_cfg(unsigned long flags, u32 key_size) { u32 cfg = 0; @@ -137,88 +141,6 @@ static u32 qce_auth_cfg(unsigned long flags, u32 key_size) return cfg; } -static u32 qce_config_reg(struct qce_device *qce, int little) -{ - u32 beats = (qce->burst_size >> 3) - 1; - u32 pipe_pair = qce->pipe_pair_id; - u32 config; - - config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK; - config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) | - BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT); - config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK; - config &= ~HIGH_SPD_EN_N_SHIFT; - - if (little) - config |= BIT(LITTLE_ENDIAN_MODE_SHIFT); - - return config; -} - -void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len) -{ - __be32 *d = dst; - const u8 *s = src; - unsigned int n; - - n = len / sizeof(u32); - for (; n > 0; n--) { - *d = cpu_to_be32p((const __u32 *) s); - s += sizeof(__u32); - d++; - } -} - -static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize) -{ - u8 swap[QCE_AES_IV_LENGTH]; - u32 i, j; - - if (ivsize > QCE_AES_IV_LENGTH) - return; - - memset(swap, 0, QCE_AES_IV_LENGTH); - - for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1; - i < QCE_AES_IV_LENGTH; i++, j--) - swap[i] = src[j]; - - qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH); -} - -static void qce_xtskey(struct qce_device *qce, const u8 *enckey, - unsigned int enckeylen, unsigned int cryptlen) -{ - u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0}; - unsigned int xtsklen = enckeylen / (2 * sizeof(u32)); - unsigned int xtsdusize; - - qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2, - enckeylen / 2); - qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen); - - /* xts du size 512B */ - xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen); - qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize); -} - -static void qce_setup_config(struct qce_device *qce) -{ - u32 config; - - /* get big endianness */ - config = qce_config_reg(qce, 0); - - /* clear status */ - qce_write(qce, REG_STATUS, 0); - qce_write(qce, REG_CONFIG, config); -} - -static inline void qce_crypto_go(struct qce_device *qce) -{ - qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); -} - static int qce_setup_regs_ahash(struct crypto_async_request *async_req, u32 totallen, u32 offset) { @@ -303,6 +225,87 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req, return 0; } +#endif + +#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER +static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size) +{ + u32 cfg = 0; + + if (IS_AES(flags)) { + if (aes_key_size == AES_KEYSIZE_128) + cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT; + else if (aes_key_size == AES_KEYSIZE_256) + cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT; + } + + if (IS_AES(flags)) + cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT; + else if (IS_DES(flags) || IS_3DES(flags)) + cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT; + + if (IS_DES(flags)) + cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT; + + if (IS_3DES(flags)) + cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT; + + switch (flags & QCE_MODE_MASK) { + case QCE_MODE_ECB: + cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT; + break; + case QCE_MODE_CBC: + cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT; + break; + case QCE_MODE_CTR: + cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT; + break; + case QCE_MODE_XTS: + cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT; + break; + case QCE_MODE_CCM: + cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT; + cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT; + break; + default: + return ~0; + } + + return cfg; +} + +static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize) +{ + u8 swap[QCE_AES_IV_LENGTH]; + u32 i, j; + + if (ivsize > QCE_AES_IV_LENGTH) + return; + + memset(swap, 0, QCE_AES_IV_LENGTH); + + for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1; + i < QCE_AES_IV_LENGTH; i++, j--) + swap[i] = src[j]; + + qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH); +} + +static void qce_xtskey(struct qce_device *qce, const u8 *enckey, + unsigned int enckeylen, unsigned int cryptlen) +{ + u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0}; + unsigned int xtsklen = enckeylen / (2 * sizeof(u32)); + unsigned int xtsdusize; + + qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2, + enckeylen / 2); + qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen); + + /* xts du size 512B */ + xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen); + qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize); +} static int qce_setup_regs_skcipher(struct crypto_async_request *async_req, u32 totallen, u32 offset) @@ -384,15 +387,20 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req, return 0; } +#endif int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen, u32 offset) { switch (type) { +#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER case CRYPTO_ALG_TYPE_SKCIPHER: return qce_setup_regs_skcipher(async_req, totallen, offset); +#endif +#ifdef CONFIG_CRYPTO_DEV_QCE_SHA case CRYPTO_ALG_TYPE_AHASH: return qce_setup_regs_ahash(async_req, totallen, offset); +#endif default: return -EINVAL; } diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 0a44a6eeacf5..cb6d61eb7302 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -22,8 +22,12 @@ #define QCE_QUEUE_LENGTH 1 static const struct qce_algo_ops *qce_ops[] = { +#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER &skcipher_ops, +#endif +#ifdef CONFIG_CRYPTO_DEV_QCE_SHA &ahash_ops, +#endif }; static void qce_unregister_algs(struct qce_device *qce)