From patchwork Thu Dec 26 22:17:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11310753 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D40D109A for ; Thu, 26 Dec 2019 22:17:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF27720740 for ; Thu, 26 Dec 2019 22:17:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UQmFVNA7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727015AbfLZWRt (ORCPT ); Thu, 26 Dec 2019 17:17:49 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:33762 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726277AbfLZWRq (ORCPT ); Thu, 26 Dec 2019 17:17:46 -0500 Received: by mail-pl1-f195.google.com with SMTP id c13so10964274pls.0 for ; Thu, 26 Dec 2019 14:17:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tubUT90M6ZUsQq/NCNWX8+4auD3W82M3BMPow6ghbj8=; b=UQmFVNA7UILTF3d5FkPUjDuMXwndbRHZm1U93zjabv/K6dGhtSfmt4s9JIg+xMq75d Y23XDZw4It10l4QHXqaDJ2gjQ7UgsgsYKUABY6o6xlTM6PcI9JGpvxzOiNBkPbauQJQX rOb03V74Q2iuvkeRbjoJ25qWSvTN+tewTjT3wPd/ueVoyCzibclmSE33cOkd0g/LLhFE PwN21iKGHN6E0QaX+a9jOmpxp/0FWhAO0E6515STbaiPfJvHp37nOVMDlntvCQ+pVwZD /Ct2qloyyzoXbev8IsVQDmVybAPP5fOQHljHSIHCexni+dNs47E8KE1BxAOlCHWLI6ls AFUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tubUT90M6ZUsQq/NCNWX8+4auD3W82M3BMPow6ghbj8=; b=B4wYxP+8J9wONcX+EGlDY/G6MyIRM/Ictn/lzoQvJReDD5WR5G83ebG0Tqgfn6mOgl LdeGxcCvmOyl0EYIRbWHlgMe5wB7gW2gIocuixjVvXKRWaEA7Tzn8rRYIYZx8g5HI8Ic zF1eSin7ImAzQqxKCwogSIHpKO9Ug29JUcLR7u0APKw8Jk0c9A6zMJmN/ZoS+En0aIas GKVihBZKnebVxR6Axy7bQoJSWqR4yWEtpZY1hYHQUnn7YnS2hAWSRB2zn13Qr/YR4JdO KMG64zTWQ/xfRXNrHL/wPi7GToECpXad9+VCQ82PqwkS+ICmn+SOEF0fY/DXvOjYzSfn adwA== X-Gm-Message-State: APjAAAVHzYd0a8mgPlZyhxMhdCEuHOxUEvJas6n7WGXnqwH0UgZEX54W E/ZJAY8/jWyjnGqO1qmeJmWTAQ== X-Google-Smtp-Source: APXvYqzsnGwMryOZ8OSkxJxnL0bgVLu9XUOFhXRRLNcQ4apGus/dVePA/bPEIWlQsBQNQtZUk1Rydw== X-Received: by 2002:a17:90a:9f04:: with SMTP id n4mr22039896pjp.76.1577398665952; Thu, 26 Dec 2019 14:17:45 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id 2sm11779409pjh.19.2019.12.26.14.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Dec 2019 14:17:45 -0800 (PST) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Patrick Daly , Pratik Patel , Rob Clark Subject: [PATCH 1/3] iommu/arm-smmu: Don't blindly use first SMR to calculate mask Date: Thu, 26 Dec 2019 14:17:07 -0800 Message-Id: <20191226221709.3844244-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191226221709.3844244-1-bjorn.andersson@linaro.org> References: <20191226221709.3844244-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org With the SMRs inherited from the bootloader the first SMR might actually be valid and in use. As such probing the SMR mask using the first SMR might break a stream in use. Search for an unused stream and use this to probe the SMR mask. Signed-off-by: Bjorn Andersson --- Changes since RFC: - Deal with EXIDS - Use arm_smmu_gr0_read/write() drivers/iommu/arm-smmu.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 4f1a350d9529..6ca6a4e072c8 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -945,24 +945,43 @@ static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx) */ static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu) { + u32 s2cr; u32 smr; + int idx; if (!smmu->smrs) return; + for (idx = 0; idx < smmu->num_mapping_groups; idx++) { + if (smmu->features & ARM_SMMU_FEAT_EXIDS) { + s2cr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_S2CR(idx)); + if (!FIELD_GET(S2CR_EXIDVALID, s2cr)) + break; + } else { + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(idx)); + if (!FIELD_GET(SMR_VALID, smr)) + break; + } + } + + if (idx == smmu->num_mapping_groups) { + dev_err(smmu->dev, "Unable to compute streamid_mask\n"); + return; + } + /* * SMR.ID bits may not be preserved if the corresponding MASK * bits are set, so check each one separately. We can reject * masters later if they try to claim IDs outside these masks. */ smr = FIELD_PREP(SMR_ID, smmu->streamid_mask); - arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(0), smr); - smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(0)); + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(idx), smr); + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(idx)); smmu->streamid_mask = FIELD_GET(SMR_ID, smr); smr = FIELD_PREP(SMR_MASK, smmu->streamid_mask); - arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(0), smr); - smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(0)); + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(idx), smr); + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(idx)); smmu->smr_mask_mask = FIELD_GET(SMR_MASK, smr); } From patchwork Thu Dec 26 22:17:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11310759 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0DE7014B7 for ; Thu, 26 Dec 2019 22:17:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF9BC20838 for ; Thu, 26 Dec 2019 22:17:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PovNYG/8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727028AbfLZWRt (ORCPT ); Thu, 26 Dec 2019 17:17:49 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:40581 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727008AbfLZWRt (ORCPT ); Thu, 26 Dec 2019 17:17:49 -0500 Received: by mail-pg1-f196.google.com with SMTP id k25so13487457pgt.7 for ; Thu, 26 Dec 2019 14:17:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=atr5dH9+58H0L1dBqDewFnWoCVnAfiU1TJyN0b3SOLw=; b=PovNYG/8yvcQkau2yxewsi61ZYVYH+xuJSm+1FfpbcX5Lrd0edTC29t1WUNmEMOldi qPeG9Jit/2cej0EQ3S5UwiPB/P81sRwx+kA8476XgyLM5vPpDYODNowEb4qZFqL370i1 nXB/3af9sVFwcCfMTVDORSGSaNQlKr11e+WY4JkXYXKJP5VvY/aqksZoQw0qmCWg2S0s vqwUhMkHrVdcPw4NicoDOQLFcfvb9iF8bkTXnGXxMQHpPYnXN+5TlDya2LAmMPM+fAMa HvLK4DsOixPh0d9iJ2c1bstBsXyJ6sHGcqpJ+oJBaA1BiyxgKAFa91LP4IwOrSkettTv 4fJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=atr5dH9+58H0L1dBqDewFnWoCVnAfiU1TJyN0b3SOLw=; b=SzMHutcnr705HchQ2ZUJd8RChPWe3H4z5eicqYVa7+xpAXj6mtIsiusweQ3nhDd7QI 5C4eyxwXkaAatt2d1nlbTLg32+IGATK86z+O3RtDwU6WkII+4wCVGHXp8AA/1Diekpc4 Mtg/WU6SPctzop1CgnFUtmNQc85sdW2uPa7pWKDMdo1kpqamEU6W4sb1GfALLmbGO0qu H1y1bR6xmpDeTh+N1jTmxi7qF/5g2KulDJsuiekR8cT08eC1V+GcIY+Owev5XYuga/b5 uivzpITeCSGxY7ITjRyNXiOF9QeLdYyDXjmS7KcgmA7yzTH5ltO6yKC3u8F7YtG8EYdS gyoQ== X-Gm-Message-State: APjAAAXILTtk4CxOWiRTbY8IV9wazjXLZNygCwHTEoMNkZQPXgrPiqli qIhVJM1LRpjnv2ee5j0M4P0XYw== X-Google-Smtp-Source: APXvYqxjkphDV74NYDySl7S4Q4EqHt9CrR3SMTKiWnb+uEpFNDfkgplzaC9LAXUDcXRpxSglzDL53A== X-Received: by 2002:a62:3603:: with SMTP id d3mr49051073pfa.37.1577398667182; Thu, 26 Dec 2019 14:17:47 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id 2sm11779409pjh.19.2019.12.26.14.17.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Dec 2019 14:17:46 -0800 (PST) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Patrick Daly , Pratik Patel , Rob Clark Subject: [PATCH 2/3] iommu/arm-smmu: Expose s2cr and smr structs to impl Date: Thu, 26 Dec 2019 14:17:08 -0800 Message-Id: <20191226221709.3844244-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191226221709.3844244-1-bjorn.andersson@linaro.org> References: <20191226221709.3844244-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move the arm_smmu_s2cr and arm_smmu_smr structs to the internal header file, in order to expose them to the platform specific arm-smmu implementations. Signed-off-by: Bjorn Andersson --- Changes since RFC: - New patch drivers/iommu/arm-smmu.c | 14 -------------- drivers/iommu/arm-smmu.h | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 6ca6a4e072c8..9a9091b9dcc7 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -73,24 +73,10 @@ module_param(disable_bypass, bool, S_IRUGO); MODULE_PARM_DESC(disable_bypass, "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU."); -struct arm_smmu_s2cr { - struct iommu_group *group; - int count; - enum arm_smmu_s2cr_type type; - enum arm_smmu_s2cr_privcfg privcfg; - u8 cbndx; -}; - #define s2cr_init_val (struct arm_smmu_s2cr){ \ .type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS, \ } -struct arm_smmu_smr { - u16 mask; - u16 id; - bool valid; -}; - struct arm_smmu_cb { u64 ttbr[2]; u32 tcr[2]; diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index 62b9f0cec49b..73f94579b926 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -224,6 +224,20 @@ enum arm_smmu_implementation { QCOM_SMMUV2, }; +struct arm_smmu_s2cr { + struct iommu_group *group; + int count; + enum arm_smmu_s2cr_type type; + enum arm_smmu_s2cr_privcfg privcfg; + u8 cbndx; +}; + +struct arm_smmu_smr { + u16 mask; + u16 id; + bool valid; +}; + struct arm_smmu_device { struct device *dev; From patchwork Thu Dec 26 22:17:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11310757 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A62EF109A for ; Thu, 26 Dec 2019 22:17:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A8E7208C4 for ; Thu, 26 Dec 2019 22:17:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XnlEYoHl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727066AbfLZWRu (ORCPT ); Thu, 26 Dec 2019 17:17:50 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:34029 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727030AbfLZWRu (ORCPT ); Thu, 26 Dec 2019 17:17:50 -0500 Received: by mail-pg1-f196.google.com with SMTP id r11so13513274pgf.1 for ; Thu, 26 Dec 2019 14:17:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b4nCH35NcICW88DtPeVc2y4BpH7bKLWG0sdpxkzMId4=; b=XnlEYoHlvYt0xMVeZaPgTijBnaigSekfgfAtnotdTaCRtunM8H527mMoDyXDncl0lu gkuFXFWXl7eyAnf8Ym1yn1X8FdyyMFL+tY3KDfIi97Uu1CcIAtqpv62y5tu0yzLalJ0K UdHO/TijyKoBv4xUdzHk4cs+WfuHWyCTn12HRRyIrJDI+nkf+bGC3xM7sr0qPHG1fu8m BWlFoReSGRlBNVUkcqihItsU4JfIUm2coCMm29FuMy5SVNftATpxaIFWK2YViJfiXGBC +rOPVo4CRiOPXUZ/g3dXpJhT+DiH6kvV2ywDCiYSld3ixyUnMMN2015Dw9S3zOGZjenO sifA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b4nCH35NcICW88DtPeVc2y4BpH7bKLWG0sdpxkzMId4=; b=pbU6gj1mr4Isq0cTOB4wn9oABDciUwMrWfcler48Ks+knnQkP67LEQrEA92+VfwYJA BAwdMqsjGA/Od332/Jn6KCcDOxwYNkYfds5auASmSyPfER6LoZOkOH8fgPSkul/3X2lu NSKCJL3u3ol4brNE7Xs8haiCYt6CgmfBXFn7v1LLUrE72ODDoQSfEY0p0XRJjqGBX4zr 29U1OT9v3lo5qUs0k27KXOTlVtzcJdcjxjiQLl4bohJU3NRX0GjsIbYF+v62oDh5gsw4 jz0C+nRAkkdvYSG1GRhfzOg8/bE3P4R/uaFQcCtBhw/Sto1YfnO+mQk2ov9cWekJThfn IF6w== X-Gm-Message-State: APjAAAWv4Mdqt/AGrw5ZElfPvgv0KFgo2l4LBTsHVKn92Lnpi/X0+un0 h19M8YKL8WQKXaDDYYkfP7TVQQ== X-Google-Smtp-Source: APXvYqxgh62ruEOoozlZUPF1Csw6qAEXjVj+daPfQwQTGicHoC82SAgmdsiuM8ZADcIT05YrxH/PMg== X-Received: by 2002:a62:8247:: with SMTP id w68mr42721610pfd.2.1577398668422; Thu, 26 Dec 2019 14:17:48 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id 2sm11779409pjh.19.2019.12.26.14.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Dec 2019 14:17:47 -0800 (PST) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Patrick Daly , Pratik Patel , Rob Clark Subject: [PATCH 3/3] iommu/arm-smmu: Allow inherting stream mapping from bootloader Date: Thu, 26 Dec 2019 14:17:09 -0800 Message-Id: <20191226221709.3844244-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191226221709.3844244-1-bjorn.andersson@linaro.org> References: <20191226221709.3844244-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm bootloaders leaves the IOMMU with stream mapping for the display hardware to be able to read the framebuffer memory in DDR, to continuously display a boot splash or to implement EFI framebuffer. This patch implements support for implementations to pin stream mappings and adds the code to the Qualcomm implementation for reading out the stream mapping from the bootloader, with the result of maintaining the display hardware's access to DDR until the context bank is enabled. Heavily based on downstream implementation by Patrick Daly . Signed-off-by: Bjorn Andersson --- Changes since RFC: - Deal with EXIDS - The onetime handoff has been replaced with a "pinned" state, to deal with probe deferring in the display driver - Reads back s2cr for all groups, not only the "valid" ones drivers/iommu/arm-smmu-qcom.c | 35 +++++++++++++++++++++++++++++++++++ drivers/iommu/arm-smmu.c | 29 +++++++++++++++++++++++------ drivers/iommu/arm-smmu.h | 1 + 3 files changed, 59 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index 24c071c1d8b0..06e5799dcb87 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -3,6 +3,7 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#include #include #include "arm-smmu.h" @@ -11,6 +12,39 @@ struct qcom_smmu { struct arm_smmu_device smmu; }; +static int qcom_sdm845_smmu500_cfg_probe(struct arm_smmu_device *smmu) +{ + u32 s2cr; + u32 smr; + int i; + + for (i = 0; i < smmu->num_mapping_groups; i++) { + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); + s2cr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_S2CR(i)); + + smmu->smrs[i].mask = FIELD_GET(SMR_MASK, smr); + smmu->smrs[i].id = FIELD_GET(SMR_ID, smr); + if (smmu->features & ARM_SMMU_FEAT_EXIDS) + smmu->smrs[i].valid = FIELD_GET(S2CR_EXIDVALID, s2cr); + else + smmu->smrs[i].valid = FIELD_GET(SMR_VALID, smr); + + smmu->s2crs[i].group = NULL; + smmu->s2crs[i].count = 0; + smmu->s2crs[i].type = FIELD_GET(S2CR_TYPE, s2cr); + smmu->s2crs[i].privcfg = FIELD_GET(S2CR_PRIVCFG, s2cr); + smmu->s2crs[i].cbndx = FIELD_GET(S2CR_CBNDX, s2cr); + + if (!smmu->smrs[i].valid) + continue; + + smmu->s2crs[i].pinned = true; + bitmap_set(smmu->context_map, smmu->s2crs[i].cbndx, 1); + } + + return 0; +} + static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) { int ret; @@ -31,6 +65,7 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) } static const struct arm_smmu_impl qcom_smmu_impl = { + .cfg_probe = qcom_sdm845_smmu500_cfg_probe, .reset = qcom_sdm845_smmu500_reset, }; diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 9a9091b9dcc7..01f22eff2ec5 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -206,9 +206,19 @@ static int arm_smmu_register_legacy_master(struct device *dev, return err; } -static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) +static int __arm_smmu_alloc_cb(struct arm_smmu_device *smmu, int start, + struct device *dev) { + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + unsigned long *map = smmu->context_map; + int end = smmu->num_context_banks; int idx; + int i; + + for_each_cfg_sme(fwspec, i, idx) { + if (smmu->s2crs[idx].pinned) + return smmu->s2crs[idx].cbndx; + } do { idx = find_next_zero_bit(map, end, start); @@ -628,7 +638,8 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) } static int arm_smmu_init_domain_context(struct iommu_domain *domain, - struct arm_smmu_device *smmu) + struct arm_smmu_device *smmu, + struct device *dev) { int irq, start, ret = 0; unsigned long ias, oas; @@ -742,8 +753,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, ret = -EINVAL; goto out_unlock; } - ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, - smmu->num_context_banks); + ret = __arm_smmu_alloc_cb(smmu, start, dev); if (ret < 0) goto out_unlock; @@ -1015,12 +1025,19 @@ static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx) { + bool pinned = smmu->s2crs[idx].pinned; + u8 cbndx = smmu->s2crs[idx].cbndx;; + if (--smmu->s2crs[idx].count) return false; smmu->s2crs[idx] = s2cr_init_val; - if (smmu->smrs) + if (pinned) { + smmu->s2crs[idx].pinned = true; + smmu->s2crs[idx].cbndx = cbndx; + } else if (smmu->smrs) { smmu->smrs[idx].valid = false; + } return true; } @@ -1154,7 +1171,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; /* Ensure that the domain is finalised */ - ret = arm_smmu_init_domain_context(domain, smmu); + ret = arm_smmu_init_domain_context(domain, smmu, dev); if (ret < 0) goto rpm_put; diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index 73f94579b926..0701e6875964 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -230,6 +230,7 @@ struct arm_smmu_s2cr { enum arm_smmu_s2cr_type type; enum arm_smmu_s2cr_privcfg privcfg; u8 cbndx; + bool pinned; }; struct arm_smmu_smr {