From patchwork Mon Dec 30 05:32:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11312625 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 43A23109A for ; Mon, 30 Dec 2019 05:33:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1B2562071E for ; Mon, 30 Dec 2019 05:33:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="jGIZbKeg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727126AbfL3Fcw (ORCPT ); Mon, 30 Dec 2019 00:32:52 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:57637 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725834AbfL3Fcw (ORCPT ); Mon, 30 Dec 2019 00:32:52 -0500 X-UUID: 81322c802c744abf8443e2a67cf0bf72-20191230 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=c9VpmytTBWUhbyeGUJ4t0316OksYU3H36qNO5LPrNNg=; b=jGIZbKegTKGyEQvqGCGNzQBxBYYgVOJwjTntbOuYgdbJVEMM8KxJHjSfhiULm16PCI5RVLCdzHlPEjIYOhu3/syoxiv4aPuZDRvMdG6VlO50PlbD1pvxc91LZ6wjlBY3lHtGmJ+luajY9YgIEMStwLYHzD5OdZBA1Oof3c0WV9c=; X-UUID: 81322c802c744abf8443e2a67cf0bf72-20191230 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 889479634; Mon, 30 Dec 2019 13:32:46 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 30 Dec 2019 13:33:20 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 30 Dec 2019 13:31:30 +0800 From: Stanley Chu To: , , , , , , , , CC: , , , , , , , , , , Stanley Chu Subject: [PATCH v2 1/6] soc: mediatek: add header for SiP service interface Date: Mon, 30 Dec 2019 13:32:25 +0800 Message-ID: <1577683950-1702-2-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> References: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Add a common header for the SiP service interface in MediaTek Chipsets. Cc: Alim Akhtar Cc: Avri Altman Cc: Bart Van Assche Cc: Bean Huo Cc: Can Guo Cc: Florian Fainelli Cc: Matthias Brugger Signed-off-by: Stanley Chu --- include/linux/soc/mediatek/mtk_sip_svc.h | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/linux/soc/mediatek/mtk_sip_svc.h diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h new file mode 100644 index 000000000000..082398e0cfb1 --- /dev/null +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + */ +#ifndef __MTK_SIP_SVC_H +#define __MTK_SIP_SVC_H + +/* Error Code */ +#define SIP_SVC_E_SUCCESS 0 +#define SIP_SVC_E_NOT_SUPPORTED -1 +#define SIP_SVC_E_INVALID_PARAMS -2 +#define SIP_SVC_E_INVALID_RANGE -3 +#define SIP_SVC_E_PERMISSION_DENIED -4 + +#ifdef CONFIG_ARM64 +#define MTK_SIP_SMC_CONVENTION ARM_SMCCC_SMC_64 +#else +#define MTK_SIP_SMC_CONVENTION ARM_SMCCC_SMC_32 +#endif + +#define MTK_SIP_SMC_CMD(fn_id) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ + ARM_SMCCC_OWNER_SIP, fn_id) + +#endif From patchwork Mon Dec 30 05:32:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11312637 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1CE6B109A for ; Mon, 30 Dec 2019 05:33:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EF49321744 for ; Mon, 30 Dec 2019 05:33:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="p0BakxZe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727219AbfL3Fc7 (ORCPT ); Mon, 30 Dec 2019 00:32:59 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:60253 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727178AbfL3Fc7 (ORCPT ); Mon, 30 Dec 2019 00:32:59 -0500 X-UUID: 73e27eb881a6497898f52cac3ef29c55-20191230 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=lASBnsWC43Rfu6UB24oYUGd0P99a4d4L+O1D0Rkd/kg=; b=p0BakxZeyUmy4+OrwLlFFIwnpTpmvnZoVDazX1F0Qg56PJUrh4Igyn+7zc/wiknx5mQ0oteUBYquY5u82KvZrWyON6GOpYkVhDMZPYlyze4V3+rt/a1TO5V9Ut/QFQFIF9JyFsfjsIwm3Xrq2ig3b4fqUYxE9YosmZj8SUyTaPE=; X-UUID: 73e27eb881a6497898f52cac3ef29c55-20191230 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 854484596; Mon, 30 Dec 2019 13:32:52 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 30 Dec 2019 13:32:05 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 30 Dec 2019 13:31:31 +0800 From: Stanley Chu To: , , , , , , , , CC: , , , , , , , , , , Stanley Chu Subject: [PATCH v2 2/6] scsi: ufs-mediatek: add device reset implementation Date: Mon, 30 Dec 2019 13:32:26 +0800 Message-ID: <1577683950-1702-3-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> References: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Add device reset vops implementation in MediaTek UFS driver. Cc: Alim Akhtar Cc: Avri Altman Cc: Bart Van Assche Cc: Bean Huo Cc: Can Guo Cc: Florian Fainelli Cc: Matthias Brugger Signed-off-by: Stanley Chu Reviewed-by: Avri Altman --- drivers/scsi/ufs/ufs-mediatek.c | 33 +++++++++++++++++++++++++++++++++ drivers/scsi/ufs/ufs-mediatek.h | 9 +++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 83e28edc3ac5..37e2c91fc452 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -6,16 +6,25 @@ * Peter Wang */ +#include #include #include #include #include +#include #include "ufshcd.h" #include "ufshcd-pltfrm.h" #include "unipro.h" #include "ufs-mediatek.h" +#define ufs_mtk_smc(cmd, val, res) \ + arm_smccc_smc(MTK_SIP_UFS_CONTROL, \ + cmd, val, 0, 0, 0, 0, 0, &(res)) + +#define ufs_mtk_device_reset_ctrl(high, res) \ + ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, high, res) + static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable) { u32 tmp; @@ -269,6 +278,29 @@ static int ufs_mtk_link_startup_notify(struct ufs_hba *hba, return ret; } +static void ufs_mtk_device_reset(struct ufs_hba *hba) +{ + struct arm_smccc_res res; + + ufs_mtk_device_reset_ctrl(0, res); + + /* + * The reset signal is active low. UFS devices shall detect + * more than or equal to 1us of positive or negative RST_n + * pulse width. + * + * To be on safe side, keep the reset low for at least 10us. + */ + usleep_range(10, 15); + + ufs_mtk_device_reset_ctrl(1, res); + + /* Some devices may need time to respond to rst_n */ + usleep_range(10000, 15000); + + dev_info(hba->dev, "device reset done\n"); +} + static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); @@ -303,6 +335,7 @@ static struct ufs_hba_variant_ops ufs_hba_mtk_vops = { .pwr_change_notify = ufs_mtk_pwr_change_notify, .suspend = ufs_mtk_suspend, .resume = ufs_mtk_resume, + .device_reset = ufs_mtk_device_reset, }; /** diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index 19f8c42fe06f..ce68ce25fdd7 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -6,6 +6,9 @@ #ifndef _UFS_MEDIATEK_H #define _UFS_MEDIATEK_H +#include +#include + /* * Vendor specific pre-defined parameters */ @@ -29,6 +32,12 @@ #define VS_SAVEPOWERCONTROL 0xD0A6 #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8 +/* + * SiP commands + */ +#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) +#define UFS_MTK_SIP_DEVICE_RESET BIT(1) + /* * VS_DEBUGCLOCKENABLE */ From patchwork Mon Dec 30 05:32:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11312633 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EE8C921 for ; Mon, 30 Dec 2019 05:33:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4385A222C3 for ; Mon, 30 Dec 2019 05:33:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="oNPS4xmp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727263AbfL3FdG (ORCPT ); Mon, 30 Dec 2019 00:33:06 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:9238 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727213AbfL3FdA (ORCPT ); Mon, 30 Dec 2019 00:33:00 -0500 X-UUID: fa325d3261484dad856316724e1efeda-20191230 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CT6J6Mos8F012MHJEi2dQQCWX4KKKCdgeXYgBRHOS3k=; b=oNPS4xmpH1QbfA/e8MS3EK28wTDCCkRqJxxug7ZWJq/zPG8nSgCOASSfCEFz7Ofdaywx56/0quWdpRJtG3wuG0QiRX7fmXgnNDfPlR1PtGSYhIkjcNV+1Y0DdY2iOm1B1eXMkdIEJktoip0KkHB+1mjaF+TOPVe9B+ERV3K7MlI=; X-UUID: fa325d3261484dad856316724e1efeda-20191230 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1529864162; Mon, 30 Dec 2019 13:32:52 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 30 Dec 2019 13:32:05 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 30 Dec 2019 13:31:37 +0800 From: Stanley Chu To: , , , , , , , , CC: , , , , , , , , , , Stanley Chu Subject: [PATCH v2 3/6] scsi: ufs-mediatek: introduce reference clock control Date: Mon, 30 Dec 2019 13:32:27 +0800 Message-ID: <1577683950-1702-4-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> References: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Introduce reference clock control in MediaTek Chipset in order to disable it if it is not necessary by UFS device to save system power. Currently reference clock can be disabled during system suspend, runtime suspend and clock-gating after link enters hibernate state. Cc: Alim Akhtar Cc: Avri Altman Cc: Bart Van Assche Cc: Bean Huo Cc: Can Guo Cc: Florian Fainelli Cc: Matthias Brugger Signed-off-by: Stanley Chu Reviewed-by: Alim Akhtar --- drivers/scsi/ufs/ufs-mediatek.c | 62 ++++++++++++++++++++++++++++++--- drivers/scsi/ufs/ufs-mediatek.h | 22 ++++++++++-- 2 files changed, 78 insertions(+), 6 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 37e2c91fc452..fc5ba21ec02a 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -22,6 +22,9 @@ arm_smccc_smc(MTK_SIP_UFS_CONTROL, \ cmd, val, 0, 0, 0, 0, 0, &(res)) +#define ufs_mtk_ref_clk_notify(on, res) \ + ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, on, res) + #define ufs_mtk_device_reset_ctrl(high, res) \ ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, high, res) @@ -90,6 +93,49 @@ static int ufs_mtk_bind_mphy(struct ufs_hba *hba) return err; } +static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + struct arm_smccc_res res; + unsigned long timeout; + u32 value; + + if (host->ref_clk_enabled == on) + return 0; + + if (on) { + ufs_mtk_ref_clk_notify(on, res); + ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL); + } else { + ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL); + } + + /* Wait for ack */ + timeout = jiffies + msecs_to_jiffies(REFCLK_REQ_TIMEOUT_MS); + do { + value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL); + + /* Wait until ack bit equals to req bit */ + if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST)) + goto out; + + usleep_range(100, 200); + } while (time_before(jiffies, timeout)); + + dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value); + + ufs_mtk_ref_clk_notify(host->ref_clk_enabled, res); + + return -ETIMEDOUT; + +out: + host->ref_clk_enabled = on; + if (!on) + ufs_mtk_ref_clk_notify(on, res); + + return 0; +} + /** * ufs_mtk_setup_clocks - enables/disable clocks * @hba: host controller instance @@ -114,12 +160,16 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on, switch (status) { case PRE_CHANGE: - if (!on) + if (!on) { + ufs_mtk_setup_ref_clk(hba, on); ret = phy_power_off(host->mphy); + } break; case POST_CHANGE: - if (on) + if (on) { ret = phy_power_on(host->mphy); + ufs_mtk_setup_ref_clk(hba, on); + } break; } @@ -305,8 +355,10 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); - if (ufshcd_is_link_hibern8(hba)) + if (ufshcd_is_link_hibern8(hba)) { phy_power_off(host->mphy); + ufs_mtk_setup_ref_clk(hba, false); + } return 0; } @@ -315,8 +367,10 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); - if (ufshcd_is_link_hibern8(hba)) + if (ufshcd_is_link_hibern8(hba)) { + ufs_mtk_setup_ref_clk(hba, true); phy_power_on(host->mphy); + } return 0; } diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index ce68ce25fdd7..31b7fead19eb 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -9,6 +9,22 @@ #include #include +/* + * Vendor specific UFSHCI Registers + */ +#define REG_UFS_REFCLK_CTRL 0x144 + +/* + * Ref-clk control + * + * Values for register REG_UFS_REFCLK_CTRL + */ +#define REFCLK_RELEASE 0x0 +#define REFCLK_REQUEST BIT(0) +#define REFCLK_ACK BIT(1) + +#define REFCLK_REQ_TIMEOUT_MS 3 + /* * Vendor specific pre-defined parameters */ @@ -35,8 +51,9 @@ /* * SiP commands */ -#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) -#define UFS_MTK_SIP_DEVICE_RESET BIT(1) +#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) +#define UFS_MTK_SIP_DEVICE_RESET BIT(1) +#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) /* * VS_DEBUGCLOCKENABLE @@ -57,6 +74,7 @@ enum { struct ufs_mtk_host { struct ufs_hba *hba; struct phy *mphy; + bool ref_clk_enabled; }; #endif /* !_UFS_MEDIATEK_H */ From patchwork Mon Dec 30 05:32:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11312641 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9536D921 for ; Mon, 30 Dec 2019 05:33:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 733EC21744 for ; Mon, 30 Dec 2019 05:33:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="UkeGjux8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727189AbfL3Fc6 (ORCPT ); Mon, 30 Dec 2019 00:32:58 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:60253 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727175AbfL3Fc5 (ORCPT ); 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Mon, 30 Dec 2019 13:31:37 +0800 From: Stanley Chu To: , , , , , , , , CC: , , , , , , , , , , Stanley Chu Subject: [PATCH v2 4/6] scsi: ufs: export ufshcd_auto_hibern8_update for vendor usage Date: Mon, 30 Dec 2019 13:32:28 +0800 Message-ID: <1577683950-1702-5-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> References: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 97CF5BE00D11748E05E5C3E33B6C4B8E66E050C1BF8D0689055532E9B369AA932000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Export ufshcd_auto_hibern8_update to allow vendors to use common interface to customize auto-hibernate timer. Cc: Alim Akhtar Cc: Avri Altman Cc: Bart Van Assche Cc: Bean Huo Cc: Can Guo Cc: Florian Fainelli Cc: Matthias Brugger Signed-off-by: Stanley Chu Reviewed-by: Asutosh Das Reviewed-by: Alim Akhtar --- drivers/scsi/ufs/ufs-sysfs.c | 20 -------------------- drivers/scsi/ufs/ufshcd.c | 18 ++++++++++++++++++ drivers/scsi/ufs/ufshcd.h | 1 + 3 files changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/scsi/ufs/ufs-sysfs.c b/drivers/scsi/ufs/ufs-sysfs.c index ad2abc96c0f1..720be3f64be7 100644 --- a/drivers/scsi/ufs/ufs-sysfs.c +++ b/drivers/scsi/ufs/ufs-sysfs.c @@ -118,26 +118,6 @@ static ssize_t spm_target_link_state_show(struct device *dev, ufs_pm_lvl_states[hba->spm_lvl].link_state)); } -static void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) -{ - unsigned long flags; - - if (!ufshcd_is_auto_hibern8_supported(hba)) - return; - - spin_lock_irqsave(hba->host->host_lock, flags); - if (hba->ahit != ahit) - hba->ahit = ahit; - spin_unlock_irqrestore(hba->host->host_lock, flags); - if (!pm_runtime_suspended(hba->dev)) { - pm_runtime_get_sync(hba->dev); - ufshcd_hold(hba, false); - ufshcd_auto_hibern8_enable(hba); - ufshcd_release(hba); - pm_runtime_put(hba->dev); - } -} - /* Convert Auto-Hibernate Idle Timer register value to microseconds */ static int ufshcd_ahit_to_us(u32 ahit) { diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index a6936bebb513..ed02a704c1c2 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -3893,6 +3893,24 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) return ret; } +void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) +{ + unsigned long flags; + + if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT)) + return; + + spin_lock_irqsave(hba->host->host_lock, flags); + if (hba->ahit == ahit) + goto out_unlock; + hba->ahit = ahit; + if (!pm_runtime_suspended(hba->dev)) + ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); +out_unlock: + spin_unlock_irqrestore(hba->host->host_lock, flags); +} +EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); + void ufshcd_auto_hibern8_enable(struct ufs_hba *hba) { unsigned long flags; diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index b536a26d665e..e05cafddc87b 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -923,6 +923,7 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, enum flag_idn idn, bool *flag_res); void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); +void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); #define SD_ASCII_STD true #define SD_RAW false From patchwork Mon Dec 30 05:32:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11312631 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9106214BD for ; Mon, 30 Dec 2019 05:33:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6FC9120718 for ; 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Mon, 30 Dec 2019 13:32:52 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 30 Dec 2019 13:32:05 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 30 Dec 2019 13:31:37 +0800 From: Stanley Chu To: , , , , , , , , CC: , , , , , , , , , , Stanley Chu Subject: [PATCH v2 5/6] scsi: ufs-mediatek: configure customized auto-hibern8 timer Date: Mon, 30 Dec 2019 13:32:29 +0800 Message-ID: <1577683950-1702-6-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> References: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Configure customized auto-hibern8 timer in MediaTek Chipsets. Cc: Alim Akhtar Cc: Avri Altman Cc: Bart Van Assche Cc: Bean Huo Cc: Can Guo Cc: Florian Fainelli Cc: Matthias Brugger Signed-off-by: Stanley Chu Reviewed-by: Alim Akhtar --- drivers/scsi/ufs/ufs-mediatek.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index fc5ba21ec02a..1f025723b61b 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -305,6 +306,13 @@ static int ufs_mtk_post_link(struct ufs_hba *hba) /* enable unipro clock gating feature */ ufs_mtk_cfg_unipro_cg(hba, true); + /* configure auto-hibern8 timer to 10ms */ + if (ufshcd_is_auto_hibern8_supported(hba)) { + ufshcd_auto_hibern8_update(hba, + FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) | + FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3)); + } + return 0; } From patchwork Mon Dec 30 05:32:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11312635 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 44E56921 for ; Mon, 30 Dec 2019 05:33:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 23B0720CC7 for ; Mon, 30 Dec 2019 05:33:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="fB8Q1VNy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727256AbfL3FdF (ORCPT ); Mon, 30 Dec 2019 00:33:05 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:37493 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727178AbfL3FdE (ORCPT ); Mon, 30 Dec 2019 00:33:04 -0500 X-UUID: 2c9e0d46941340628726e638ba382d4e-20191230 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zcqo/uUAToxxvQgNL6zzmxHLy2AwGsR7I5v8srG1wtE=; b=fB8Q1VNy9BkcjMm7a40vQb+NWWUYfksb0Hcl7ikKYWnTxXSRUfL4IJn18v0J2eoYUoGe5pr40OYBs83fMNEkc7n8+7l9EfAnfnofrTMcJG63kxclGriURv6y3hptaurb1sOkdxZOG8ju81fyOAy+cuX4gFXvZMW/TsKtCP8WqGs=; X-UUID: 2c9e0d46941340628726e638ba382d4e-20191230 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 582843976; Mon, 30 Dec 2019 13:33:00 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 30 Dec 2019 13:32:10 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 30 Dec 2019 13:31:37 +0800 From: Stanley Chu To: , , , , , , , , CC: , , , , , , , , , , Stanley Chu Subject: [PATCH v2 6/6] scsi: ufs-mediatek: configure and enable clk-gating Date: Mon, 30 Dec 2019 13:32:30 +0800 Message-ID: <1577683950-1702-7-git-send-email-stanley.chu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> References: <1577683950-1702-1-git-send-email-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 2A150414534660147BE3BB69D4F20D1A8206033647AC2FCC00F343D7FC19C24F2000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Enable clk-gating with customized delayed timer value in MediaTek Chipsets. Cc: Alim Akhtar Cc: Avri Altman Cc: Bart Van Assche Cc: Bean Huo Cc: Can Guo Cc: Florian Fainelli Cc: Matthias Brugger Signed-off-by: Stanley Chu Reviewed-by: Alim Akhtar --- drivers/scsi/ufs/ufs-mediatek.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 1f025723b61b..41f80eeada46 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -210,6 +210,9 @@ static int ufs_mtk_init(struct ufs_hba *hba) /* Enable runtime autosuspend */ hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; + /* Enable clock-gating */ + hba->caps |= UFSHCD_CAP_CLK_GATING; + /* * ufshcd_vops_init() is invoked after * ufshcd_setup_clock(true) in ufshcd_hba_init() thus @@ -298,6 +301,23 @@ static int ufs_mtk_pre_link(struct ufs_hba *hba) return ret; } +static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) +{ + unsigned long flags; + u32 ah_ms; + + if (ufshcd_is_clkgating_allowed(hba)) { + if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit) + ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, + hba->ahit); + else + ah_ms = 10; + spin_lock_irqsave(hba->host->host_lock, flags); + hba->clk_gating.delay_ms = ah_ms + 5; + spin_unlock_irqrestore(hba->host->host_lock, flags); + } +} + static int ufs_mtk_post_link(struct ufs_hba *hba) { /* disable device LCC */ @@ -313,6 +333,8 @@ static int ufs_mtk_post_link(struct ufs_hba *hba) FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3)); } + ufs_mtk_setup_clk_gating(hba); + return 0; }