From patchwork Fri Jan 3 08:18:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 11316541 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 942C5139A for ; Fri, 3 Jan 2020 08:18:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 726362464B for ; Fri, 3 Jan 2020 08:18:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="TMVO19DT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727452AbgACISX (ORCPT ); Fri, 3 Jan 2020 03:18:23 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17279 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726054AbgACISW (ORCPT ); Fri, 3 Jan 2020 03:18:22 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 00:17:38 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 00:18:22 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Jan 2020 00:18:22 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 08:18:21 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 08:18:21 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.108.118]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 03 Jan 2020 00:18:20 -0800 From: JC Kuo To: , , , , CC: , , , , , JC Kuo Subject: [PATCH v5 1/5] phy: tegra: xusb: Protect Tegra186 soc with config Date: Fri, 3 Jan 2020 16:18:10 +0800 Message-ID: <20200103081814.9848-2-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103081814.9848-1-jckuo@nvidia.com> References: <20200103081814.9848-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578039458; bh=jtzhgmOSyLlj7voWgVZkhzmevHlkmril+TYqeYqIUAw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=TMVO19DT564EdqdoqBGJfRsE12O2RpJgoAXKOYjwWpjLSM56xjVFXPo6mzcowRGif UoHGSvWygjFgGmKugqYSzPlEUOXwNlrgkKOFehk1GCzquqVXbQnC/+AUCNBaInqDid ukwONRHGhD+Y49e/WYD9oV0f1YnEz5/ftBHnVoNgnfc2GeHapohr54nLZ/yvDW/z71 Vvw4gjXAysMUuUNn807fnDEnsfo/fdS3rZH+wNb+A1gr3PJZWHKpSzpSS0PP4eYXOW wTP6vCplSLSe2sgLfwEPEUpa/ORstOJ6hO72Pj2g7DGAXGYRmX/ia8dVJcv/qTPv9G xH9xwe9vnaqKw== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org As xusb-tegra186.c will be reused for Tegra194, it would be good to protect Tegra186 soc data with CONFIG_ARCH_TEGRA_186_SOC. This commit also reshuffles Tegra186 soc data single CONFIG_ARCH_TEGRA_186_SOC will be sufficient. Signed-off-by: JC Kuo Acked-by: Thierry Reding --- Changes in v5: none Changes in v4: none Changes in v3: none Changes in v2: - new patch to protect Tegra186 soc data with config drivers/phy/tegra/xusb-tegra186.c | 70 ++++++++++++++++--------------- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index 84c27394c181..01f7d979c9a8 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -503,19 +503,6 @@ static const char * const tegra186_usb2_functions[] = { "xusb", }; -static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { - TEGRA186_LANE("usb2-0", 0, 0, 0, usb2), - TEGRA186_LANE("usb2-1", 0, 0, 0, usb2), - TEGRA186_LANE("usb2-2", 0, 0, 0, usb2), -}; - -static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { - .name = "usb2", - .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes), - .lanes = tegra186_usb2_lanes, - .ops = &tegra186_usb2_pad_ops, -}; - static int tegra186_usb2_port_enable(struct tegra_xusb_port *port) { return 0; @@ -765,27 +752,6 @@ static const char * const tegra186_usb3_functions[] = { "xusb", }; -static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { - TEGRA186_LANE("usb3-0", 0, 0, 0, usb3), - TEGRA186_LANE("usb3-1", 0, 0, 0, usb3), - TEGRA186_LANE("usb3-2", 0, 0, 0, usb3), -}; - -static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { - .name = "usb3", - .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes), - .lanes = tegra186_usb3_lanes, - .ops = &tegra186_usb3_pad_ops, -}; - -static const struct tegra_xusb_pad_soc * const tegra186_pads[] = { - &tegra186_usb2_pad, - &tegra186_usb3_pad, -#if 0 /* TODO implement */ - &tegra186_hsic_pad, -#endif -}; - static int tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl) { @@ -885,6 +851,7 @@ static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { .vbus_override = tegra186_xusb_padctl_vbus_override, }; +#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) static const char * const tegra186_xusb_padctl_supply_names[] = { "avdd-pll-erefeut", "avdd-usb", @@ -892,6 +859,40 @@ static const char * const tegra186_xusb_padctl_supply_names[] = { "vddio-hsic", }; +static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { + TEGRA186_LANE("usb2-0", 0, 0, 0, usb2), + TEGRA186_LANE("usb2-1", 0, 0, 0, usb2), + TEGRA186_LANE("usb2-2", 0, 0, 0, usb2), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { + .name = "usb2", + .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes), + .lanes = tegra186_usb2_lanes, + .ops = &tegra186_usb2_pad_ops, +}; + +static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { + TEGRA186_LANE("usb3-0", 0, 0, 0, usb3), + TEGRA186_LANE("usb3-1", 0, 0, 0, usb3), + TEGRA186_LANE("usb3-2", 0, 0, 0, usb3), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { + .name = "usb3", + .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes), + .lanes = tegra186_usb3_lanes, + .ops = &tegra186_usb3_pad_ops, +}; + +static const struct tegra_xusb_pad_soc * const tegra186_pads[] = { + &tegra186_usb2_pad, + &tegra186_usb3_pad, +#if 0 /* TODO implement */ + &tegra186_hsic_pad, +#endif +}; + const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { .num_pads = ARRAY_SIZE(tegra186_pads), .pads = tegra186_pads, @@ -916,6 +917,7 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names), }; EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); +#endif MODULE_AUTHOR("JC Kuo "); MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver"); From patchwork Fri Jan 3 08:18:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 11316549 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 246CE139A for ; Fri, 3 Jan 2020 08:18:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ED9FA2464B for ; Fri, 3 Jan 2020 08:18:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="myhmmAFJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727470AbgACIS1 (ORCPT ); Fri, 3 Jan 2020 03:18:27 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:5964 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726054AbgACIS0 (ORCPT ); Fri, 3 Jan 2020 03:18:26 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 00:18:08 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 00:18:24 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Jan 2020 00:18:24 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 08:18:23 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 08:18:23 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.108.118]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 03 Jan 2020 00:18:23 -0800 From: JC Kuo To: , , , , CC: , , , , , JC Kuo Subject: [PATCH v5 2/5] phy: tegra: xusb: Add Tegra194 support Date: Fri, 3 Jan 2020 16:18:11 +0800 Message-ID: <20200103081814.9848-3-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103081814.9848-1-jckuo@nvidia.com> References: <20200103081814.9848-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578039489; bh=Wed89M0um0gl+T6w+EXfV0IVn5tLZvtKGhYpmGXx9Ig=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=myhmmAFJudE8LNRCxfY1lSTUaM22103hOk5sW8AASS98Eu46//3J24ZmpgCBPT9bd O4VQkjwgUlEKZnUxRJCWsIYr/XhcP8mtwTwPLsTP9BkFE1D5IGTf0CNfvJEOBxHO4V qlC+q2DCEOKecT+5YFB8qnLjMn74B6O5acAaUf1hzWPXpdZqPHFVgbQmygDQy6UBsZ ymhV4zDAsVfMdApLeY0CDAYxDSqDAtTxrOVkjNOkz7S5IVOVwAY7C9M3QmZ8MvoCdE S5RGojIKHkR3pRetmad3EQpgHRWSB9qnIgRLTJ+RVsDLC9Shgg5alH0VGUbT3xLB6R TBixp7ycx5ABw== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add support for the XUSB pad controller found on Tegra194 SoCs. It is mostly similar to the same IP found on Tegra186, but the number of pads exposed differs, as do the programming sequences. Because most of the Tegra194 XUSB PADCTL registers definition and programming sequence are the same as Tegra186, Tegra194 XUSB PADCTL can share the same driver, xusb-tegra186.c, with Tegra186 XUSB PADCTL. Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed". Signed-off-by: JC Kuo --- Changes in v5: - re-use "maximum-speed" instead of adding "nvidia,disable-gen2" Changes in v4: none Changes in v3: none Changes in v2: - removed unnecessary #if/#endif pairs - introduce new soc->supports_gen2 flag which indicate whether or not a soc supports USB 3.1 Gen 2 speed drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 73 +++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb.c | 17 +++++++ drivers/phy/tegra/xusb.h | 5 +++ 4 files changed, 96 insertions(+) diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile index 320dd389f34d..89b84067cb4c 100644 --- a/drivers/phy/tegra/Makefile +++ b/drivers/phy/tegra/Makefile @@ -6,4 +6,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index 01f7d979c9a8..f16016dcd260 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -63,6 +63,10 @@ #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3) #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3) #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3) +#define XUSB_PADCTL_SS_PORT_CFG 0x2c +#define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4) +#define PORTX_SPEED_SUPPORT_MASK (0x3) +#define PORT_SPEED_SUPPORT_GEN1 (0x0) #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40) #define HS_CURR_LEVEL(x) ((x) & 0x3f) @@ -622,6 +626,15 @@ static int tegra186_usb3_phy_power_on(struct phy *phy) padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP); + if (padctl->soc->supports_gen2 && port->disable_gen2) { + value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG); + value &= ~(PORTX_SPEED_SUPPORT_MASK << + PORTX_SPEED_SUPPORT_SHIFT(index)); + value |= (PORT_SPEED_SUPPORT_GEN1 << + PORTX_SPEED_SUPPORT_SHIFT(index)); + padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG); + } + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); value &= ~SSPX_ELPG_VCORE_DOWN(index); padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); @@ -919,6 +932,66 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); #endif +#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) +static const char * const tegra194_xusb_padctl_supply_names[] = { + "avdd-usb", + "vclamp-usb", +}; + +static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = { + TEGRA186_LANE("usb2-0", 0, 0, 0, usb2), + TEGRA186_LANE("usb2-1", 0, 0, 0, usb2), + TEGRA186_LANE("usb2-2", 0, 0, 0, usb2), + TEGRA186_LANE("usb2-3", 0, 0, 0, usb2), +}; + +static const struct tegra_xusb_pad_soc tegra194_usb2_pad = { + .name = "usb2", + .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes), + .lanes = tegra194_usb2_lanes, + .ops = &tegra186_usb2_pad_ops, +}; + +static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = { + TEGRA186_LANE("usb3-0", 0, 0, 0, usb3), + TEGRA186_LANE("usb3-1", 0, 0, 0, usb3), + TEGRA186_LANE("usb3-2", 0, 0, 0, usb3), + TEGRA186_LANE("usb3-3", 0, 0, 0, usb3), +}; + +static const struct tegra_xusb_pad_soc tegra194_usb3_pad = { + .name = "usb3", + .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes), + .lanes = tegra194_usb3_lanes, + .ops = &tegra186_usb3_pad_ops, +}; + +static const struct tegra_xusb_pad_soc * const tegra194_pads[] = { + &tegra194_usb2_pad, + &tegra194_usb3_pad, +}; + +const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = { + .num_pads = ARRAY_SIZE(tegra194_pads), + .pads = tegra194_pads, + .ports = { + .usb2 = { + .ops = &tegra186_usb2_port_ops, + .count = 4, + }, + .usb3 = { + .ops = &tegra186_usb3_port_ops, + .count = 4, + }, + }, + .ops = &tegra186_xusb_padctl_ops, + .supply_names = tegra194_xusb_padctl_supply_names, + .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), + .supports_gen2 = true, +}; +EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc); +#endif + MODULE_AUTHOR("JC Kuo "); MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index f98ec3922c02..90b8fb187cf4 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -65,6 +65,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = { .compatible = "nvidia,tegra186-xusb-padctl", .data = &tegra186_xusb_padctl_soc, }, +#endif +#if defined(CONFIG_ARCH_TEGRA_194_SOC) + { + .compatible = "nvidia,tegra194-xusb-padctl", + .data = &tegra194_xusb_padctl_soc, + }, #endif { } }; @@ -726,6 +732,7 @@ static int tegra_xusb_usb3_port_parse_dt(struct tegra_xusb_usb3_port *usb3) { struct tegra_xusb_port *port = &usb3->base; struct device_node *np = port->dev.of_node; + enum usb_device_speed maximum_speed; u32 value; int err; @@ -739,6 +746,16 @@ static int tegra_xusb_usb3_port_parse_dt(struct tegra_xusb_usb3_port *usb3) usb3->internal = of_property_read_bool(np, "nvidia,internal"); + if (device_property_present(&port->dev, "maximum-speed")) { + maximum_speed = usb_get_maximum_speed(&port->dev); + if (maximum_speed == USB_SPEED_SUPER) + usb3->disable_gen2 = true; + else if (maximum_speed == USB_SPEED_SUPER_PLUS) + usb3->disable_gen2 = false; + else + return -EINVAL; + } + usb3->supply = devm_regulator_get(&port->dev, "vbus"); return PTR_ERR_OR_ZERO(usb3->supply); } diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index da94fcce6307..e2152d4f1dbf 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -333,6 +333,7 @@ struct tegra_xusb_usb3_port { bool context_saved; unsigned int port; bool internal; + bool disable_gen2; u32 tap1; u32 amp; @@ -392,6 +393,7 @@ struct tegra_xusb_padctl_soc { const char * const *supply_names; unsigned int num_supplies; + bool supports_gen2; bool need_fake_usb3_port; }; @@ -448,5 +450,8 @@ extern const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc; #if defined(CONFIG_ARCH_TEGRA_186_SOC) extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc; #endif +#if defined(CONFIG_ARCH_TEGRA_194_SOC) +extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc; +#endif #endif /* __PHY_TEGRA_XUSB_H */ From patchwork Fri Jan 3 08:18:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 11316547 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 08803139A for ; Fri, 3 Jan 2020 08:18:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9B542464E for ; Fri, 3 Jan 2020 08:18:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="gXirWtxS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727479AbgACIS2 (ORCPT ); Fri, 3 Jan 2020 03:18:28 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17285 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726295AbgACIS1 (ORCPT ); Fri, 3 Jan 2020 03:18:27 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 00:17:42 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 00:18:26 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Jan 2020 00:18:26 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 08:18:25 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 08:18:25 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.108.118]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 03 Jan 2020 00:18:25 -0800 From: JC Kuo To: , , , , CC: , , , , , JC Kuo Subject: [PATCH v5 3/5] dt-bindings: phy: tegra: Add Tegra194 support Date: Fri, 3 Jan 2020 16:18:12 +0800 Message-ID: <20200103081814.9848-4-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103081814.9848-1-jckuo@nvidia.com> References: <20200103081814.9848-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578039462; bh=iYyIXUxkirPSBJ7iu5TXTf34bSdyG8fxwUBD40kVdj0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=gXirWtxSFL6a5mIjmhdwWMybAMIgl1VUE9k5qaaUwQktt40sNHmgYer3xBdKDqfxR NagZurg4X6ZUzbaklOtPMpiMen8U7/xdETMWnZkTRHAhBEaTldB0W8qebz5rwhqVim r0o/AS5HHcfc3LY6KI62w/UcDsuc2P/rSTWMkz77mVDJpFNrCX271kusEB8gvNgNhO 1IGxqdKmKtMKY4GjEB6rgm5S3w5d2S2pp0q3wteg694/iVDKqmEjNnphpzaY5K0p55 TkiZLhFZPQzB3Ormvc/dqCeLzQjO0DEibLbM6bRp45xQlQ+OqatEwfghIJPrM/S+l4 18kuZh6G5eUJg== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Extend the bindings to cover the set of features found in Tegra194. Note that, technically, there are four more supplies connected to the XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL) , but the power sequencing requirements of Tegra194 require these to be under the control of the PMIC. Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed". Signed-off-by: JC Kuo --- Changes in v5: - re-use "maximum-speed" instead of adding "nvidia,disable-gen2" Changes in v4: none Changes in v3: none Changes in v2: - fix a typo .../phy/nvidia,tegra124-xusb-padctl.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt index 9fb682e47c29..7d0089006e67 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt @@ -37,6 +37,7 @@ Required properties: - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - Tegra210: "nvidia,tegra210-xusb-padctl" - Tegra186: "nvidia,tegra186-xusb-padctl" + - Tegra194: "nvidia,tegra194-xusb-padctl" - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. - reset-names: Must include the following entries: @@ -62,6 +63,10 @@ For Tegra186: - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V. +For Tegra194: +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply + 3.3 V. +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. Pad nodes: ========== @@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below: - sata: sata-0 - functions: "usb3-ss", "sata" +For Tegra194, the list of valid PHY nodes is given below: +- usb2: usb2-0, usb2-1, usb2-2, usb2-3 + - functions: "xusb" +- usb3: usb3-0, usb3-1, usb3-2, usb3-3 + - functions: "xusb" Port nodes: =========== @@ -221,6 +231,11 @@ Optional properties: is internal. In the absence of this property the port is considered to be external. +- maximum-speed: Only for Tegra194. A string property that specifies maximum + supported speed of a usb3 port. Valid values are: + - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed. + - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only. + For Tegra124 and Tegra132, the XUSB pad controller exposes the following ports: - 3x USB2: usb2-0, usb2-1, usb2-2 @@ -233,6 +248,9 @@ For Tegra210, the XUSB pad controller exposes the following ports: - 2x HSIC: hsic-0, hsic-1 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 +For Tegra194, the XUSB pad controller exposes the following ports: +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 Examples: ========= From patchwork Fri Jan 3 08:18:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 11316543 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5095C139A for ; Fri, 3 Jan 2020 08:18:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2F40722B48 for ; Fri, 3 Jan 2020 08:18:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="qJlSI+5W" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727506AbgACISc (ORCPT ); Fri, 3 Jan 2020 03:18:32 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:5058 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727488AbgACIS3 (ORCPT ); Fri, 3 Jan 2020 03:18:29 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 00:18:13 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 00:18:28 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Jan 2020 00:18:28 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 08:18:28 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 08:18:28 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.108.118]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 03 Jan 2020 00:18:27 -0800 From: JC Kuo To: , , , , CC: , , , , , JC Kuo Subject: [PATCH v5 4/5] arm64: tegra: Add XUSB and pad controller on Tegra194 Date: Fri, 3 Jan 2020 16:18:13 +0800 Message-ID: <20200103081814.9848-5-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103081814.9848-1-jckuo@nvidia.com> References: <20200103081814.9848-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578039493; bh=nmyzhD/f6mjDJQHt5dzAuBpxUM7e/MZRpBL0Z2t3sWI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=qJlSI+5WOGjDPcMrpv9cSo93dAHvLbYSOhLKRoaXFKjQ9r1B0kiPlwcO4rRXhCsZ/ 7QQHoMI1NFkxT4AZCqDgm+Qrndb4yC4Ci9RIjTHJgEX3hNqVzolUSkSg75a5fsafsD +FLxkvQ1eeN8gnoDWowU0svWHotCrm9ijege8BcSRyz6o9DIGV9J/OHRo7ZzoMf/Vc donuv2a8fISR3MAyS292TAIMpPGnhaIOwF7HFmBGmVOjJztci8TZ7e66T2RKgnxciT triUIpcTgaNWM3RvIVpYwpUZiP7fjGGedlFlTdnxqR4I6GQ5lznjln1UWsw+ayIAbr uUsJp0EksJA6Q== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Adds the XUSB pad and XUSB controllers on Tegra194. Signed-off-by: JC Kuo --- Changes in v5: none Changes in v4: none Changes in v3: none Changes in v2: - renamed xhci@3610000 with usb@3610000 - moved padctl@3520000 and usb@3610000 inside /cbb - cleaned up "clocks" property of usb@3610000 node - added blanks lines to visually separate blocks arch/arm64/boot/dts/nvidia/tegra194.dtsi | 139 +++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 11220d97adb8..495f692e6a0b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -488,6 +488,145 @@ status = "disabled"; }; + xusb_padctl: padctl@3520000 { + compatible = "nvidia,tegra194-xusb-padctl"; + reg = <0x03520000 0x1000>, + <0x03540000 0x1000>; + reg-names = "padctl", "ao"; + + resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + + usb@3610000 { + compatible = "nvidia,tegra194-xusb"; + reg = <0x03610000 0x40000>, + < 0x03600000 0x10000>; + reg-names = "hcd", "fpci"; + + interrupts = , + , + ; + + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA194_CLK_XUSB_FALCON>, + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA194_CLK_XUSB_SS>, + <&bpmp TEGRA194_CLK_CLK_M>, + <&bpmp TEGRA194_CLK_XUSB_FS>, + <&bpmp TEGRA194_CLK_UTMIPLL>, + <&bpmp TEGRA194_CLK_CLK_M>, + <&bpmp TEGRA194_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; + gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From patchwork Fri Jan 3 08:18:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 11316545 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F30A6930 for ; Fri, 3 Jan 2020 08:18:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D16C02464E for ; Fri, 3 Jan 2020 08:18:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="c7rQivYZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727516AbgACISh (ORCPT ); Fri, 3 Jan 2020 03:18:37 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17291 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726295AbgACISb (ORCPT ); Fri, 3 Jan 2020 03:18:31 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 00:17:47 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 00:18:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Jan 2020 00:18:30 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 08:18:30 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 08:18:30 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.108.118]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 03 Jan 2020 00:18:29 -0800 From: JC Kuo To: , , , , CC: , , , , , JC Kuo Subject: [PATCH v5 5/5] arm64: tegra: Enable XUSB host in P2972-0000 board Date: Fri, 3 Jan 2020 16:18:14 +0800 Message-ID: <20200103081814.9848-6-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103081814.9848-1-jckuo@nvidia.com> References: <20200103081814.9848-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578039467; bh=HFCFVfUkHlCBFcm+mlAAgYHn7YBPtjgDr4lQB1CTZcw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=c7rQivYZa+VBoaZTJTfKUIU5r4NIWxXDCZ1jzkLX4H7tz0eLb3toVyTcTPKa/bll0 wBXAFEtQp/O2S7UjylZ7HDfx0lLcmLk/du5V+aGFjXOiDU6j/kqBFJBRtRWpuhloOx odULfqHugoVkI3LFm9+1Tz4s4mNDb8OhbsMLElOcjsUOhqOPPg5h2qFj/7Ja9pxzSV 2+fFsgg/7GEuisXGKEPWwllLftyGWv0/gn4CZtwUa0k7izYoByDb1Fm4hriPpoE1Z1 nCeIc9Amg30z4C+GNXhYHIPKyV4JYoAFrriCYiGZ8SI5HNZ6KU9RwKJBJ8mD/UoBxU PwbIcciaHh2hQ== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org This commit enables XUSB host and pad controller in Tegra194 P2972-0000 board. Signed-off-by: JC Kuo --- Changes in v5: none Changes in v4: none Changes in v3: none Changes in v2: - use capitalization of regulator names - fix gpio property of VDD_5V_SATA regulator .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 ++++++++++- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 63 +++++++++++++++++++ 2 files changed, 98 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index c7f2a20e6b02..014e18b2d52a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -67,6 +67,29 @@ vmmc-supply = <&vdd_emmc_3v3>; }; + padctl@3520000 { + avdd-usb-supply = <&vdd_usb_3v3>; + vclamp-usb-supply = <&vdd_1v8ao>; + + ports { + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + vbus-supply = <&vdd_5v_sata>; + }; + + usb3-0 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb3-3 { + vbus-supply = <&vdd_5v0_sys>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; }; @@ -230,7 +253,7 @@ regulator-max-microvolt = <3300000>; }; - ldo5 { + vdd_usb_3v3: ldo5 { regulator-name = "VDD_USB_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -313,5 +336,16 @@ gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>; regulator-boot-on; }; + + vdd_5v_sata: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + + regulator-name = "VDD_5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 353a6a22196d..2cbcae39d1b0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -37,6 +37,69 @@ status = "okay"; }; + padctl@3520000 { + status = "okay"; + + pads { + usb2 { + lanes { + usb2-1 { + status = "okay"; + }; + + usb2-3 { + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + status = "okay"; + }; + + usb3-3 { + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-1 { + mode = "host"; + status = "okay"; + }; + + usb2-3 { + mode = "host"; + status = "okay"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + + usb3-3 { + nvidia,usb2-companion = <3>; + nvidia,disable-gen2; + status = "okay"; + }; + }; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-3}>; + phy-names = "usb2-1", "usb2-3", "usb3-0", "usb3-3"; + }; + pwm@c340000 { status = "okay"; };