From patchwork Fri Jan 3 10:07:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11316739 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CC7ED6C1 for ; Fri, 3 Jan 2020 10:07:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A57FA206DB for ; Fri, 3 Jan 2020 10:07:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="I8wE0jsk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727313AbgACKHx (ORCPT ); Fri, 3 Jan 2020 05:07:53 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:9099 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727221AbgACKHw (ORCPT ); Fri, 3 Jan 2020 05:07:52 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 02:07:36 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 02:07:51 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Jan 2020 02:07:51 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 10:07:51 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 10:07:51 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.48]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 03 Jan 2020 02:07:50 -0800 From: Vidya Sagar To: , , , , , , CC: , , , , , , , Subject: [PATCH V2 1/5] PCI: endpoint: Add core init notifying feature Date: Fri, 3 Jan 2020 15:37:32 +0530 Message-ID: <20200103100736.27627-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103100736.27627-1-vidyas@nvidia.com> References: <20200103100736.27627-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578046056; bh=ZGS66YvIi/B+9woRlbOt3YnbjLoJjEyLMauJaqifX90=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=I8wE0jskqTddrVj4uYAJ0Qpjj1lPU4AAe6VrirwQPtwO3DwEk+O2vq9O9sKr8mfP8 4SUEEFY1DqwB99Ies9m2G571NkSJeX1c7iytlPwucwYngb0nXAZPVW/XaAWx7csSmo A/IRTOTEm8iR5AqRHvT5o8ST5VQSHReDMJcuYmxRvIIr/jY0wbIVFGoGm8jEPuTZJT xU6rMMNzHdI94s1y2H+4/88807z7WDtSECAIDL43izWdpBBYurafYBjV2Lpl2/S4zh SjaZoM+HQumESF1/GWSAMhA7mDPRD05rQeyBuamcEOGwbHBAvFpE+Lc7xi1hl/z41g UnFa7uInhOXbw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add a new feature core_init_notifier for cores that can notify about their availability for initialization (Ex:- Tegra194). Signed-off-by: Vidya Sagar --- V2: * This is a new patch in this series include/linux/pci-epc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 36644ccd32ac..ec8d4d896564 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -115,6 +115,7 @@ struct pci_epc { */ struct pci_epc_features { unsigned int linkup_notifier : 1; + unsigned int core_init_notifier : 1; unsigned int msi_capable : 1; unsigned int msix_capable : 1; u8 reserved_bar; From patchwork Fri Jan 3 10:07:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11316743 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1EF56C1 for ; Fri, 3 Jan 2020 10:07:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9634B21D7D for ; Fri, 3 Jan 2020 10:07:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="iWe/sUAQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727539AbgACKH6 (ORCPT ); Fri, 3 Jan 2020 05:07:58 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:2362 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727221AbgACKH6 (ORCPT ); Fri, 3 Jan 2020 05:07:58 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 02:07:13 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 02:07:57 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 03 Jan 2020 02:07:57 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 10:07:56 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 10:07:56 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.48]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 03 Jan 2020 02:07:56 -0800 From: Vidya Sagar To: , , , , , , CC: , , , , , , , Subject: [PATCH V2 2/5] PCI: dwc: Refactor core initialization code for EP mode Date: Fri, 3 Jan 2020 15:37:33 +0530 Message-ID: <20200103100736.27627-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103100736.27627-1-vidyas@nvidia.com> References: <20200103100736.27627-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578046033; bh=jC+jVFEIhEm9CKmOx1bqAgrHEJ74z8k/IwNBM3Cv20w=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=iWe/sUAQag0bLCAEcACXzQAujuLm78mNTsZ4zR82hM3WohEaCJuWmrXL9BMGDJMBt oz10bAzud1T6cF5A97IvGS+oEcBE83QTMJKUBcg/kcq6zrU8Etnm1sr5SBtvgx3/Dp NOeQxylP7ZG3WXoJXL/w/c4LfhlATyjXU3pB3ZXW2LRu3MHezRBVeILD0Rad4AcwMa aGMyg2T959BcOpGlWuY08Qf+Jxm7ewNszfFaHL4fwtyEz/IkXiDJjMwPocBWTf7uDN 0Z72k9IlCXsWyzwIqu2z0YwsjvlN47rNeAbnMdxbiTu9r5k9EpIFE2MVYIyF/RXAs7 Yop3XyBJUeaCg== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Splits core initialization code for EP mode into two, one that doesn't touch core registers and the other that touches core registers. The latter would be called/skipped based on the EPC feature 'core_init_notifier'. In case of platforms where this is skipped (Ex:- Tegra194), it would be called indirectly through hooks from the function driver. Signed-off-by: Vidya Sagar --- V2: * Changed EPC feature name from 'skip_core_init' to 'core_init_notifier' * Made the pci-epc.h header file change as a separate patch as per the review comment from Kishon .../pci/controller/dwc/pcie-designware-ep.c | 72 +++++++++++-------- drivers/pci/controller/dwc/pcie-designware.h | 6 ++ 2 files changed, 50 insertions(+), 28 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 3dd2e2697294..c0ff34e5a1e3 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -492,19 +492,53 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) return 0; } -int dw_pcie_ep_init(struct dw_pcie_ep *ep) +int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) { + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + unsigned int offset; + unsigned int nbars; + u8 hdr_type; + u32 reg; int i; + + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); + if (hdr_type != PCI_HEADER_TYPE_NORMAL) { + dev_err(pci->dev, + "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", + hdr_type); + return -EIO; + } + + ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); + + ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX); + + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (offset) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + dw_pcie_dbi_ro_wr_en(pci); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); + dw_pcie_dbi_ro_wr_dis(pci); + } + + dw_pcie_setup(pci); + + return 0; +} + +int dw_pcie_ep_init(struct dw_pcie_ep *ep) +{ int ret; - u32 reg; void *addr; - u8 hdr_type; - unsigned int nbars; - unsigned int offset; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; struct device_node *np = dev->of_node; + const struct pci_epc_features *epc_features; if (!pci->dbi_base || !pci->dbi_base2) { dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); @@ -563,13 +597,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ep->ops->ep_init) ep->ops->ep_init(ep); - hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); - if (hdr_type != PCI_HEADER_TYPE_NORMAL) { - dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", - hdr_type); - return -EIO; - } - ret = of_property_read_u8(np, "max-functions", &epc->max_functions); if (ret < 0) epc->max_functions = 1; @@ -587,23 +614,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); return -ENOMEM; } - ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); - ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX); - - offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); - if (offset) { - reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); - nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> - PCI_REBAR_CTRL_NBAR_SHIFT; - - dw_pcie_dbi_ro_wr_en(pci); - for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) - dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); - dw_pcie_dbi_ro_wr_dis(pci); + if (ep->ops->get_features) { + epc_features = ep->ops->get_features(ep); + if (epc_features->core_init_notifier) + return 0; } - dw_pcie_setup(pci); - - return 0; + return dw_pcie_ep_init_complete(ep); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 5accdd6bc388..340783e9032e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -399,6 +399,7 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp) #ifdef CONFIG_PCIE_DW_EP void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); int dw_pcie_ep_init(struct dw_pcie_ep *ep); +int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep); void dw_pcie_ep_exit(struct dw_pcie_ep *ep); int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no); int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, @@ -416,6 +417,11 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep) return 0; } +static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) +{ + return 0; +} + static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) { } From patchwork Fri Jan 3 10:07:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11316745 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA8151398 for ; Fri, 3 Jan 2020 10:08:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A8E3024650 for ; Fri, 3 Jan 2020 10:08:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="XHumTBBO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727546AbgACKIE (ORCPT ); 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Fri, 03 Jan 2020 02:08:01 -0800 From: Vidya Sagar To: , , , , , , CC: , , , , , , , Subject: [PATCH V2 3/5] PCI: endpoint: Add notification for core init completion Date: Fri, 3 Jan 2020 15:37:34 +0530 Message-ID: <20200103100736.27627-4-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103100736.27627-1-vidyas@nvidia.com> References: <20200103100736.27627-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578046067; bh=Ha+bcuXGrM0L03R3lRVubmjiE0J+PZcOB0XAy0EUE5c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=XHumTBBOq4zk1kksPblE5ZUSUrzLSmEl8wbn906VZpik6Gzt+DFwwioE8PzD+qHVa LNKWGidyu34JtJAAyOU7EdmV38tiE2JDajYDQ+hYryyLI4tMObAGjxXYd48caSrbE+ gIDZSKuUXKAokHF+2804e8fniTT9AzfD4+F1EWSfNu9LW/LSHzja/s+opScSHn4ROW AA3ZrZ0tie/6Phd3lT9Y/uxG8dVhgG7kpSUH4E5fjoUqsV5f0tnBF4+ezRNCp1lymc HKPH8Gzo+JwdfKcxLG7b0/2eW84q2PIN59Ao4em/fuU8vYMXzdTOOVRCuFTQtOJCcD lwsLSqddEHtvw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to send notifications to EPF from EPC once the core registers initialization is complete. Signed-off-by: Vidya Sagar --- V2: * None drivers/pci/endpoint/pci-epc-core.c | 19 ++++++++++++++++++- include/linux/pci-epc.h | 1 + include/linux/pci-epf.h | 5 +++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 2f6436599fcb..fcc3f7fb19c0 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -542,10 +542,27 @@ void pci_epc_linkup(struct pci_epc *epc) if (!epc || IS_ERR(epc)) return; - atomic_notifier_call_chain(&epc->notifier, 0, NULL); + atomic_notifier_call_chain(&epc->notifier, LINK_UP, NULL); } EXPORT_SYMBOL_GPL(pci_epc_linkup); +/** + * pci_epc_init_notify() - Notify the EPF device that EPC device's core + * initialization is completed. + * @epc: the EPC device whose core initialization is completeds + * + * Invoke to Notify the EPF device that the EPC device's initialization + * is completed. + */ +void pci_epc_init_notify(struct pci_epc *epc) +{ + if (!epc || IS_ERR(epc)) + return; + + atomic_notifier_call_chain(&epc->notifier, CORE_INIT, NULL); +} +EXPORT_SYMBOL_GPL(pci_epc_init_notify); + /** * pci_epc_destroy() - destroy the EPC device * @epc: the EPC device that has to be destroyed diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index ec8d4d896564..31cdae7e2cdd 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -160,6 +160,7 @@ void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc); void pci_epc_destroy(struct pci_epc *epc); int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf); void pci_epc_linkup(struct pci_epc *epc); +void pci_epc_init_notify(struct pci_epc *epc); void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf); int pci_epc_write_header(struct pci_epc *epc, u8 func_no, struct pci_epf_header *hdr); diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 4993f7f6439b..3cb65ac1648c 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -15,6 +15,11 @@ struct pci_epf; +enum pci_notify_event { + CORE_INIT, + LINK_UP, +}; + enum pci_barno { BAR_0, BAR_1, From patchwork Fri Jan 3 10:07:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11316747 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45E3B1395 for ; Fri, 3 Jan 2020 10:08:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 255BC227BF for ; Fri, 3 Jan 2020 10:08:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="gkjYgYM7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727456AbgACKIJ (ORCPT ); Fri, 3 Jan 2020 05:08:09 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:9129 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725972AbgACKIJ (ORCPT ); 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Fri, 03 Jan 2020 02:08:07 -0800 From: Vidya Sagar To: , , , , , , CC: , , , , , , , Subject: [PATCH V2 4/5] PCI: dwc: Add API to notify core initialization completion Date: Fri, 3 Jan 2020 15:37:35 +0530 Message-ID: <20200103100736.27627-5-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103100736.27627-1-vidyas@nvidia.com> References: <20200103100736.27627-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578046072; bh=rXEzoZ1bhsdsA/OpJsdAky0XHTUMrsxzH/65Q+vvZ7E=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=gkjYgYM7Dt6qaLHRgivWxoirFryCDoMtrGplfNiIM6Vdl/NCe8Vhj/2SR52nEHI6b 5Zw83S1BPur84xADWzQDh5xEatMPd+WpwlCEOri0TGQdn3u+1YNoRXDhJz4fEbeA9J 774hXf5Cg2xoVrNDaKIivLik/eiXddWQZ2vZLd5WLEOp5j2dQHYJxivGjr2opALZG0 O4/fv44kmykXQ6ZIUJhd/MPd37RjxI2WST3bTaAT+7v4i6h8uncifq5TT8IGiRXwSL eil9VNv7rSjXbTiex6QBhElNOuG2ytANcWcxZl4XavpeB7AyOuZb+tW/FGIgpLcLFL jXfnoXcP4pbvQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add a new API dw_pcie_ep_init_notify() to let platform drivers call it when the core is available for initialization. Signed-off-by: Vidya Sagar --- V2: * None drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++++ drivers/pci/controller/dwc/pcie-designware.h | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index c0ff34e5a1e3..9da2689e77df 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -19,6 +19,13 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) pci_epc_linkup(epc); } +void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) +{ + struct pci_epc *epc = ep->epc; + + pci_epc_init_notify(epc); +} + static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar, int flags) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 340783e9032e..f62c5bae6b2d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -400,6 +400,7 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp) void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); int dw_pcie_ep_init(struct dw_pcie_ep *ep); int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep); +void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep); void dw_pcie_ep_exit(struct dw_pcie_ep *ep); int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no); int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, @@ -422,6 +423,10 @@ static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) return 0; } +static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) +{ +} + static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) { } From patchwork Fri Jan 3 10:07:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11316749 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35A3D6C1 for ; Fri, 3 Jan 2020 10:08:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 080ED22314 for ; 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Fri, 3 Jan 2020 10:08:13 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 10:08:13 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.48]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 03 Jan 2020 02:08:13 -0800 From: Vidya Sagar To: , , , , , , CC: , , , , , , , Subject: [PATCH V2 5/5] PCI: pci-epf-test: Add support to defer core initialization Date: Fri, 3 Jan 2020 15:37:36 +0530 Message-ID: <20200103100736.27627-6-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103100736.27627-1-vidyas@nvidia.com> References: <20200103100736.27627-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578046078; bh=82bxgHehHs+lQ3XjqHsqxJ/EXb2nno7xCFyteu5Ons8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=OwafoHuGQRsJeuQ6jcxz80XbT5xaif/So4yAIRHcAoTO095evhv380AXU1bzHSshM 5MaRhYBXBUHz77WqnjMQhu0sFwx9urFv62sfUPflHptrSA7x+FBlTRJ4YAjAHpEnnp q01Dng/gby+0DYMtW9/SZNsxCW0PH3LOH6a512w3uGakJ0VR4Vyh06zg6CRAh+zwVA EsKTbLjrTXDbOK5s0d+sisxmTwqf7ldKiC93qvBLz1M/miGZifi3ZVGEF8xmuRsgsn LAz/uUH53lgnFTMhzNFwjiAb8DNRAHb53IDrfb4PfEOiiBZIcavA5MuJ6TNAYTKl2t JbVfVhNedWhKA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to defer core initialization and to receive a notifier when core is ready to accommodate platforms where core is not for initialization untile reference clock from host is available. Signed-off-by: Vidya Sagar --- V2: * Addressed review comments from Kishon drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------ 1 file changed, 77 insertions(+), 41 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index bddff15052cc..be04c6220265 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -360,18 +360,6 @@ static void pci_epf_test_cmd_handler(struct work_struct *work) msecs_to_jiffies(1)); } -static int pci_epf_test_notifier(struct notifier_block *nb, unsigned long val, - void *data) -{ - struct pci_epf *epf = container_of(nb, struct pci_epf, nb); - struct pci_epf_test *epf_test = epf_get_drvdata(epf); - - queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler, - msecs_to_jiffies(1)); - - return NOTIFY_OK; -} - static void pci_epf_test_unbind(struct pci_epf *epf) { struct pci_epf_test *epf_test = epf_get_drvdata(epf); @@ -428,6 +416,78 @@ static int pci_epf_test_set_bar(struct pci_epf *epf) return 0; } +static int pci_epf_test_core_init(struct pci_epf *epf) +{ + struct pci_epf_header *header = epf->header; + const struct pci_epc_features *epc_features; + struct pci_epc *epc = epf->epc; + struct device *dev = &epf->dev; + bool msix_capable = false; + bool msi_capable = true; + int ret; + + epc_features = pci_epc_get_features(epc, epf->func_no); + if (epc_features) { + msix_capable = epc_features->msix_capable; + msi_capable = epc_features->msi_capable; + } + + ret = pci_epc_write_header(epc, epf->func_no, header); + if (ret) { + dev_err(dev, "Configuration header write failed\n"); + return ret; + } + + ret = pci_epf_test_set_bar(epf); + if (ret) + return ret; + + if (msi_capable) { + ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts); + if (ret) { + dev_err(dev, "MSI configuration failed\n"); + return ret; + } + } + + if (msix_capable) { + ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts); + if (ret) { + dev_err(dev, "MSI-X configuration failed\n"); + return ret; + } + } + + return 0; +} + +static int pci_epf_test_notifier(struct notifier_block *nb, unsigned long val, + void *data) +{ + struct pci_epf *epf = container_of(nb, struct pci_epf, nb); + struct pci_epf_test *epf_test = epf_get_drvdata(epf); + int ret; + + switch (val) { + case CORE_INIT: + ret = pci_epf_test_core_init(epf); + if (ret) + return NOTIFY_BAD; + break; + + case LINK_UP: + queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler, + msecs_to_jiffies(1)); + break; + + default: + dev_err(&epf->dev, "Invalid EPF test notifier event\n"); + return NOTIFY_BAD; + } + + return NOTIFY_OK; +} + static int pci_epf_test_alloc_space(struct pci_epf *epf) { struct pci_epf_test *epf_test = epf_get_drvdata(epf); @@ -496,14 +556,11 @@ static int pci_epf_test_bind(struct pci_epf *epf) { int ret; struct pci_epf_test *epf_test = epf_get_drvdata(epf); - struct pci_epf_header *header = epf->header; const struct pci_epc_features *epc_features; enum pci_barno test_reg_bar = BAR_0; struct pci_epc *epc = epf->epc; - struct device *dev = &epf->dev; bool linkup_notifier = false; - bool msix_capable = false; - bool msi_capable = true; + bool core_init_notifier = false; if (WARN_ON_ONCE(!epc)) return -EINVAL; @@ -511,8 +568,7 @@ static int pci_epf_test_bind(struct pci_epf *epf) epc_features = pci_epc_get_features(epc, epf->func_no); if (epc_features) { linkup_notifier = epc_features->linkup_notifier; - msix_capable = epc_features->msix_capable; - msi_capable = epc_features->msi_capable; + core_init_notifier = epc_features->core_init_notifier; test_reg_bar = pci_epc_get_first_free_bar(epc_features); pci_epf_configure_bar(epf, epc_features); } @@ -520,34 +576,14 @@ static int pci_epf_test_bind(struct pci_epf *epf) epf_test->test_reg_bar = test_reg_bar; epf_test->epc_features = epc_features; - ret = pci_epc_write_header(epc, epf->func_no, header); - if (ret) { - dev_err(dev, "Configuration header write failed\n"); - return ret; - } - ret = pci_epf_test_alloc_space(epf); if (ret) return ret; - ret = pci_epf_test_set_bar(epf); - if (ret) - return ret; - - if (msi_capable) { - ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts); - if (ret) { - dev_err(dev, "MSI configuration failed\n"); - return ret; - } - } - - if (msix_capable) { - ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts); - if (ret) { - dev_err(dev, "MSI-X configuration failed\n"); + if (!core_init_notifier) { + ret = pci_epf_test_core_init(epf); + if (ret) return ret; - } } if (linkup_notifier) {