From patchwork Mon Jan 6 15:33:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11319505 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A58651395 for ; Mon, 6 Jan 2020 15:33:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A56120848 for ; Mon, 6 Jan 2020 15:33:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="2OCluKsl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726524AbgAFPdg (ORCPT ); Mon, 6 Jan 2020 10:33:36 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:36777 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726437AbgAFPdg (ORCPT ); Mon, 6 Jan 2020 10:33:36 -0500 Received: by mail-wm1-f66.google.com with SMTP id p17so15703064wma.1 for ; Mon, 06 Jan 2020 07:33:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=0JRPiNtt3u1fwu5304YsC27D9nzp3GtGxqufyN7DwQ0=; b=2OCluKsl58KRcqFE6zYcG9FIghU5uAMvt9h9Dob1L3VF4wbkucoqlpCvqhOrYhwc1M MMsfHmPriEJnFDCl0sWgru29pJDg0Wf3uQTJjIG9QC/QxVbCW4HqqAk2Jq50Ex6CNlkS PAUOKb5XuoWtHWJ6lO8wry9LC//n23ufR0HKOi0vr+kcHIWSmL8tI802e/3Vc9jamB1Z nqfpyR63uLMV0OzVaUfqMszg7lvUfJq5b36U5m+XmTN+VlWA7H3yKfBKlrDeWj0fCAET BYUiZyGkHdJrvkd8bXvEAI11OoIJ3w91vDW1/X7c5X5NGYvcaPGXMHXpxOGDG0BQGsMn oxfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=0JRPiNtt3u1fwu5304YsC27D9nzp3GtGxqufyN7DwQ0=; b=UoUrHnlVE58+qbfcYF7+9icY7xivs4zcY6EAYLwXt3YhoyGmZRhixmLZk36M8ZnjmW FxoEWwiTiqgtEAd1yojt/h5RTvTbZOZZ/BzVcV8g1kXdn2hxxauMePOoaXXktP/6GYMn 99BtBWyiZNjGLw9zH+m9KgBXxyPzZhc7Kt8ipSH+cZQWYdjZyzLR5XOuSrC5TDqIouaN tJYPI6T7pegQc++W2GJ5VywYPZ4/F/TGHaQ6UDsW7oHJiwoUE+vSVpdcnYwEbItsBfD5 GjiR8/nWTrSzCJVwW06c7X94kuYo7gnMHtm1UWGppZozhJMiTuA/wW96M8KglSlClyLk ib2w== X-Gm-Message-State: APjAAAWvyxPqSdVN49Vvr1IhATkRBoScSEgFOiVwH3l9kqE4xtKokaIs QAz5IHiQe9FOzywVmJ5BWdlrfbfBl1o= X-Google-Smtp-Source: APXvYqzJQmAgT5lJh3TebYCZ/Hl140NWSL2zkP18c1OOEc/RvoVgYrWKYqtN1nBykrpR4ypJx+zitw== X-Received: by 2002:a1c:9d52:: with SMTP id g79mr35332858wme.148.1578324812800; Mon, 06 Jan 2020 07:33:32 -0800 (PST) Received: from localhost.localdomain (93-137-254-179.adsl.net.t-com.hr. [93.137.254.179]) by smtp.googlemail.com with ESMTPSA id m10sm73578046wrx.19.2020.01.06.07.33.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jan 2020 07:33:32 -0800 (PST) From: Robert Marko To: agross@kernel.org, linux-arm-msm@vger.kernel.org Cc: Robert Marko , John Crispin , Luka Perkov Subject: [PATCH 1/3] phy: add driver for Qualcomm IPQ40xx USB PHY Date: Mon, 6 Jan 2020 16:33:23 +0100 Message-Id: <20200106153325.1281420-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a driver to setup the USB phy on Qualcom Dakota SoCs. The driver sets up HS and SS phys. In case of HS some magic values need to be written to magic offsets. These were taken from the SDK driver. Signed-off-by: John Crispin Tested-by: Robert Marko Cc: Luka Perkov --- drivers/phy/qualcomm/Kconfig | 7 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 180 ++++++++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index e46824da29f6..964bd5d784d2 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -18,6 +18,13 @@ config PHY_QCOM_APQ8064_SATA depends on OF select GENERIC_PHY +config PHY_QCOM_IPQ4019_USB + tristate "Qualcomm IPQ4019 USB PHY module" + depends on OF && ARCH_QCOM + select GENERIC_PHY + help + Support for the USB PHY on QCOM IPQ4019/Dakota chipsets. + config PHY_QCOM_IPQ806X_SATA tristate "Qualcomm IPQ806x SATA SerDes/PHY driver" depends on ARCH_QCOM diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 283251d6a5d9..8afe6c4f5178 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o +obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c new file mode 100644 index 000000000000..eddea2901062 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2018 John Crispin + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Magic registers copied from the SDK driver code + */ +#define PHY_CTRL0_ADDR 0x000 +#define PHY_CTRL1_ADDR 0x004 +#define PHY_CTRL2_ADDR 0x008 +#define PHY_CTRL3_ADDR 0x00C +#define PHY_CTRL4_ADDR 0x010 +#define PHY_MISC_ADDR 0x024 +#define PHY_IPG_ADDR 0x030 + +#define PHY_CTRL0_VAL 0xA4600015 +#define PHY_CTRL1_VAL 0x09500000 +#define PHY_CTRL2_VAL 0x00058180 +#define PHY_CTRL3_VAL 0x6DB6DCD6 +#define PHY_CTRL4_VAL 0x836DB6DB +#define PHY_MISC_VAL 0x3803FB0C +#define PHY_IPG_VAL 0x47323232 + +struct ipq4019_usb_phy { + struct device *dev; + struct phy *phy; + void __iomem *base; + struct reset_control *por_rst; + struct reset_control *srif_rst; +}; + +static int ipq4019_ss_phy_power_off(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + reset_control_assert(phy->por_rst); + msleep(10); + + return 0; +} + +static int ipq4019_ss_phy_power_on(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + ipq4019_ss_phy_power_off(_phy); + + reset_control_deassert(phy->por_rst); + + return 0; +} + +static struct phy_ops ipq4019_usb_ss_phy_ops = { + .power_on = ipq4019_ss_phy_power_on, + .power_off = ipq4019_ss_phy_power_off, +}; + +static int ipq4019_hs_phy_power_off(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + reset_control_assert(phy->por_rst); + msleep(10); + + reset_control_assert(phy->srif_rst); + msleep(10); + + return 0; +} + +static int ipq4019_hs_phy_power_on(struct phy *_phy) +{ + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + + ipq4019_hs_phy_power_off(_phy); + + reset_control_deassert(phy->srif_rst); + msleep(10); + + writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR); + writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR); + writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR); + writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR); + writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR); + writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR); + writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR); + msleep(10); + + reset_control_deassert(phy->por_rst); + + return 0; +} + +static struct phy_ops ipq4019_usb_hs_phy_ops = { + .power_on = ipq4019_hs_phy_power_on, + .power_off = ipq4019_hs_phy_power_off, +}; + +static const struct of_device_id ipq4019_usb_phy_of_match[] = { + { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops}, + { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops}, + { }, +}; +MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match); + +static int ipq4019_usb_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct phy_provider *phy_provider; + struct ipq4019_usb_phy *phy; + const struct of_device_id *match; + + match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev); + if (!match) + return -ENODEV; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->dev = &pdev->dev; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + phy->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(phy->base)) { + dev_err(dev, "failed to remap register memory\n"); + return PTR_ERR(phy->base); + } + + phy->por_rst = devm_reset_control_get(phy->dev, "por_rst"); + if (IS_ERR(phy->por_rst)) { + if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER) + dev_err(dev, "POR reset is missing\n"); + return PTR_ERR(phy->por_rst); + } + + phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst"); + if (IS_ERR(phy->srif_rst)) + return PTR_ERR(phy->srif_rst); + + phy->phy = devm_phy_create(dev, NULL, match->data); + if (IS_ERR(phy->phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(phy->phy); + } + phy_set_drvdata(phy->phy, phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static struct platform_driver ipq4019_usb_phy_driver = { + .probe = ipq4019_usb_phy_probe, + .driver = { + .of_match_table = ipq4019_usb_phy_of_match, + .name = "ipq4019-usb-phy", + } +}; +module_platform_driver(ipq4019_usb_phy_driver); + +MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver"); +MODULE_AUTHOR("John Crispin "); +MODULE_LICENSE("GPL v2"); From patchwork Mon Jan 6 15:33:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11319507 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D19D013A0 for ; Mon, 6 Jan 2020 15:33:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AEEF920848 for ; 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[93.137.254.179]) by smtp.googlemail.com with ESMTPSA id m10sm73578046wrx.19.2020.01.06.07.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jan 2020 07:33:35 -0800 (PST) From: Robert Marko To: agross@kernel.org, linux-arm-msm@vger.kernel.org Cc: Robert Marko , John Crispin , Luka Perkov Subject: [PATCH 2/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document Date: Mon, 6 Jan 2020 16:33:24 +0100 Message-Id: <20200106153325.1281420-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200106153325.1281420-1-robert.marko@sartura.hr> References: <20200106153325.1281420-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the binding documentation for the HS/SS USB PHY found inside Qualcom Dakota SoCs. Signed-off-by: John Crispin Signed-off-by: Robert Marko Cc: Luka Perkov --- .../bindings/phy/qcom-usb-ipq4019-phy.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml new file mode 100644 index 000000000000..6473731b07a1 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcom IPQ40xx Dakota HS/SS USB PHY + +properties: + compatible: + enum: + - qcom,usb-ss-ipq4019-phy + - qcom,usb-hs-ipq4019-phy + + reg: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: por_rst + - const: srif_rst + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - resets + - reset-names + - "#phy-cells" + +examples: + - | + hsphy@a8000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + phy-cells = <0>; + reg = <0xa8000 0x40>; + resets = <&gcc USB2_HSPHY_POR_ARES>, + <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + }; From patchwork Mon Jan 6 15:33:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11319511 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 92FC91395 for ; Mon, 6 Jan 2020 15:33:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 67747207FF for ; Mon, 6 Jan 2020 15:33:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="ad7ngc5b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726510AbgAFPdj (ORCPT ); Mon, 6 Jan 2020 10:33:39 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:35180 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726508AbgAFPdi (ORCPT ); Mon, 6 Jan 2020 10:33:38 -0500 Received: by mail-wm1-f67.google.com with SMTP id p17so15719585wmb.0 for ; Mon, 06 Jan 2020 07:33:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2FYYv2CkjElFAYjDohnfSrEmf3CiiM23ViUusDP3kSQ=; b=ad7ngc5bJlE2n14Gj3b6Nfl+1n/vamPfIE28LrpGnOINIuNlv4ZpkLTzsG01cjeOxD 04NydcE/20B74uze1n0R3/D8WGh+AWEDrj/I4Zkf5UEFFGOHAjtsLJQyJx3cOW4vJnGh ZGk5OxsrjOualJD663Vd7hQiLdM3Zu+GusBfo+yBrwZGEUhGZncW/0uszYJKS42m3OlL AsrLDa0/GJiijYoQpPxmbu7niC1PQnjWA9gJWPTLgmA7bnPc2eDyFGTu9RZFmP+xnfO7 vdcGtIcfrDj1j/6fB3flYaEuresllRrFb5UQ+6X8X06uXrBCxpO4MRqZvEndP4155hFL DT8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2FYYv2CkjElFAYjDohnfSrEmf3CiiM23ViUusDP3kSQ=; b=Hr93CpRxNOgDrY34XksAhMZ25HUdH9t164X36xONG/dFgKZQkApn/sUuVRMAW0iHbw x5nb26QB1SYMJ1DD1Stb/cRZXG+oXCNMzhX4tCn06Zn8R7kvsq/tTtDXcuxke75mCjGG 3W1TJIK030EMkNzIYZZnuJVZfSyztOAVVqYJ9kH3RYCHFhE73zXpIsOVVvlnt+MO/p2t o+khGdeIJwmyBAywixe2nI4J7cZoMfHD5hH8hoTvd5neLlK4Em9/CQ9P4XtN8hJTo213 YxC4zNNDHXgEBjYGMOEcvqrVcvVutf/h4/1hoSI1h55SJQcAPZp2GioB68J33L8XTjrG 3yfw== X-Gm-Message-State: APjAAAUc63YJXYoObeKyGpF8Jn961JSNMIgWSJtnHR+Zk1oe2irj4ZHf NaJsybLuClp3tTWIfIPBcjw1oe00tpQ= X-Google-Smtp-Source: APXvYqwPv3zhWtJa0TFdN+kGJD964mS2gB2guJpl6uLx998eyRVoyp+IVBPYPpaNn/KJ8LusyT5lOg== X-Received: by 2002:a05:600c:2298:: with SMTP id 24mr36197375wmf.65.1578324816974; Mon, 06 Jan 2020 07:33:36 -0800 (PST) Received: from localhost.localdomain (93-137-254-179.adsl.net.t-com.hr. [93.137.254.179]) by smtp.googlemail.com with ESMTPSA id m10sm73578046wrx.19.2020.01.06.07.33.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jan 2020 07:33:36 -0800 (PST) From: Robert Marko To: agross@kernel.org, linux-arm-msm@vger.kernel.org Cc: John Crispin , Robert Marko , Luka Perkov Subject: [PATCH 3/3] ARM: dts: qcom: ipq4019: add USB devicetree nodes Date: Mon, 6 Jan 2020 16:33:25 +0100 Message-Id: <20200106153325.1281420-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200106153325.1281420-1-robert.marko@sartura.hr> References: <20200106153325.1281420-1-robert.marko@sartura.hr> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: John Crispin Since we now have driver for the USB PHY, lets add the necessary nodes to DTSI. Signed-off-by: John Crispin Tested-by: Robert Marko Cc: Luka Perkov --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 +++++ arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 418f9a022336..2ee5f05d5a43 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -109,5 +109,25 @@ wifi@a800000 { status = "ok"; }; + + usb3_ss_phy: ssphy@9a000 { + status = "ok"; + }; + + usb3_hs_phy: hsphy@a6000 { + status = "ok"; + }; + + usb3: usb3@8af8800 { + status = "ok"; + }; + + usb2_hs_phy: hsphy@a8000 { + status = "ok"; + }; + + usb2: usb2@60f8800 { + status = "ok"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index b6e5203a210b..18e9c639514c 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -564,5 +564,79 @@ "legacy"; status = "disabled"; }; + + usb3_ss_phy: ssphy@9a000 { + compatible = "qcom,usb-ss-ipq4019-phy"; + #phy-cells = <0>; + reg = <0x9a000 0x800>; + reg-names = "phy_base"; + resets = <&gcc USB3_UNIPHY_PHY_ARES>; + reset-names = "por_rst"; + status = "disabled"; + }; + + usb3_hs_phy: hsphy@a6000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa6000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb3@8af8800 { + compatible = "qcom,dwc3"; + reg = <0x8af8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB3_MASTER_CLK>, + <&gcc GCC_USB3_SLEEP_CLK>, + <&gcc GCC_USB3_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xf8000>; + interrupts = ; + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + }; + }; + + usb2_hs_phy: hsphy@a8000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa8000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb2@60f8800 { + compatible = "qcom,dwc3"; + reg = <0x60f8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB2_MASTER_CLK>, + <&gcc GCC_USB2_SLEEP_CLK>, + <&gcc GCC_USB2_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@6000000 { + compatible = "snps,dwc3"; + reg = <0x6000000 0xf8000>; + interrupts = ; + phys = <&usb2_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + }; + }; }; };