From patchwork Tue Jan 7 04:48:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320359 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC7CD6C1 for ; Tue, 7 Jan 2020 04:53:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 839632075A for ; Tue, 7 Jan 2020 04:53:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="XnO7c4g4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 839632075A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iogrZ-0003JE-U3 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jan 2020 23:53:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44130) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognI-0005Kg-Ao for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognH-0004ch-9C for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:40 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:34477 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognG-0004Vu-VC; Mon, 06 Jan 2020 23:48:39 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdX1c7qz9sRf; Tue, 7 Jan 2020 15:48:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372512; bh=TfQTmXYbC8QhW9e6z4YK15NqUFRWl/4wKLoSPI7wBfQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XnO7c4g4M44yHzlm8HFUJdT1t8yBD1JJUIv4f/H6ea5UdulOLl/a0Fj/x4pA4k8tx cX5jQEHsEuRUvezFlGXaqYdNdU7jRbzmej68JtpD3KVwrjqt05HCssABHpYi6RRTPH zXOYuFc3RYQ7NisC2MjmKy7sDlhDI3uJwseIJpZg= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 01/10] ppc: Drop PPC_EMULATE_32BITS_HYPV stub Date: Tue, 7 Jan 2020 15:48:18 +1100 Message-Id: <20200107044827.471355-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The only effect of the PPC_EMULATE_32BITS_HYPV define is to change how MSR_HVB is defined. This appears to be something to handle hypervisor mode for 32-bit CPUs, but there's really no other code to handle this. The MSR_THV bit, which it uses is implemented for no cpus we model. It's unlikely anyone is going to implement this any time soon, so just drop it. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/cpu.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 103bfe9dc2..2de9e2fa2b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -26,8 +26,6 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" -/* #define PPC_EMULATE_32BITS_HYPV */ - #define TCG_GUEST_DEFAULT_MO 0 #define TARGET_PAGE_BITS_64K 16 @@ -450,14 +448,9 @@ typedef struct ppc_v3_pate_t { #define MSR_HVB (1ULL << MSR_SHV) #define msr_hv msr_shv #else -#if defined(PPC_EMULATE_32BITS_HYPV) -#define MSR_HVB (1ULL << MSR_THV) -#define msr_hv msr_thv -#else #define MSR_HVB (0ULL) #define msr_hv (0) #endif -#endif /* DSISR */ #define DSISR_NOPTE 0x40000000 From patchwork Tue Jan 7 04:48:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320397 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5FCA814B4 for ; Tue, 7 Jan 2020 04:56:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2BBFE2075A for ; Tue, 7 Jan 2020 04:56:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="crhWWj77" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2BBFE2075A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iogvB-0000Wy-04 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jan 2020 23:56:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44126) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognI-0005K4-F8 for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognG-0004bT-NS for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:39 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:34365 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognG-0004Vq-30; Mon, 06 Jan 2020 23:48:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdX0QB4z9sRG; Tue, 7 Jan 2020 15:48:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372512; bh=hKHBL40fvquvop2W00XL2m4WOhOqI+ZG7iI5VyXxM7g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=crhWWj776waB4cRfVhWnKO6O/GXfdyo36re9dP4K8bJDvimHKEbFw/mNuvhu3qu17 mwD7K5qqPPAzMob87rWVKi/3w/rGj3fWw0NAy7koNkbk85kh/Vrb2LeLhkO2Qv61V1 uuyy2taKkTRcsqh9eoMoXp8pykFhfrbmQi4xYNH0= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 02/10] ppc: Remove stub of PPC970 HID4 implementation Date: Tue, 7 Jan 2020 15:48:19 +1100 Message-Id: <20200107044827.471355-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor capability. However, it can be (and often was) strapped into "Apple mode", where the hypervisor capabilities were disabled (essentially putting it always in hypervisor mode). That's actually the only mode of the 970 we support in qemu, and we're unlikely to change that any time soon. However, we do have a partial implementation of the 970's HID4 register which affects things only relevant for hypervisor mode. That stub is also really ugly, since it attempts to duplicate the effects of HID4 by re-encoding it into the LPCR register used in newer CPUs, but in a really confusing way. Just get rid of it. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz --- target/ppc/mmu-hash64.c | 28 +--------------------------- target/ppc/translate_init.inc.c | 17 ++++++----------- 2 files changed, 7 insertions(+), 38 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index da8966ccf5..a881876647 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1091,33 +1091,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) /* Filter out bits */ switch (env->mmu_model) { - case POWERPC_MMU_64B: /* 970 */ - if (val & 0x40) { - lpcr |= LPCR_LPES0; - } - if (val & 0x8000000000000000ull) { - lpcr |= LPCR_LPES1; - } - if (val & 0x20) { - lpcr |= (0x4ull << LPCR_RMLS_SHIFT); - } - if (val & 0x4000000000000000ull) { - lpcr |= (0x2ull << LPCR_RMLS_SHIFT); - } - if (val & 0x2000000000000000ull) { - lpcr |= (0x1ull << LPCR_RMLS_SHIFT); - } - env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26; - - /* - * XXX We could also write LPID from HID4 here - * but since we don't tag any translation on it - * it doesn't actually matter - * - * XXX For proper emulation of 970 we also need - * to dig HRMOR out of HID5 - */ - break; case POWERPC_MMU_2_03: /* P5p */ lpcr = val & (LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | @@ -1154,6 +1127,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) } break; default: + g_assert_not_reached(); ; } env->spr[SPR_LPCR] = lpcr; diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index d33d65dff7..436d0d5a51 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -7884,25 +7884,20 @@ static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) { gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); } - -static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn) -{ -#if defined(TARGET_PPC64) - spr_write_generic(ctx, sprn, gprn); - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); -#endif -} - #endif /* !defined(CONFIG_USER_ONLY) */ static void gen_spr_970_lpar(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) /* Logical partitionning */ - /* PPC970: HID4 is effectively the LPCR */ + /* PPC970: HID4 covers things later controlled by the LPCR and + * RMOR in later CPUs, but with a different encoding. We only + * support the 970 in "Apple mode" which has all hypervisor + * facilities disabled by strapping, so we can basically just + * ignore it */ spr_register(env, SPR_970_HID4, "HID4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_970_hid4, + &spr_read_generic, &spr_write_generic, 0x00000000); #endif } From patchwork Tue Jan 7 04:48:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320357 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5794D14B4 for ; Tue, 7 Jan 2020 04:53:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2EAEA2075A for ; Tue, 7 Jan 2020 04:53:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Sm8u3hyL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2EAEA2075A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iogrc-0003MJ-Fh for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jan 2020 23:53:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44127) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognI-0005KP-Bm for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognG-0004be-Q8 for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:40 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:50599) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognG-0004W7-CJ; Mon, 06 Jan 2020 23:48:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdX3k6bz9sRk; Tue, 7 Jan 2020 15:48:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372512; bh=UomTOzzCLUxQKFOwa15TEphgpgzlVFcF75Lx2wGRjBg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Sm8u3hyL2RMEaNDYnmaEFBZKnwpbrpk2C23JpOjpnvhJ77SA03lxlDj14k7fOM989 giOizVEde4BEdk5AkUgGwK8gjteXsnzo/EIpCuDWrai4ZMzpWB6WhKA8OFIOFLwVPK G0hAxCOr8RjafHMeU+/B8i6/0E8QP/g4fL9OZTf0= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 03/10] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU Date: Tue, 7 Jan 2020 15:48:20 +1100 Message-Id: <20200107044827.471355-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" On ppc we have the concept of virtual hypervisor ("vhyp") mode, where we only model the non-hypervisor-privileged parts of the cpu. Essentially we model the hypervisor's behaviour from the point of view of a guest OS, but we don't model the hypervisor's execution. In particular, in this mode, qemu's notion of target physical address is a guest physical address from the vcpu's point of view. So accesses in guest real mode don't require translation. If we were modelling the hypervisor mode, we'd need to translate the guest physical address into a host physical address. Currently, we handle this sloppily: we rely on setting up the virtual LPCR and RMOR registers so that GPAs are simply HPAs plus an offset, which we set to zero. This is already conceptually dubious, since the LPCR and RMOR registers don't exist in the non-hypervisor portion of the CPU. It gets worse with POWER9, where RMOR and LPCR[VPM0] no longer exist at all. Clean this up by explicitly handling the vhyp case. While we're there, remove some unnecessary nesting of if statements that made the logic to select the correct real mode behaviour a bit less clear than it could be. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/mmu-hash64.c | 60 ++++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index a881876647..5fabd93c92 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -789,27 +789,30 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, */ raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; - /* In HV mode, add HRMOR if top EA bit is clear */ - if (msr_hv || !env->has_hv_mode) { + if (cpu->vhyp) { + /* + * In virtual hypervisor mode, there's nothing to do: + * EA == GPA == qemu guest address + */ + } else if (msr_hv || !env->has_hv_mode) { + /* In HV mode, add HRMOR if top EA bit is clear */ if (!(eaddr >> 63)) { raddr |= env->spr[SPR_HRMOR]; } - } else { - /* Otherwise, check VPM for RMA vs VRMA */ - if (env->spr[SPR_LPCR] & LPCR_VPM0) { - slb = &env->vrma_slb; - if (slb->sps) { - goto skip_slb_search; - } - /* Not much else to do here */ + } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + /* Emulated VRMA mode */ + slb = &env->vrma_slb; + if (!slb->sps) { + /* Invalid VRMA setup, machine check */ cs->exception_index = POWERPC_EXCP_MCHECK; env->error_code = 0; return 1; - } else if (raddr < env->rmls) { - /* RMA. Check bounds in RMLS */ - raddr |= env->spr[SPR_RMOR]; - } else { - /* The access failed, generate the approriate interrupt */ + } + + goto skip_slb_search; + } else { + /* Emulated old-style RMO mode, bounds check against RMLS */ + if (raddr >= env->rmls) { if (rwx == 2) { ppc_hash64_set_isi(cs, SRR1_PROTFAULT); } else { @@ -821,6 +824,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, } return 1; } + + raddr |= env->spr[SPR_RMOR]; } tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, @@ -953,22 +958,27 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) /* In real mode the top 4 effective address bits are ignored */ raddr = addr & 0x0FFFFFFFFFFFFFFFULL; - /* In HV mode, add HRMOR if top EA bit is clear */ - if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { + if (cpu->vhyp) { + /* + * In virtual hypervisor mode, there's nothing to do: + * EA == GPA == qemu guest address + */ + return raddr; + } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { + /* In HV mode, add HRMOR if top EA bit is clear */ return raddr | env->spr[SPR_HRMOR]; - } - - /* Otherwise, check VPM for RMA vs VRMA */ - if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + /* Emulated VRMA mode */ slb = &env->vrma_slb; if (!slb->sps) { return -1; } - } else if (raddr < env->rmls) { - /* RMA. Check bounds in RMLS */ - return raddr | env->spr[SPR_RMOR]; } else { - return -1; + /* Emulated old-style RMO mode, bounds check against RMLS */ + if (raddr >= env->rmls) { + return -1; + } + return raddr | env->spr[SPR_RMOR]; } } else { slb = slb_lookup(cpu, addr); From patchwork Tue Jan 7 04:48:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320401 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B1F4930 for ; Tue, 7 Jan 2020 04:59:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 21E8B2075A for ; Tue, 7 Jan 2020 04:59:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="bKpvvZO9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 21E8B2075A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iogxl-000412-Kv for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jan 2020 23:59:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44129) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognI-0005Ke-B5 for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognH-0004cC-04 for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:40 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:50579 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognG-0004W5-3c; Mon, 06 Jan 2020 23:48:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdX2qlrz9sRW; Tue, 7 Jan 2020 15:48:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372512; bh=BUqhshOcWk+Swa3UXK3WA+Ekx9g6BOIPl7hkmltSymM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bKpvvZO9+2vGH3YmTQ8TW7DN1tB6seHLA+lc6H2hOnU56uJ9eWyD7rQfAFt9tFJF4 9nXJTkBCxRKaue/XYwX4qQEUjOtR93DNlgDI7lQd2r17+Hjm6h5jkhiX4jiz/kGFA2 m68ORdSQQm1hgQMit7M6Oie6gLZIhjPZz8BnyFvc= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 04/10] target/ppc: Introduce ppc_hash64_use_vrma() helper Date: Tue, 7 Jan 2020 15:48:21 +1100 Message-Id: <20200107044827.471355-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" When running guests under a hypervisor, the hypervisor obviously needs to be protected from guest accesses even if those are in what the guest considers real mode (translation off). The POWER hardware provides two ways of doing that: The old way has guest real mode accesses simply offset and bounds checked into host addresses. It works, but requires that a significant chunk of the guest's memory - the RMA - be physically contiguous in the host, which is pretty inconvenient. The new way, known as VRMA, has guest real mode accesses translated in roughly the normal way but with some special parameters. In POWER7 and POWER8 the LPCR[VPM0] bit selected between the two modes, but in POWER9 only VRMA mode is supported and LPCR[VPM0] no longer exists. We handle that difference in behaviour in ppc_hash64_set_isi().. but not in other places that we blindly check LPCR[VPM0]. Correct those instances with a new helper to tell if we should be in VRMA mode. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/mmu-hash64.c | 41 +++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 5fabd93c92..d878180df5 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -668,6 +668,19 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, return 0; } +static bool ppc_hash64_use_vrma(CPUPPCState *env) +{ + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR + * register no longer exist */ + return true; + + default: + return !!(env->spr[SPR_LPCR] & LPCR_VPM0); + } +} + static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) { CPUPPCState *env = &POWERPC_CPU(cs)->env; @@ -676,15 +689,7 @@ static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) if (msr_ir) { vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - switch (env->mmu_model) { - case POWERPC_MMU_3_00: - /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ - vpm = true; - break; - default: - vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); - break; - } + vpm = ppc_hash64_use_vrma(env); } if (vpm && !msr_hv) { cs->exception_index = POWERPC_EXCP_HISI; @@ -702,15 +707,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr) if (msr_dr) { vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - switch (env->mmu_model) { - case POWERPC_MMU_3_00: - /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ - vpm = true; - break; - default: - vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); - break; - } + vpm = ppc_hash64_use_vrma(env); } if (vpm && !msr_hv) { cs->exception_index = POWERPC_EXCP_HDSI; @@ -799,7 +796,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, if (!(eaddr >> 63)) { raddr |= env->spr[SPR_HRMOR]; } - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ slb = &env->vrma_slb; if (!slb->sps) { @@ -967,7 +964,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { /* In HV mode, add HRMOR if top EA bit is clear */ return raddr | env->spr[SPR_HRMOR]; - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ slb = &env->vrma_slb; if (!slb->sps) { @@ -1056,8 +1053,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) slb->sps = NULL; /* Is VRMA enabled ? */ - lpcr = env->spr[SPR_LPCR]; - if (!(lpcr & LPCR_VPM0)) { + if (ppc_hash64_use_vrma(env)) { return; } @@ -1065,6 +1061,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) * Make one up. Mostly ignore the ESID which will not be needed * for translation */ + lpcr = env->spr[SPR_LPCR]; vsid = SLB_VSID_VRMA; vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); From patchwork Tue Jan 7 04:48:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320413 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9EAB4921 for ; Tue, 7 Jan 2020 05:14:12 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 74A07207FD for ; Tue, 7 Jan 2020 05:14:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="KxTiFHSI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 74A07207FD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iohBy-0006jg-2y for patchwork-qemu-devel@patchwork.kernel.org; Tue, 07 Jan 2020 00:14:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44238) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognO-0005P5-Fb for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognM-0004hg-R0 for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:46 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:46393) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognM-0004cX-GD; Mon, 06 Jan 2020 23:48:44 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdX4cptz9sRh; Tue, 7 Jan 2020 15:48:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372512; bh=pOhF9Y4Db6T7gymFJzNkWvkw/xq6Ps53OMhtnsGSzic=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KxTiFHSImnyNIq+cIMIL38Cenv3EGiD9e4IEREgxj8BtN15GcG8pKefI6vQTnnsiX 0FrPEU0YZ40Xc0gO502NvQULN9dFzskwv1VlOfV63Obe7PUT3ic878Q3K3/vY2/BU9 Gqim69ipfz/BaykTclnhQGUSPG2sTl+MV7xzvYc4= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 05/10] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 Date: Tue, 7 Jan 2020 15:48:22 +1100 Message-Id: <20200107044827.471355-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" For the "pseries" machine, we use "virtual hypervisor" mode where we only model the CPU in non-hypervisor privileged mode. This means that we need guest physical addresses within the modelled within the cpu to be treated as absolute physical addresses. We used to do that by clearing LPCR[VPM0] and setting LPCR[RMLS] to a high limit so that the old offset based translation for guest mode applied, which does what we need. However, POWER9 has removed support for that translation mode, which meant we had some ugly hacks to keep it working. We now explicitly handle this sort of translation for virtual hypervisor mode, so the hacks aren't necessary. We don't need to set VPM0 and RMLS from the machine type code - they're now ignored in vhyp mode. On the cpu side we don't need to allow LPCR[RMLS] to be set on POWER9 in vhyp mode - that was only there to allow the hack on the machine side. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- hw/ppc/spapr_cpu_core.c | 6 +----- target/ppc/mmu-hash64.c | 8 -------- 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 8339c4c0f8..daebcd9f38 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -58,14 +58,10 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) * we don't get spurious wakups before an RTAS start-cpu call. * For the same reason, set PSSCR_EC. */ - lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); + lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); lpcr |= LPCR_LPES0 | LPCR_LPES1; env->spr[SPR_PSSCR] |= PSSCR_EC; - /* Set RMLS to the max (ie, 16G) */ - lpcr &= ~LPCR_RMLS; - lpcr |= 1ull << LPCR_RMLS_SHIFT; - ppc_store_lpcr(cpu, lpcr); /* Set a full AMOR so guest can use the AMR as it sees fit */ diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index d878180df5..d7f9933e6d 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1124,14 +1124,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); - /* - * If we have a virtual hypervisor, we need to bring back RMLS. It - * doesn't exist on an actual P9 but that's all we know how to - * configure with softmmu at the moment - */ - if (cpu->vhyp) { - lpcr |= (val & LPCR_RMLS); - } break; default: g_assert_not_reached(); From patchwork Tue Jan 7 04:48:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320405 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BC565138D for ; Tue, 7 Jan 2020 05:05:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 878DC2075A for ; Tue, 7 Jan 2020 05:05:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Pk5WBMKv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 878DC2075A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ioh3y-0003GG-Hu for patchwork-qemu-devel@patchwork.kernel.org; Tue, 07 Jan 2020 00:05:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44235) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognO-0005Oy-Ld for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognM-0004iJ-VD for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:46 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:49713 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognM-0004dC-JH; Mon, 06 Jan 2020 23:48:44 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdY1Gx6z9sSK; Tue, 7 Jan 2020 15:48:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372513; bh=1u/P2vH19t9mX7gOFadyrTySstHu9Bg7Wifev5EcSUA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pk5WBMKvlzGQ1987yso+gX5SAEYld+VmOet6yS3585F1k8h4pk2dSZSAuf7q7YhTS G05cXSK5D5WQya3/Klwz/6sFnueCkVWQ6Ae487y9MZSmKHfqWTDg0z6VljwPPlLpZn LKsl7ClBwe3AAjZkzukZvGJNxoRfOrvRTnVj2D2o= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 06/10] target/ppc: Remove RMOR register from POWER9 & POWER10 Date: Tue, 7 Jan 2020 15:48:23 +1100 Message-Id: <20200107044827.471355-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently we create the Real Mode Offset Register (RMOR) on all Book3S cpus from POWER7 onwards. However the translation mode which the RMOR controls is no longer supported in POWER9, and so the register has been removed from the architecture. Remove it from our model on POWER9 and POWER10. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/translate_init.inc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 436d0d5a51..893fb12e90 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8003,12 +8003,16 @@ static void gen_spr_book3s_ids(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register_hv(env, SPR_RMOR, "RMOR", + spr_register_hv(env, SPR_HRMOR, "HRMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register_hv(env, SPR_HRMOR, "HRMOR", +} + +static void gen_spr_rmor(CPUPPCState *env) +{ + spr_register_hv(env, SPR_RMOR, "RMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -8522,6 +8526,7 @@ static void init_proc_POWER7(CPUPPCState *env) /* POWER7 Specific Registers */ gen_spr_book3s_ids(env); + gen_spr_rmor(env); gen_spr_amr(env); gen_spr_book3s_purr(env); gen_spr_power5p_common(env); @@ -8663,6 +8668,7 @@ static void init_proc_POWER8(CPUPPCState *env) /* POWER8 Specific Registers */ gen_spr_book3s_ids(env); + gen_spr_rmor(env); gen_spr_amr(env); gen_spr_iamr(env); gen_spr_book3s_purr(env); From patchwork Tue Jan 7 04:48:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C872F921 for ; Tue, 7 Jan 2020 05:13:30 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4B430207FD for ; Tue, 7 Jan 2020 05:13:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="D44kTTMQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4B430207FD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42308 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iohBE-0005p0-4W for patchwork-qemu-devel@patchwork.kernel.org; Tue, 07 Jan 2020 00:13:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44244) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognO-0005PO-Ik for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognM-0004ho-S1 for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:46 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:56919) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognM-0004cr-HR; Mon, 06 Jan 2020 23:48:44 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdX6Zv7z9sSL; Tue, 7 Jan 2020 15:48:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372512; bh=n5w7wxI3+o5C/QN2AUn7RAYo17qAhLMn+hlhTqaOse8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D44kTTMQVWXBMjWZ/UekpsRJBOrRTqjo3z6fWrLDO+IPpq/LlvmCSxfiUNZznFFw+ 2+8pTkGfkhaahbGdMoAGrBRvSDMwH36XZ1DOUWQm+SCFl1ptTfWWxgKWisQbbzmZcy xK6VvIAk/DURs6p3mK6bS/fRraSHFarm9aaMdQPM= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 07/10] target/ppc: Use class fields to simplify LPCR masking Date: Tue, 7 Jan 2020 15:48:24 +1100 Message-Id: <20200107044827.471355-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" When we store the Logical Partitioning Control Register (LPCR) we have a big switch statement to work out which are valid bits for the cpu model we're emulating. As well as being ugly, this isn't really conceptually correct, since it is based on the mmu_model variable, whereas the LPCR isn't (only) about the MMU, so mmu_model is basically just acting as a proxy for the cpu model. Handle this in a simpler way, by adding a suitable lpcr_mask to the QOM class. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/cpu-qom.h | 1 + target/ppc/mmu-hash64.c | 37 ++------------------------------- target/ppc/translate_init.inc.c | 27 ++++++++++++++++++++---- 3 files changed, 26 insertions(+), 39 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index e499575dc8..15d6b54a7d 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -177,6 +177,7 @@ typedef struct PowerPCCPUClass { uint64_t insns_flags; uint64_t insns_flags2; uint64_t msr_mask; + uint64_t lpcr_mask; /* Available bits in the LPCR */ uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ powerpc_mmu_t mmu_model; powerpc_excp_t excp_model; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index d7f9933e6d..127b7250ae 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1093,43 +1093,10 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) { + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; - uint64_t lpcr = 0; - /* Filter out bits */ - switch (env->mmu_model) { - case POWERPC_MMU_2_03: /* P5p */ - lpcr = val & (LPCR_RMLS | LPCR_ILE | - LPCR_LPES0 | LPCR_LPES1 | - LPCR_RMI | LPCR_HDICE); - break; - case POWERPC_MMU_2_06: /* P7 */ - lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | - LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | - LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | - LPCR_MER | LPCR_TC | - LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); - break; - case POWERPC_MMU_2_07: /* P8 */ - lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | - LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | - LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | - LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | - LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); - break; - case POWERPC_MMU_3_00: /* P9 */ - lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); - break; - default: - g_assert_not_reached(); - ; - } - env->spr[SPR_LPCR] = lpcr; + env->spr[SPR_LPCR] = val & pcc->lpcr_mask; ppc_hash64_update_rmls(cpu); ppc_hash64_update_vrma(cpu); } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 893fb12e90..240ac00506 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8463,6 +8463,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI); + pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | + LPCR_RMI | LPCR_HDICE; pcc->mmu_model = POWERPC_MMU_2_03; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; @@ -8640,6 +8642,12 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | + LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | + LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | + LPCR_MER | LPCR_TC | + LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; + pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; @@ -8656,7 +8664,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; - pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; } static void init_proc_POWER8(CPUPPCState *env) @@ -8812,6 +8819,13 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_TS0) | (1ull << MSR_TS1) | (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | + LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | + LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | + LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | + LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; + pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | + LPCR_P8_PECE3 | LPCR_P8_PECE4; pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; @@ -8829,8 +8843,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; - pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | - LPCR_P8_PECE3 | LPCR_P8_PECE4; } #ifdef CONFIG_SOFTMMU @@ -9023,6 +9035,14 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | + LPCR_DEE | LPCR_OEE)) + | LPCR_MER | LPCR_GTSE | LPCR_TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; pcc->mmu_model = POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; @@ -9042,7 +9062,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; - pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; } #ifdef CONFIG_SOFTMMU From patchwork Tue Jan 7 04:48:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320407 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3CD57921 for ; Tue, 7 Jan 2020 05:06:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 131C52073D for ; Tue, 7 Jan 2020 05:06:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="KSgeKko3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 131C52073D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42270 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ioh4g-0004KQ-5g for patchwork-qemu-devel@patchwork.kernel.org; Tue, 07 Jan 2020 00:06:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44249) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognO-0005PY-Oa for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognM-0004iE-Uj for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:46 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:42311 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognM-0004d1-J6; Mon, 06 Jan 2020 23:48:44 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdY0JTvz9sSH; Tue, 7 Jan 2020 15:48:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372513; bh=Rxx2qkydXpS+SLgpGEY+gkMtWzxEvGQpLzM+4rL4q54=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KSgeKko3TEPuy6VlolqIa9oT06CfVwwoIZwxgO3QkzcqXxkuWIKw5n2FkIen/PIce 58cd/Zll3iAwfMLZEHgzpVs/pIDPOvHiC+iLouYAUzIhg60fdenlHRyskS7BJb6EYQ LkvDuALOTe48leeJUiAXIdT7o9R/VHPZ3bZOiVK0= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 08/10] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] Date: Tue, 7 Jan 2020 15:48:25 +1100 Message-Id: <20200107044827.471355-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently we use a big switch statement in ppc_hash64_update_rmls() to work out what the right RMA limit is based on the LPCR[RMLS] field. There's no formula for this - it's just an arbitrary mapping defined by the existing CPU implementations - but we can make it a bit more readable by using a lookup table rather than a switch. In addition we can use the MiB/GiB symbols to make it a bit clearer. While there we add a bit of clarity and rationale to the comment about what happens if the LPCR[RMLS] doesn't contain a valid value. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/mmu-hash64.c | 71 ++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 36 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 127b7250ae..bb9ebeaf48 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -18,6 +18,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -755,6 +756,39 @@ static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); } +static target_ulong rmls_limit(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + /* + * This is the full 4 bits encoding of POWER8. Previous + * CPUs only support a subset of these but the filtering + * is done when writing LPCR + */ + const target_ulong rma_sizes[] = { + [0] = 0, + [1] = 16 * GiB, + [2] = 1 * GiB, + [3] = 64 * MiB, + [4] = 256 * MiB, + [5] = 0, + [6] = 0, + [7] = 128 * MiB, + [8] = 32 * MiB, + }; + target_ulong rmls = (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SHIFT; + + if (rmls < ARRAY_SIZE(rma_sizes)) { + return rma_sizes[rmls]; + } else { + /* + * Bad value, so the OS has shot itself in the foot. Return a + * 0-sized RMA which we expect to trigger an immediate DSI or + * ISI + */ + return 0; + } +} + int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { @@ -1004,41 +1038,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; } -static void ppc_hash64_update_rmls(PowerPCCPU *cpu) -{ - CPUPPCState *env = &cpu->env; - uint64_t lpcr = env->spr[SPR_LPCR]; - - /* - * This is the full 4 bits encoding of POWER8. Previous - * CPUs only support a subset of these but the filtering - * is done when writing LPCR - */ - switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { - case 0x8: /* 32MB */ - env->rmls = 0x2000000ull; - break; - case 0x3: /* 64MB */ - env->rmls = 0x4000000ull; - break; - case 0x7: /* 128MB */ - env->rmls = 0x8000000ull; - break; - case 0x4: /* 256MB */ - env->rmls = 0x10000000ull; - break; - case 0x2: /* 1GB */ - env->rmls = 0x40000000ull; - break; - case 0x1: /* 16GB */ - env->rmls = 0x400000000ull; - break; - default: - /* What to do here ??? */ - env->rmls = 0; - } -} - static void ppc_hash64_update_vrma(PowerPCCPU *cpu) { CPUPPCState *env = &cpu->env; @@ -1097,7 +1096,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env = &cpu->env; env->spr[SPR_LPCR] = val & pcc->lpcr_mask; - ppc_hash64_update_rmls(cpu); + env->rmls = rmls_limit(cpu); ppc_hash64_update_vrma(cpu); } From patchwork Tue Jan 7 04:48:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320403 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 721B7921 for ; Tue, 7 Jan 2020 05:01:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48B3F2075A for ; Tue, 7 Jan 2020 05:01:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="chLTQoea" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 48B3F2075A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iogzJ-00069l-Ma for patchwork-qemu-devel@patchwork.kernel.org; Tue, 07 Jan 2020 00:01:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44225) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognO-0005Oa-2s for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognM-0004i8-Uh for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:45 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:38533 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognM-0004cn-Ik; Mon, 06 Jan 2020 23:48:44 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdX5dSDz9sRl; Tue, 7 Jan 2020 15:48:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372512; bh=LX+p22y98QJHXeR526fSlmyfXK9IbB1S0L2Puxze/Ts=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=chLTQoeadr9/n3QAjE5GxwOg3vFFGuVuWuCbIzILktYhTK4gze6EmHzAaa/35hO6f BWFF9erLQ13R4nWKGJUWjQTcp0zs7ml6YwKjgCVEMuQLKdRl3Ce7RCbztf46nuK2OY XVxBGouH1WBp0y+kMAk5aOiumVipqZWoBnHacHbk= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 09/10] target/ppc: Correct RMLS table Date: Tue, 7 Jan 2020 15:48:26 +1100 Message-Id: <20200107044827.471355-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The table of RMA limits based on the LPCR[RMLS] field is slightly wrong. We're missing the RMLS == 0 => 256 GiB RMA option, which is available on POWER8, so add that. The comment that goes with the table is much more wrong. We *don't* filter invalid RMLS values when writing the LPCR, and there's not really a sensible way to do so. Furthermore, while in theory the set of RMLS values is implementation dependent, it seems in practice the same set has been available since around POWER4+ up until POWER8, the last model which supports RMLS at all. So, correct that as well. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/mmu-hash64.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index bb9ebeaf48..e6f24be93e 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -760,12 +760,12 @@ static target_ulong rmls_limit(PowerPCCPU *cpu) { CPUPPCState *env = &cpu->env; /* - * This is the full 4 bits encoding of POWER8. Previous - * CPUs only support a subset of these but the filtering - * is done when writing LPCR + * In theory the meanings of RMLS values are implementation + * dependent. In practice, this seems to have been the set from + * POWER4+..POWER8, and RMLS is no longer supported in POWER9. */ const target_ulong rma_sizes[] = { - [0] = 0, + [0] = 256 * GiB, [1] = 16 * GiB, [2] = 1 * GiB, [3] = 64 * MiB, From patchwork Tue Jan 7 04:48:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11320399 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E97F6930 for ; Tue, 7 Jan 2020 04:59:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC6BE2075A for ; Tue, 7 Jan 2020 04:59:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="kUb+6iyk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BC6BE2075A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iogxZ-0003i4-FG for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jan 2020 23:59:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44234) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iognO-0005Ox-7i for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iognM-0004hw-T4 for qemu-devel@nongnu.org; Mon, 06 Jan 2020 23:48:46 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:39747 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iognM-0004dV-H4; Mon, 06 Jan 2020 23:48:44 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47sKdY25Hbz9sRs; Tue, 7 Jan 2020 15:48:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1578372513; bh=4HhSMl0Es+rg1RXiqlkZW6iMgJYBDjPW1np9fGChUSE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kUb+6iykEcVAHgjueI61Ab9O4tZt1v2CitFwt0npqz5RTaO9nIyhHUoPUbIZUkuYT IL9aR7rJQmuHrfABmov6XlG0ItjzSLhZz9jl4674S6XSlvQb68CJfMbl2V+SJWxOcA UTNN2W68DcVnGVbRaxsboqfDDHFzNShxqc7GizGc= From: David Gibson To: qemu-devel@nongnu.org, groug@kaod.org, philmd@redhat.com, clg@kaod.org Subject: [PATCH v2 10/10] target/ppc: Only calculate RMLS derived RMA limit on demand Date: Tue, 7 Jan 2020 15:48:27 +1100 Message-Id: <20200107044827.471355-11-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200107044827.471355-1-david@gibson.dropbear.id.au> References: <20200107044827.471355-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-ppc@nongnu.org, paulus@samba.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" When the LPCR is written, we update the env->rmls field with the RMA limit it implies. Simplify things by just calculating the value directly from the LPCR value when we need it. It's possible this is a little slower, but it's unlikely to be significant, since this is only for real mode accesses in a translation configuration that's not used very often, and the whole thing is behind the qemu TLB anyway. Therefore, keeping the number of state variables down and not having to worry about making sure it's always in sync seems the better option. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/cpu.h | 1 - target/ppc/mmu-hash64.c | 8 +++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2de9e2fa2b..2a79b97bd8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1075,7 +1075,6 @@ struct CPUPPCState { uint64_t insns_flags2; #if defined(TARGET_PPC64) ppc_slb_t vrma_slb; - target_ulong rmls; #endif int error_code; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index e6f24be93e..170a78bd2e 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -842,8 +842,10 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, goto skip_slb_search; } else { + target_ulong limit = rmls_limit(cpu); + /* Emulated old-style RMO mode, bounds check against RMLS */ - if (raddr >= env->rmls) { + if (raddr >= limit) { if (rwx == 2) { ppc_hash64_set_isi(cs, SRR1_PROTFAULT); } else { @@ -1005,8 +1007,9 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) return -1; } } else { + target_ulong limit = rmls_limit(cpu); /* Emulated old-style RMO mode, bounds check against RMLS */ - if (raddr >= env->rmls) { + if (raddr >= limit) { return -1; } return raddr | env->spr[SPR_RMOR]; @@ -1096,7 +1099,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env = &cpu->env; env->spr[SPR_LPCR] = val & pcc->lpcr_mask; - env->rmls = rmls_limit(cpu); ppc_hash64_update_vrma(cpu); }