From patchwork Mon Sep 24 22:15:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612935 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7814D17D2 for ; Mon, 24 Sep 2018 22:16:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D9D8297F2 for ; Mon, 24 Sep 2018 22:16:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 61E192989B; Mon, 24 Sep 2018 22:16:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 00F82297F2 for ; Mon, 24 Sep 2018 22:16:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728808AbeIYEUf (ORCPT ); Tue, 25 Sep 2018 00:20:35 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46851 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728582AbeIYETq (ORCPT ); Tue, 25 Sep 2018 00:19:46 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOB012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 01/11] qtnfmac_pcie: do not store FW name in driver state structure Date: Mon, 24 Sep 2018 15:15:04 -0700 Message-Id: <20180924221514.4273-2-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Firmware name is only needed at probe stage, no point in keeping it in driver state structure. Signed-off-by: Igor Mitsyanko --- drivers/net/wireless/quantenna/qtnfmac/bus.h | 1 - drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/quantenna/qtnfmac/bus.h b/drivers/net/wireless/quantenna/qtnfmac/bus.h index 323e47c..2beca5b 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/bus.h +++ b/drivers/net/wireless/quantenna/qtnfmac/bus.h @@ -57,7 +57,6 @@ struct qtnf_bus { struct qtnf_wmac *mac[QTNF_MAX_MAC]; struct qtnf_qlink_transport trans; struct qtnf_hw_info hw_info; - char fwname[32]; struct napi_struct mux_napi; struct net_device mux_dev; struct completion firmware_init_complete; diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c index 3120d49..97cc7f2 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c @@ -1177,13 +1177,14 @@ static void qtnf_fw_work_handler(struct work_struct *work) const struct firmware *fw; int ret; u32 state = QTN_RC_FW_LOADRDY | QTN_RC_FW_QLINK; + const char *fwname = QTN_PCI_PEARL_FW_NAME; if (flashboot) { state |= QTN_RC_FW_FLASHBOOT; } else { - ret = request_firmware(&fw, bus->fwname, &pdev->dev); + ret = request_firmware(&fw, fwname, &pdev->dev); if (ret < 0) { - pr_err("failed to get firmware %s\n", bus->fwname); + pr_err("failed to get firmware %s\n", fwname); goto fw_load_fail; } } @@ -1205,7 +1206,7 @@ static void qtnf_fw_work_handler(struct work_struct *work) if (flashboot) { pr_info("booting firmware from flash\n"); } else { - pr_info("starting firmware upload: %s\n", bus->fwname); + pr_info("starting firmware upload: %s\n", fwname); ret = qtnf_ep_fw_load(priv, fw->data, fw->size); release_firmware(fw); @@ -1290,7 +1291,6 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) bus->fw_state = QTNF_FW_STATE_RESET; pcie_priv->pdev = pdev; - strcpy(bus->fwname, QTN_PCI_PEARL_FW_NAME); init_completion(&bus->firmware_init_complete); mutex_init(&bus->bus_lock); spin_lock_init(&pcie_priv->tx0_lock); From patchwork Mon Sep 24 22:15:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612933 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D4B45161F for ; Mon, 24 Sep 2018 22:16:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C8BC9297F2 for ; Mon, 24 Sep 2018 22:16:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BCB482989B; Mon, 24 Sep 2018 22:16:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CEF95297F2 for ; Mon, 24 Sep 2018 22:16:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728607AbeIYETr (ORCPT ); Tue, 25 Sep 2018 00:19:47 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46849 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1726586AbeIYETq (ORCPT ); Tue, 25 Sep 2018 00:19:46 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOC012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 02/11] qtnfmac_pcie: move Pearl pcie sources to pcie-specific directory Date: Mon, 24 Sep 2018 15:15:05 -0700 Message-Id: <20180924221514.4273-3-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In preparation to extract common qtnfmac PCIe driver sources into a separate file, move existing Pearl-specific pcie driver sources to pcie/ directory. Signed-off-by: Igor Mitsyanko --- drivers/net/wireless/quantenna/qtnfmac/Makefile | 2 +- .../wireless/quantenna/qtnfmac/{pearl/pcie.c => pcie/pearl_pcie.c} | 2 +- .../qtnfmac/{pearl/pcie_bus_priv.h => pcie/pearl_pcie_bus_priv.h} | 4 ++-- .../quantenna/qtnfmac/{pearl/pcie_ipc.h => pcie/pearl_pcie_ipc.h} | 0 .../qtnfmac/{pearl/pcie_regs_pearl.h => pcie/pearl_pcie_regs.h} | 0 5 files changed, 4 insertions(+), 4 deletions(-) rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie.c => pcie/pearl_pcie.c} (99%) rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie_bus_priv.h => pcie/pearl_pcie_bus_priv.h} (97%) rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie_ipc.h => pcie/pearl_pcie_ipc.h} (100%) rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie_regs_pearl.h => pcie/pearl_pcie_regs.h} (100%) diff --git a/drivers/net/wireless/quantenna/qtnfmac/Makefile b/drivers/net/wireless/quantenna/qtnfmac/Makefile index 97f760a..9eeddea 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/Makefile +++ b/drivers/net/wireless/quantenna/qtnfmac/Makefile @@ -23,6 +23,6 @@ obj-$(CONFIG_QTNFMAC_PEARL_PCIE) += qtnfmac_pearl_pcie.o qtnfmac_pearl_pcie-objs += \ shm_ipc.o \ - pearl/pcie.o + pcie/pearl_pcie.o qtnfmac_pearl_pcie-$(CONFIG_DEBUG_FS) += debug.o diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c similarity index 99% rename from drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c rename to drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c index 97cc7f2..269a6e4 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c @@ -29,7 +29,7 @@ #include #include "qtn_hw_ids.h" -#include "pcie_bus_priv.h" +#include "pearl_pcie_bus_priv.h" #include "core.h" #include "bus.h" #include "debug.h" diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_bus_priv.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h similarity index 97% rename from drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_bus_priv.h rename to drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h index 397875a..986b957 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_bus_priv.h +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h @@ -20,8 +20,8 @@ #include #include -#include "pcie_regs_pearl.h" -#include "pcie_ipc.h" +#include "pearl_pcie_regs.h" +#include "pearl_pcie_ipc.h" #include "shm_ipc.h" struct bus; diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_ipc.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h similarity index 100% rename from drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_ipc.h rename to drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_regs_pearl.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h similarity index 100% rename from drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_regs_pearl.h rename to drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h From patchwork Mon Sep 24 22:15:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612915 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AA199161F for ; Mon, 24 Sep 2018 22:15:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9C468297EF for ; Mon, 24 Sep 2018 22:15:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 908A829858; Mon, 24 Sep 2018 22:15:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66A47297EF for ; Mon, 24 Sep 2018 22:15:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728698AbeIYETt (ORCPT ); Tue, 25 Sep 2018 00:19:49 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46853 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728588AbeIYETr (ORCPT ); Tue, 25 Sep 2018 00:19:47 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOD012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 03/11] qtnfmac_pcie: rename private Pearl PCIe state structure Date: Mon, 24 Sep 2018 15:15:06 -0700 Message-Id: <20180924221514.4273-4-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In preparation to extract common pcie driver state into a separate structure, rename Pearl-specific state to qtnf_pcie_pearl_state and move it directly to pearl-specific PCIe source file. Signed-off-by: Igor Mitsyanko --- .../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 158 +++++++++++++++------ .../quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h | 91 ------------ 2 files changed, 111 insertions(+), 138 deletions(-) delete mode 100644 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c index 269a6e4..ab06eca 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c @@ -28,10 +28,12 @@ #include #include +#include "pearl_pcie_regs.h" +#include "pearl_pcie_ipc.h" #include "qtn_hw_ids.h" -#include "pearl_pcie_bus_priv.h" #include "core.h" #include "bus.h" +#include "shm_ipc.h" #include "debug.h" static bool use_msi = true; @@ -52,6 +54,68 @@ MODULE_PARM_DESC(flashboot, "set to 0 to use FW binary file on FS"); #define DRV_NAME "qtnfmac_pearl_pcie" +struct qtnf_pcie_pearl_state { + struct pci_dev *pdev; + + /* lock for irq configuration changes */ + spinlock_t irq_lock; + + /* lock for tx reclaim operations */ + spinlock_t tx_reclaim_lock; + /* lock for tx0 operations */ + spinlock_t tx0_lock; + u8 msi_enabled; + u8 tx_stopped; + int mps; + + struct workqueue_struct *workqueue; + struct tasklet_struct reclaim_tq; + + void __iomem *sysctl_bar; + void __iomem *epmem_bar; + void __iomem *dmareg_bar; + + struct qtnf_shm_ipc shm_ipc_ep_in; + struct qtnf_shm_ipc shm_ipc_ep_out; + + struct qtnf_pcie_bda __iomem *bda; + void __iomem *pcie_reg_base; + + u16 tx_bd_num; + u16 rx_bd_num; + + struct sk_buff **tx_skb; + struct sk_buff **rx_skb; + + struct qtnf_tx_bd *tx_bd_vbase; + dma_addr_t tx_bd_pbase; + + struct qtnf_rx_bd *rx_bd_vbase; + dma_addr_t rx_bd_pbase; + + dma_addr_t bd_table_paddr; + void *bd_table_vaddr; + u32 bd_table_len; + + u32 rx_bd_w_index; + u32 rx_bd_r_index; + + u32 tx_bd_w_index; + u32 tx_bd_r_index; + + u32 pcie_irq_mask; + + /* diagnostics stats */ + u32 pcie_irq_count; + u32 pcie_irq_rx_count; + u32 pcie_irq_tx_count; + u32 pcie_irq_uf_count; + u32 tx_full_count; + u32 tx_done_count; + u32 tx_reclaim_done; + u32 tx_reclaim_req; +}; + static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg) { writel(val, basereg); @@ -60,7 +124,7 @@ static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg) readl(basereg); } -static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_bus_priv *priv) +static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_pearl_state *priv) { unsigned long flags; @@ -69,7 +133,7 @@ static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_bus_priv *priv) spin_unlock_irqrestore(&priv->irq_lock, flags); } -static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_bus_priv *priv) +static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_pearl_state *priv) { unsigned long flags; @@ -78,7 +142,7 @@ static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_bus_priv *priv) spin_unlock_irqrestore(&priv->irq_lock, flags); } -static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_bus_priv *priv) +static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_pearl_state *priv) { unsigned long flags; @@ -87,7 +151,7 @@ static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_bus_priv *priv) spin_unlock_irqrestore(&priv->irq_lock, flags); } -static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_bus_priv *priv) +static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_pearl_state *priv) { unsigned long flags; @@ -97,7 +161,7 @@ static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_bus_priv *priv) spin_unlock_irqrestore(&priv->irq_lock, flags); } -static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_bus_priv *priv) +static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_pearl_state *priv) { unsigned long flags; @@ -107,7 +171,7 @@ static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_bus_priv *priv) spin_unlock_irqrestore(&priv->irq_lock, flags); } -static inline void qtnf_en_txdone_irq(struct qtnf_pcie_bus_priv *priv) +static inline void qtnf_en_txdone_irq(struct qtnf_pcie_pearl_state *priv) { unsigned long flags; @@ -117,7 +181,7 @@ static inline void qtnf_en_txdone_irq(struct qtnf_pcie_bus_priv *priv) spin_unlock_irqrestore(&priv->irq_lock, flags); } -static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_bus_priv *priv) +static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_pearl_state *priv) { unsigned long flags; @@ -127,7 +191,7 @@ static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_bus_priv *priv) spin_unlock_irqrestore(&priv->irq_lock, flags); } -static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv) +static void qtnf_pcie_init_irq(struct qtnf_pcie_pearl_state *priv) { struct pci_dev *pdev = priv->pdev; @@ -150,7 +214,7 @@ static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv) } } -static void qtnf_deassert_intx(struct qtnf_pcie_bus_priv *priv) +static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *priv) { void __iomem *reg = priv->sysctl_bar + PEARL_PCIE_CFG0_OFFSET; u32 cfg; @@ -160,7 +224,7 @@ static void qtnf_deassert_intx(struct qtnf_pcie_bus_priv *priv) qtnf_non_posted_write(cfg, reg); } -static void qtnf_reset_card(struct qtnf_pcie_bus_priv *priv) +static void qtnf_reset_card(struct qtnf_pcie_pearl_state *priv) { const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_EP_RESET); void __iomem *reg = priv->sysctl_bar + @@ -173,7 +237,7 @@ static void qtnf_reset_card(struct qtnf_pcie_bus_priv *priv) static void qtnf_ipc_gen_ep_int(void *arg) { - const struct qtnf_pcie_bus_priv *priv = arg; + const struct qtnf_pcie_pearl_state *priv = arg; const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_IPC_IRQ); void __iomem *reg = priv->sysctl_bar + QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET; @@ -181,7 +245,7 @@ static void qtnf_ipc_gen_ep_int(void *arg) qtnf_non_posted_write(data, reg); } -static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 index) +static void __iomem *qtnf_map_bar(struct qtnf_pcie_pearl_state *priv, u8 index) { void __iomem *vaddr; dma_addr_t busaddr; @@ -206,7 +270,7 @@ static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 index) static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t len) { - struct qtnf_pcie_bus_priv *priv = arg; + struct qtnf_pcie_pearl_state *priv = arg; struct qtnf_bus *bus = pci_get_drvdata(priv->pdev); struct sk_buff *skb; @@ -227,7 +291,7 @@ static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t len) qtnf_trans_handle_rx_ctl_packet(bus, skb); } -static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv) +static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pearl_state *priv) { struct qtnf_shm_ipc_region __iomem *ipc_tx_reg; struct qtnf_shm_ipc_region __iomem *ipc_rx_reg; @@ -248,13 +312,13 @@ static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv) return 0; } -static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv) +static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_pearl_state *priv) { qtnf_shm_ipc_free(&priv->shm_ipc_ep_in); qtnf_shm_ipc_free(&priv->shm_ipc_ep_out); } -static int qtnf_pcie_init_memory(struct qtnf_pcie_bus_priv *priv) +static int qtnf_pcie_init_memory(struct qtnf_pcie_pearl_state *priv) { int ret = -ENOMEM; @@ -283,7 +347,7 @@ static int qtnf_pcie_init_memory(struct qtnf_pcie_bus_priv *priv) return 0; } -static void qtnf_tune_pcie_mps(struct qtnf_pcie_bus_priv *priv) +static void qtnf_tune_pcie_mps(struct qtnf_pcie_pearl_state *priv) { struct pci_dev *pdev = priv->pdev; struct pci_dev *parent; @@ -355,7 +419,7 @@ static int qtnf_poll_state(__le32 __iomem *reg, u32 state, u32 delay_in_ms) return 0; } -static int alloc_skb_array(struct qtnf_pcie_bus_priv *priv) +static int alloc_skb_array(struct qtnf_pcie_pearl_state *priv) { struct sk_buff **vaddr; int len; @@ -375,7 +439,7 @@ static int alloc_skb_array(struct qtnf_pcie_bus_priv *priv) return 0; } -static int alloc_bd_table(struct qtnf_pcie_bus_priv *priv) +static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv) { dma_addr_t paddr; void *vaddr; @@ -426,7 +490,7 @@ static int alloc_bd_table(struct qtnf_pcie_bus_priv *priv) return 0; } -static int skb2rbd_attach(struct qtnf_pcie_bus_priv *priv, u16 index) +static int skb2rbd_attach(struct qtnf_pcie_pearl_state *priv, u16 index) { struct qtnf_rx_bd *rxbd; struct sk_buff *skb; @@ -469,7 +533,7 @@ static int skb2rbd_attach(struct qtnf_pcie_bus_priv *priv, u16 index) return 0; } -static int alloc_rx_buffers(struct qtnf_pcie_bus_priv *priv) +static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *priv) { u16 i; int ret = 0; @@ -487,7 +551,7 @@ static int alloc_rx_buffers(struct qtnf_pcie_bus_priv *priv) } /* all rx/tx activity should have ceased before calling this function */ -static void qtnf_free_xfer_buffers(struct qtnf_pcie_bus_priv *priv) +static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *priv) { struct qtnf_tx_bd *txbd; struct qtnf_rx_bd *rxbd; @@ -524,7 +588,7 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_bus_priv *priv) } } -static int qtnf_hhbm_init(struct qtnf_pcie_bus_priv *priv) +static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state *priv) { u32 val; @@ -542,7 +606,7 @@ static int qtnf_hhbm_init(struct qtnf_pcie_bus_priv *priv) return 0; } -static int qtnf_pcie_init_xfer(struct qtnf_pcie_bus_priv *priv) +static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *priv) { int ret; u32 val; @@ -605,7 +669,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_bus_priv *priv) return ret; } -static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_bus_priv *priv) +static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *priv) { struct qtnf_tx_bd *txbd; struct sk_buff *skb; @@ -656,7 +720,7 @@ static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_bus_priv *priv) spin_unlock_irqrestore(&priv->tx_reclaim_lock, flags); } -static int qtnf_tx_queue_ready(struct qtnf_pcie_bus_priv *priv) +static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *priv) { if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index, priv->tx_bd_num)) { @@ -675,7 +739,7 @@ static int qtnf_tx_queue_ready(struct qtnf_pcie_bus_priv *priv) static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) { - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); dma_addr_t txbd_paddr, skb_paddr; struct qtnf_tx_bd *txbd; unsigned long flags; @@ -750,7 +814,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) static int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb) { - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); int ret; ret = qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len); @@ -766,7 +830,7 @@ static int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb) static irqreturn_t qtnf_interrupt(int irq, void *data) { struct qtnf_bus *bus = (struct qtnf_bus *)data; - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); u32 status; priv->pcie_irq_count++; @@ -807,7 +871,7 @@ static irqreturn_t qtnf_interrupt(int irq, void *data) return IRQ_HANDLED; } -static int qtnf_rx_data_ready(struct qtnf_pcie_bus_priv *priv) +static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *priv) { u16 index = priv->rx_bd_r_index; struct qtnf_rx_bd *rxbd; @@ -825,7 +889,7 @@ static int qtnf_rx_data_ready(struct qtnf_pcie_bus_priv *priv) static int qtnf_rx_poll(struct napi_struct *napi, int budget) { struct qtnf_bus *bus = container_of(napi, struct qtnf_bus, mux_napi); - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); struct net_device *ndev = NULL; struct sk_buff *skb = NULL; int processed = 0; @@ -930,14 +994,14 @@ static int qtnf_rx_poll(struct napi_struct *napi, int budget) static void qtnf_pcie_data_tx_timeout(struct qtnf_bus *bus, struct net_device *ndev) { - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); tasklet_hi_schedule(&priv->reclaim_tq); } static void qtnf_pcie_data_rx_start(struct qtnf_bus *bus) { - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); qtnf_enable_hdp_irqs(priv); napi_enable(&bus->mux_napi); @@ -945,7 +1009,7 @@ static void qtnf_pcie_data_rx_start(struct qtnf_bus *bus) static void qtnf_pcie_data_rx_stop(struct qtnf_bus *bus) { - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); napi_disable(&bus->mux_napi); qtnf_disable_hdp_irqs(priv); @@ -965,7 +1029,7 @@ static const struct qtnf_bus_ops qtnf_pcie_bus_ops = { static int qtnf_dbg_mps_show(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); seq_printf(s, "%d\n", priv->mps); @@ -975,7 +1039,7 @@ static int qtnf_dbg_mps_show(struct seq_file *s, void *data) static int qtnf_dbg_msi_show(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); seq_printf(s, "%u\n", priv->msi_enabled); @@ -985,7 +1049,7 @@ static int qtnf_dbg_msi_show(struct seq_file *s, void *data) static int qtnf_dbg_irq_stats(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); u32 reg = readl(PCIE_HDP_INT_EN(priv->pcie_reg_base)); u32 status; @@ -1009,7 +1073,7 @@ static int qtnf_dbg_irq_stats(struct seq_file *s, void *data) static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); seq_printf(s, "tx_full_count(%u)\n", priv->tx_full_count); seq_printf(s, "tx_done_count(%u)\n", priv->tx_done_count); @@ -1040,7 +1104,7 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data) static int qtnf_dbg_shm_stats(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n", priv->shm_ipc_ep_in.tx_packet_count); @@ -1054,7 +1118,7 @@ static int qtnf_dbg_shm_stats(struct seq_file *s, void *data) return 0; } -static int qtnf_ep_fw_send(struct qtnf_pcie_bus_priv *priv, uint32_t size, +static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *priv, uint32_t size, int blk, const u8 *pblk, const u8 *fw) { struct pci_dev *pdev = priv->pdev; @@ -1103,7 +1167,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_bus_priv *priv, uint32_t size, } static int -qtnf_ep_fw_load(struct qtnf_pcie_bus_priv *priv, const u8 *fw, u32 fw_size) +qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, const u8 *fw, u32 fw_size) { int blk_size = QTN_PCIE_FW_BUFSZ - sizeof(struct qtnf_pcie_fw_hdr); int blk_count = fw_size / blk_size + ((fw_size % blk_size) ? 1 : 0); @@ -1172,7 +1236,7 @@ qtnf_ep_fw_load(struct qtnf_pcie_bus_priv *priv, const u8 *fw, u32 fw_size) static void qtnf_fw_work_handler(struct work_struct *work) { struct qtnf_bus *bus = container_of(work, struct qtnf_bus, fw_work); - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); struct pci_dev *pdev = priv->pdev; const struct firmware *fw; int ret; @@ -1256,7 +1320,7 @@ static void qtnf_fw_work_handler(struct work_struct *work) static void qtnf_bringup_fw_async(struct qtnf_bus *bus) { - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); struct pci_dev *pdev = priv->pdev; get_device(&pdev->dev); @@ -1266,7 +1330,7 @@ static void qtnf_bringup_fw_async(struct qtnf_bus *bus) static void qtnf_reclaim_tasklet_fn(unsigned long data) { - struct qtnf_pcie_bus_priv *priv = (void *)data; + struct qtnf_pcie_pearl_state *priv = (void *)data; qtnf_pcie_data_tx_reclaim(priv); qtnf_en_txdone_irq(priv); @@ -1274,7 +1338,7 @@ static void qtnf_reclaim_tasklet_fn(unsigned long data) static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) { - struct qtnf_pcie_bus_priv *pcie_priv; + struct qtnf_pcie_pearl_state *pcie_priv; struct qtnf_bus *bus; int ret; @@ -1407,7 +1471,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) static void qtnf_pcie_remove(struct pci_dev *pdev) { - struct qtnf_pcie_bus_priv *priv; + struct qtnf_pcie_pearl_state *priv; struct qtnf_bus *bus; bus = pci_get_drvdata(pdev); diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h deleted file mode 100644 index 986b957..0000000 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2015-2016 Quantenna Communications, Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _QTN_FMAC_PCIE_H_ -#define _QTN_FMAC_PCIE_H_ - -#include -#include - -#include "pearl_pcie_regs.h" -#include "pearl_pcie_ipc.h" -#include "shm_ipc.h" - -struct bus; - -struct qtnf_pcie_bus_priv { - struct pci_dev *pdev; - - /* lock for irq configuration changes */ - spinlock_t irq_lock; - - /* lock for tx reclaim operations */ - spinlock_t tx_reclaim_lock; - /* lock for tx0 operations */ - spinlock_t tx0_lock; - u8 msi_enabled; - u8 tx_stopped; - int mps; - - struct workqueue_struct *workqueue; - struct tasklet_struct reclaim_tq; - - void __iomem *sysctl_bar; - void __iomem *epmem_bar; - void __iomem *dmareg_bar; - - struct qtnf_shm_ipc shm_ipc_ep_in; - struct qtnf_shm_ipc shm_ipc_ep_out; - - struct qtnf_pcie_bda __iomem *bda; - void __iomem *pcie_reg_base; - - u16 tx_bd_num; - u16 rx_bd_num; - - struct sk_buff **tx_skb; - struct sk_buff **rx_skb; - - struct qtnf_tx_bd *tx_bd_vbase; - dma_addr_t tx_bd_pbase; - - struct qtnf_rx_bd *rx_bd_vbase; - dma_addr_t rx_bd_pbase; - - dma_addr_t bd_table_paddr; - void *bd_table_vaddr; - u32 bd_table_len; - - u32 rx_bd_w_index; - u32 rx_bd_r_index; - - u32 tx_bd_w_index; - u32 tx_bd_r_index; - - u32 pcie_irq_mask; - - /* diagnostics stats */ - u32 pcie_irq_count; - u32 pcie_irq_rx_count; - u32 pcie_irq_tx_count; - u32 pcie_irq_uf_count; - u32 tx_full_count; - u32 tx_done_count; - u32 tx_reclaim_done; - u32 tx_reclaim_req; -}; - -#endif /* _QTN_FMAC_PCIE_H_ */ From patchwork Mon Sep 24 22:15:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612925 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7DD22112B for ; Mon, 24 Sep 2018 22:15:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 712A4297EF for ; Mon, 24 Sep 2018 22:15:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 65A4C2988A; Mon, 24 Sep 2018 22:15:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF029297EF for ; Mon, 24 Sep 2018 22:15:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728688AbeIYETt (ORCPT ); Tue, 25 Sep 2018 00:19:49 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46857 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728647AbeIYETr (ORCPT ); Tue, 25 Sep 2018 00:19:47 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOE012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 04/11] qtnfmac_pcie: indicate pearl-specific structures by their names Date: Mon, 24 Sep 2018 15:15:07 -0700 Message-Id: <20180924221514.4273-5-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In preparation to extract common PCIe driver state, indicate PEARL-specific structures by their name and move them to pearl-specific source file. Signed-off-by: Igor Mitsyanko --- .../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 89 +++++++++++++++++----- .../quantenna/qtnfmac/pcie/pearl_pcie_ipc.h | 47 ------------ 2 files changed, 68 insertions(+), 68 deletions(-) diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c index ab06eca..4e9eb46 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c @@ -54,6 +54,53 @@ MODULE_PARM_DESC(flashboot, "set to 0 to use FW binary file on FS"); #define DRV_NAME "qtnfmac_pearl_pcie" +struct qtnf_pearl_bda { + __le16 bda_len; + __le16 bda_version; + __le32 bda_pci_endian; + __le32 bda_ep_state; + __le32 bda_rc_state; + __le32 bda_dma_mask; + __le32 bda_msi_addr; + __le32 bda_flashsz; + u8 bda_boardname[PCIE_BDA_NAMELEN]; + __le32 bda_rc_msi_enabled; + u8 bda_hhbm_list[PCIE_HHBM_MAX_SIZE]; + __le32 bda_dsbw_start_index; + __le32 bda_dsbw_end_index; + __le32 bda_dsbw_total_bytes; + __le32 bda_rc_tx_bd_base; + __le32 bda_rc_tx_bd_num; + u8 bda_pcie_mac[QTN_ENET_ADDR_LENGTH]; + struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */ + struct qtnf_shm_ipc_region bda_shm_reg2 __aligned(4096); /* host RX */ +} __packed; + +struct qtnf_pearl_tx_bd { + __le32 addr; + __le32 addr_h; + __le32 info; + __le32 info_h; +} __packed; + +struct qtnf_pearl_rx_bd { + __le32 addr; + __le32 addr_h; + __le32 info; + __le32 info_h; + __le32 next_ptr; + __le32 next_ptr_h; +} __packed; + +struct qtnf_pearl_fw_hdr { + u8 boardflg[8]; + __le32 fwsize; + __le32 seqnum; + __le32 type; + __le32 pktlen; + __le32 crc; +} __packed; + struct qtnf_pcie_pearl_state { struct pci_dev *pdev; @@ -78,7 +125,7 @@ struct qtnf_pcie_pearl_state { struct qtnf_shm_ipc shm_ipc_ep_in; struct qtnf_shm_ipc shm_ipc_ep_out; - struct qtnf_pcie_bda __iomem *bda; + struct qtnf_pearl_bda __iomem *bda; void __iomem *pcie_reg_base; u16 tx_bd_num; @@ -87,10 +134,10 @@ struct qtnf_pcie_pearl_state { struct sk_buff **tx_skb; struct sk_buff **rx_skb; - struct qtnf_tx_bd *tx_bd_vbase; + struct qtnf_pearl_tx_bd *tx_bd_vbase; dma_addr_t tx_bd_pbase; - struct qtnf_rx_bd *rx_bd_vbase; + struct qtnf_pearl_rx_bd *rx_bd_vbase; dma_addr_t rx_bd_pbase; dma_addr_t bd_table_paddr; @@ -445,8 +492,8 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv) void *vaddr; int len; - len = priv->tx_bd_num * sizeof(struct qtnf_tx_bd) + - priv->rx_bd_num * sizeof(struct qtnf_rx_bd); + len = priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd) + + priv->rx_bd_num * sizeof(struct qtnf_pearl_rx_bd); vaddr = dmam_alloc_coherent(&priv->pdev->dev, len, &paddr, GFP_KERNEL); if (!vaddr) @@ -470,8 +517,8 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv) /* rx bd */ - vaddr = ((struct qtnf_tx_bd *)vaddr) + priv->tx_bd_num; - paddr += priv->tx_bd_num * sizeof(struct qtnf_tx_bd); + vaddr = ((struct qtnf_pearl_tx_bd *)vaddr) + priv->tx_bd_num; + paddr += priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd); priv->rx_bd_vbase = vaddr; priv->rx_bd_pbase = paddr; @@ -482,7 +529,7 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv) #endif writel(QTN_HOST_LO32(paddr), PCIE_HDP_TX_HOST_Q_BASE_L(priv->pcie_reg_base)); - writel(priv->rx_bd_num | (sizeof(struct qtnf_rx_bd)) << 16, + writel(priv->rx_bd_num | (sizeof(struct qtnf_pearl_rx_bd)) << 16, PCIE_HDP_TX_HOST_Q_SZ_CTRL(priv->pcie_reg_base)); pr_debug("RX descriptor table: vaddr=0x%p paddr=%pad\n", vaddr, &paddr); @@ -492,7 +539,7 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv) static int skb2rbd_attach(struct qtnf_pcie_pearl_state *priv, u16 index) { - struct qtnf_rx_bd *rxbd; + struct qtnf_pearl_rx_bd *rxbd; struct sk_buff *skb; dma_addr_t paddr; @@ -539,7 +586,7 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *priv) int ret = 0; memset(priv->rx_bd_vbase, 0x0, - priv->rx_bd_num * sizeof(struct qtnf_rx_bd)); + priv->rx_bd_num * sizeof(struct qtnf_pearl_rx_bd)); for (i = 0; i < priv->rx_bd_num; i++) { ret = skb2rbd_attach(priv, i); @@ -553,8 +600,8 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *priv) /* all rx/tx activity should have ceased before calling this function */ static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *priv) { - struct qtnf_tx_bd *txbd; - struct qtnf_rx_bd *rxbd; + struct qtnf_pearl_tx_bd *txbd; + struct qtnf_pearl_rx_bd *rxbd; struct sk_buff *skb; dma_addr_t paddr; int i; @@ -622,7 +669,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *priv) return -EINVAL; } - val = priv->tx_bd_num * sizeof(struct qtnf_tx_bd); + val = priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd); if (val > PCIE_HHBM_MAX_SIZE) { pr_err("tx_bd_size_param %u is too large\n", priv->tx_bd_num); @@ -671,7 +718,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *priv) static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *priv) { - struct qtnf_tx_bd *txbd; + struct qtnf_pearl_tx_bd *txbd; struct sk_buff *skb; unsigned long flags; dma_addr_t paddr; @@ -741,7 +788,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) { struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); dma_addr_t txbd_paddr, skb_paddr; - struct qtnf_tx_bd *txbd; + struct qtnf_pearl_tx_bd *txbd; unsigned long flags; int len, i; u32 info; @@ -782,7 +829,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) dma_wmb(); /* write new TX descriptor to PCIE_RX_FIFO on EP */ - txbd_paddr = priv->tx_bd_pbase + i * sizeof(struct qtnf_tx_bd); + txbd_paddr = priv->tx_bd_pbase + i * sizeof(struct qtnf_pearl_tx_bd); #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT writel(QTN_HOST_HI32(txbd_paddr), @@ -874,7 +921,7 @@ static irqreturn_t qtnf_interrupt(int irq, void *data) static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *priv) { u16 index = priv->rx_bd_r_index; - struct qtnf_rx_bd *rxbd; + struct qtnf_pearl_rx_bd *rxbd; u32 descw; rxbd = &priv->rx_bd_vbase[index]; @@ -893,7 +940,7 @@ static int qtnf_rx_poll(struct napi_struct *napi, int budget) struct net_device *ndev = NULL; struct sk_buff *skb = NULL; int processed = 0; - struct qtnf_rx_bd *rxbd; + struct qtnf_pearl_rx_bd *rxbd; dma_addr_t skb_paddr; int consume; u32 descw; @@ -1124,7 +1171,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *priv, uint32_t size, struct pci_dev *pdev = priv->pdev; struct qtnf_bus *bus = pci_get_drvdata(pdev); - struct qtnf_pcie_fw_hdr *hdr; + struct qtnf_pearl_fw_hdr *hdr; u8 *pdata; int hds = sizeof(*hdr); @@ -1139,7 +1186,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *priv, uint32_t size, skb->len = QTN_PCIE_FW_BUFSZ; skb->dev = NULL; - hdr = (struct qtnf_pcie_fw_hdr *)skb->data; + hdr = (struct qtnf_pearl_fw_hdr *)skb->data; memcpy(hdr->boardflg, QTN_PCIE_BOARDFLG, strlen(QTN_PCIE_BOARDFLG)); hdr->fwsize = cpu_to_le32(size); hdr->seqnum = cpu_to_le32(blk); @@ -1169,7 +1216,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *priv, uint32_t size, static int qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, const u8 *fw, u32 fw_size) { - int blk_size = QTN_PCIE_FW_BUFSZ - sizeof(struct qtnf_pcie_fw_hdr); + int blk_size = QTN_PCIE_FW_BUFSZ - sizeof(struct qtnf_pearl_fw_hdr); int blk_count = fw_size / blk_size + ((fw_size % blk_size) ? 1 : 0); const u8 *pblk = fw; int threshold = 0; diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h index 00bb21a..af528b8 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h @@ -101,44 +101,6 @@ enum qtnf_pcie_bda_ipc_flags { QTN_PCIE_IPC_FLAG_SHM_PIO = BIT(1), }; -struct qtnf_pcie_bda { - __le16 bda_len; - __le16 bda_version; - __le32 bda_pci_endian; - __le32 bda_ep_state; - __le32 bda_rc_state; - __le32 bda_dma_mask; - __le32 bda_msi_addr; - __le32 bda_flashsz; - u8 bda_boardname[PCIE_BDA_NAMELEN]; - __le32 bda_rc_msi_enabled; - u8 bda_hhbm_list[PCIE_HHBM_MAX_SIZE]; - __le32 bda_dsbw_start_index; - __le32 bda_dsbw_end_index; - __le32 bda_dsbw_total_bytes; - __le32 bda_rc_tx_bd_base; - __le32 bda_rc_tx_bd_num; - u8 bda_pcie_mac[QTN_ENET_ADDR_LENGTH]; - struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */ - struct qtnf_shm_ipc_region bda_shm_reg2 __aligned(4096); /* host RX */ -} __packed; - -struct qtnf_tx_bd { - __le32 addr; - __le32 addr_h; - __le32 info; - __le32 info_h; -} __packed; - -struct qtnf_rx_bd { - __le32 addr; - __le32 addr_h; - __le32 info; - __le32 info_h; - __le32 next_ptr; - __le32 next_ptr_h; -} __packed; - enum qtnf_fw_loadtype { QTN_FW_DBEGIN, QTN_FW_DSUB, @@ -146,13 +108,4 @@ enum qtnf_fw_loadtype { QTN_FW_CTRL }; -struct qtnf_pcie_fw_hdr { - u8 boardflg[8]; - __le32 fwsize; - __le32 seqnum; - __le32 type; - __le32 pktlen; - __le32 crc; -} __packed; - #endif /* _QTN_FMAC_PCIE_IPC_H_ */ From patchwork Mon Sep 24 22:15:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612929 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8688E161F for ; Mon, 24 Sep 2018 22:15:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74934297EF for ; Mon, 24 Sep 2018 22:15:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 66B0229897; Mon, 24 Sep 2018 22:15:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0155F297EF for ; Mon, 24 Sep 2018 22:15:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728682AbeIYETt (ORCPT ); Tue, 25 Sep 2018 00:19:49 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46856 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1726586AbeIYETr (ORCPT ); Tue, 25 Sep 2018 00:19:47 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOF012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 05/11] qtnfmac_pcie: pearl: rename spinlock tx0_lock to tx_lock Date: Mon, 24 Sep 2018 15:15:08 -0700 Message-Id: <20180924221514.4273-6-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP tx_lock name will later be reused when common pcie code is extracted to separate files. Signed-off-by: Igor Mitsyanko --- drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c index 4e9eb46..791a1e3 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c @@ -110,7 +110,7 @@ struct qtnf_pcie_pearl_state { /* lock for tx reclaim operations */ spinlock_t tx_reclaim_lock; /* lock for tx0 operations */ - spinlock_t tx0_lock; + spinlock_t tx_lock; u8 msi_enabled; u8 tx_stopped; int mps; @@ -794,7 +794,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) u32 info; int ret = 0; - spin_lock_irqsave(&priv->tx0_lock, flags); + spin_lock_irqsave(&priv->tx_lock, flags); if (!qtnf_tx_queue_ready(priv)) { if (skb->dev) { @@ -802,7 +802,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) priv->tx_stopped = 1; } - spin_unlock_irqrestore(&priv->tx0_lock, flags); + spin_unlock_irqrestore(&priv->tx_lock, flags); return NETDEV_TX_BUSY; } @@ -852,7 +852,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) } priv->tx_done_count++; - spin_unlock_irqrestore(&priv->tx0_lock, flags); + spin_unlock_irqrestore(&priv->tx_lock, flags); qtnf_pcie_data_tx_reclaim(priv); @@ -1404,7 +1404,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) init_completion(&bus->firmware_init_complete); mutex_init(&bus->bus_lock); - spin_lock_init(&pcie_priv->tx0_lock); + spin_lock_init(&pcie_priv->tx_lock); spin_lock_init(&pcie_priv->irq_lock); spin_lock_init(&pcie_priv->tx_reclaim_lock); From patchwork Mon Sep 24 22:15:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612941 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2AF0D161F for ; Mon, 24 Sep 2018 22:16:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D519297F2 for ; Mon, 24 Sep 2018 22:16:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0FA6729897; Mon, 24 Sep 2018 22:16:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE9612988A for ; Mon, 24 Sep 2018 22:16:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727817AbeIYEUf (ORCPT ); Tue, 25 Sep 2018 00:20:35 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46850 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728574AbeIYETr (ORCPT ); Tue, 25 Sep 2018 00:19:47 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOG012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 06/11] qtnfmac_pcie: separate platform-independent PCIe structure Date: Mon, 24 Sep 2018 15:15:09 -0700 Message-Id: <20180924221514.4273-7-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move platform-independent PCIe data structure to a separate header file so it can be reused by different devices. Signed-off-by: Igor Mitsyanko --- .../wireless/quantenna/qtnfmac/pcie/pcie_priv.h | 70 +++ .../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 471 ++++++++++----------- .../quantenna/qtnfmac/pcie/pearl_pcie_ipc.h | 7 - 3 files changed, 287 insertions(+), 261 deletions(-) create mode 100644 drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h new file mode 100644 index 0000000..8da9612 --- /dev/null +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */ + +#ifndef _QTN_FMAC_PCIE_H_ +#define _QTN_FMAC_PCIE_H_ + +#include +#include +#include +#include +#include +#include + +#include "shm_ipc.h" + +#define SKB_BUF_SIZE 2048 + +#define QTN_FW_DL_TIMEOUT_MS 3000 +#define QTN_FW_QLINK_TIMEOUT_MS 30000 +#define QTN_EP_RESET_WAIT_MS 1000 + +struct qtnf_pcie_bus_priv { + struct pci_dev *pdev; + + spinlock_t tx_reclaim_lock; + spinlock_t tx_lock; + int mps; + + struct workqueue_struct *workqueue; + struct tasklet_struct reclaim_tq; + + void __iomem *sysctl_bar; + void __iomem *epmem_bar; + void __iomem *dmareg_bar; + + struct qtnf_shm_ipc shm_ipc_ep_in; + struct qtnf_shm_ipc shm_ipc_ep_out; + + u16 tx_bd_num; + u16 rx_bd_num; + + struct sk_buff **tx_skb; + struct sk_buff **rx_skb; + + u32 rx_bd_w_index; + u32 rx_bd_r_index; + + u32 tx_bd_w_index; + u32 tx_bd_r_index; + + /* diagnostics stats */ + u32 pcie_irq_count; + u32 tx_full_count; + u32 tx_done_count; + u32 tx_reclaim_done; + u32 tx_reclaim_req; + + u8 msi_enabled; + u8 tx_stopped; +}; + +static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg) +{ + writel(val, basereg); + + /* flush posted write */ + readl(basereg); +} + +#endif /* _QTN_FMAC_PCIE_H_ */ diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c index 791a1e3..97f3001 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c @@ -28,6 +28,7 @@ #include #include +#include "pcie_priv.h" #include "pearl_pcie_regs.h" #include "pearl_pcie_ipc.h" #include "qtn_hw_ids.h" @@ -102,38 +103,14 @@ struct qtnf_pearl_fw_hdr { } __packed; struct qtnf_pcie_pearl_state { - struct pci_dev *pdev; + struct qtnf_pcie_bus_priv base; /* lock for irq configuration changes */ spinlock_t irq_lock; - /* lock for tx reclaim operations */ - spinlock_t tx_reclaim_lock; - /* lock for tx0 operations */ - spinlock_t tx_lock; - u8 msi_enabled; - u8 tx_stopped; - int mps; - - struct workqueue_struct *workqueue; - struct tasklet_struct reclaim_tq; - - void __iomem *sysctl_bar; - void __iomem *epmem_bar; - void __iomem *dmareg_bar; - - struct qtnf_shm_ipc shm_ipc_ep_in; - struct qtnf_shm_ipc shm_ipc_ep_out; - struct qtnf_pearl_bda __iomem *bda; void __iomem *pcie_reg_base; - u16 tx_bd_num; - u16 rx_bd_num; - - struct sk_buff **tx_skb; - struct sk_buff **rx_skb; - struct qtnf_pearl_tx_bd *tx_bd_vbase; dma_addr_t tx_bd_pbase; @@ -143,102 +120,80 @@ struct qtnf_pcie_pearl_state { dma_addr_t bd_table_paddr; void *bd_table_vaddr; u32 bd_table_len; - - u32 rx_bd_w_index; - u32 rx_bd_r_index; - - u32 tx_bd_w_index; - u32 tx_bd_r_index; - u32 pcie_irq_mask; - - /* diagnostics stats */ - u32 pcie_irq_count; u32 pcie_irq_rx_count; u32 pcie_irq_tx_count; u32 pcie_irq_uf_count; - u32 tx_full_count; - u32 tx_done_count; - u32 tx_reclaim_done; - u32 tx_reclaim_req; }; -static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg) -{ - writel(val, basereg); - - /* flush posted write */ - readl(basereg); -} - -static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_pearl_state *priv) +static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_pearl_state *ps) { unsigned long flags; - spin_lock_irqsave(&priv->irq_lock, flags); - priv->pcie_irq_mask = (PCIE_HDP_INT_RX_BITS | PCIE_HDP_INT_TX_BITS); - spin_unlock_irqrestore(&priv->irq_lock, flags); + spin_lock_irqsave(&ps->irq_lock, flags); + ps->pcie_irq_mask = (PCIE_HDP_INT_RX_BITS | PCIE_HDP_INT_TX_BITS); + spin_unlock_irqrestore(&ps->irq_lock, flags); } -static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_pearl_state *priv) +static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_pearl_state *ps) { unsigned long flags; - spin_lock_irqsave(&priv->irq_lock, flags); - writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base)); - spin_unlock_irqrestore(&priv->irq_lock, flags); + spin_lock_irqsave(&ps->irq_lock, flags); + writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base)); + spin_unlock_irqrestore(&ps->irq_lock, flags); } -static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_pearl_state *priv) +static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_pearl_state *ps) { unsigned long flags; - spin_lock_irqsave(&priv->irq_lock, flags); - writel(0x0, PCIE_HDP_INT_EN(priv->pcie_reg_base)); - spin_unlock_irqrestore(&priv->irq_lock, flags); + spin_lock_irqsave(&ps->irq_lock, flags); + writel(0x0, PCIE_HDP_INT_EN(ps->pcie_reg_base)); + spin_unlock_irqrestore(&ps->irq_lock, flags); } -static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_pearl_state *priv) +static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_pearl_state *ps) { unsigned long flags; - spin_lock_irqsave(&priv->irq_lock, flags); - priv->pcie_irq_mask |= PCIE_HDP_INT_RX_BITS; - writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base)); - spin_unlock_irqrestore(&priv->irq_lock, flags); + spin_lock_irqsave(&ps->irq_lock, flags); + ps->pcie_irq_mask |= PCIE_HDP_INT_RX_BITS; + writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base)); + spin_unlock_irqrestore(&ps->irq_lock, flags); } -static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_pearl_state *priv) +static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_pearl_state *ps) { unsigned long flags; - spin_lock_irqsave(&priv->irq_lock, flags); - priv->pcie_irq_mask &= ~PCIE_HDP_INT_RX_BITS; - writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base)); - spin_unlock_irqrestore(&priv->irq_lock, flags); + spin_lock_irqsave(&ps->irq_lock, flags); + ps->pcie_irq_mask &= ~PCIE_HDP_INT_RX_BITS; + writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base)); + spin_unlock_irqrestore(&ps->irq_lock, flags); } -static inline void qtnf_en_txdone_irq(struct qtnf_pcie_pearl_state *priv) +static inline void qtnf_en_txdone_irq(struct qtnf_pcie_pearl_state *ps) { unsigned long flags; - spin_lock_irqsave(&priv->irq_lock, flags); - priv->pcie_irq_mask |= PCIE_HDP_INT_TX_BITS; - writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base)); - spin_unlock_irqrestore(&priv->irq_lock, flags); + spin_lock_irqsave(&ps->irq_lock, flags); + ps->pcie_irq_mask |= PCIE_HDP_INT_TX_BITS; + writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base)); + spin_unlock_irqrestore(&ps->irq_lock, flags); } -static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_pearl_state *priv) +static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_pearl_state *ps) { unsigned long flags; - spin_lock_irqsave(&priv->irq_lock, flags); - priv->pcie_irq_mask &= ~PCIE_HDP_INT_TX_BITS; - writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base)); - spin_unlock_irqrestore(&priv->irq_lock, flags); + spin_lock_irqsave(&ps->irq_lock, flags); + ps->pcie_irq_mask &= ~PCIE_HDP_INT_TX_BITS; + writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base)); + spin_unlock_irqrestore(&ps->irq_lock, flags); } -static void qtnf_pcie_init_irq(struct qtnf_pcie_pearl_state *priv) +static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv) { struct pci_dev *pdev = priv->pdev; @@ -261,9 +216,9 @@ static void qtnf_pcie_init_irq(struct qtnf_pcie_pearl_state *priv) } } -static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *priv) +static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *ps) { - void __iomem *reg = priv->sysctl_bar + PEARL_PCIE_CFG0_OFFSET; + void __iomem *reg = ps->base.sysctl_bar + PEARL_PCIE_CFG0_OFFSET; u32 cfg; cfg = readl(reg); @@ -271,28 +226,28 @@ static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *priv) qtnf_non_posted_write(cfg, reg); } -static void qtnf_reset_card(struct qtnf_pcie_pearl_state *priv) +static void qtnf_reset_card(struct qtnf_pcie_pearl_state *ps) { const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_EP_RESET); - void __iomem *reg = priv->sysctl_bar + + void __iomem *reg = ps->base.sysctl_bar + QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET; qtnf_non_posted_write(data, reg); msleep(QTN_EP_RESET_WAIT_MS); - pci_restore_state(priv->pdev); + pci_restore_state(ps->base.pdev); } static void qtnf_ipc_gen_ep_int(void *arg) { - const struct qtnf_pcie_pearl_state *priv = arg; + const struct qtnf_pcie_pearl_state *ps = arg; const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_IPC_IRQ); - void __iomem *reg = priv->sysctl_bar + + void __iomem *reg = ps->base.sysctl_bar + QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET; qtnf_non_posted_write(data, reg); } -static void __iomem *qtnf_map_bar(struct qtnf_pcie_pearl_state *priv, u8 index) +static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 index) { void __iomem *vaddr; dma_addr_t busaddr; @@ -317,7 +272,7 @@ static void __iomem *qtnf_map_bar(struct qtnf_pcie_pearl_state *priv, u8 index) static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t len) { - struct qtnf_pcie_pearl_state *priv = arg; + struct qtnf_pcie_bus_priv *priv = arg; struct qtnf_bus *bus = pci_get_drvdata(priv->pdev); struct sk_buff *skb; @@ -338,35 +293,36 @@ static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t len) qtnf_trans_handle_rx_ctl_packet(bus, skb); } -static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pearl_state *priv) +static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pearl_state *ps) { struct qtnf_shm_ipc_region __iomem *ipc_tx_reg; struct qtnf_shm_ipc_region __iomem *ipc_rx_reg; - const struct qtnf_shm_ipc_int ipc_int = { qtnf_ipc_gen_ep_int, priv }; + const struct qtnf_shm_ipc_int ipc_int = { qtnf_ipc_gen_ep_int, ps }; const struct qtnf_shm_ipc_rx_callback rx_callback = { - qtnf_pcie_control_rx_callback, priv }; + qtnf_pcie_control_rx_callback, ps }; - ipc_tx_reg = &priv->bda->bda_shm_reg1; - ipc_rx_reg = &priv->bda->bda_shm_reg2; + ipc_tx_reg = &ps->bda->bda_shm_reg1; + ipc_rx_reg = &ps->bda->bda_shm_reg2; - qtnf_shm_ipc_init(&priv->shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND, - ipc_tx_reg, priv->workqueue, + qtnf_shm_ipc_init(&ps->base.shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND, + ipc_tx_reg, ps->base.workqueue, &ipc_int, &rx_callback); - qtnf_shm_ipc_init(&priv->shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND, - ipc_rx_reg, priv->workqueue, + qtnf_shm_ipc_init(&ps->base.shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND, + ipc_rx_reg, ps->base.workqueue, &ipc_int, &rx_callback); return 0; } -static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_pearl_state *priv) +static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv) { qtnf_shm_ipc_free(&priv->shm_ipc_ep_in); qtnf_shm_ipc_free(&priv->shm_ipc_ep_out); } -static int qtnf_pcie_init_memory(struct qtnf_pcie_pearl_state *priv) +static int qtnf_pcie_init_memory(struct qtnf_pcie_pearl_state *ps) { + struct qtnf_pcie_bus_priv *priv = &ps->base; int ret = -ENOMEM; priv->sysctl_bar = qtnf_map_bar(priv, QTN_SYSCTL_BAR); @@ -387,14 +343,14 @@ static int qtnf_pcie_init_memory(struct qtnf_pcie_pearl_state *priv) return ret; } - priv->pcie_reg_base = priv->dmareg_bar; - priv->bda = priv->epmem_bar; - writel(priv->msi_enabled, &priv->bda->bda_rc_msi_enabled); + ps->pcie_reg_base = priv->dmareg_bar; + ps->bda = priv->epmem_bar; + writel(priv->msi_enabled, &ps->bda->bda_rc_msi_enabled); return 0; } -static void qtnf_tune_pcie_mps(struct qtnf_pcie_pearl_state *priv) +static void qtnf_tune_pcie_mps(struct qtnf_pcie_bus_priv *priv) { struct pci_dev *pdev = priv->pdev; struct pci_dev *parent; @@ -466,7 +422,7 @@ static int qtnf_poll_state(__le32 __iomem *reg, u32 state, u32 delay_in_ms) return 0; } -static int alloc_skb_array(struct qtnf_pcie_pearl_state *priv) +static int alloc_skb_array(struct qtnf_pcie_bus_priv *priv) { struct sk_buff **vaddr; int len; @@ -486,8 +442,9 @@ static int alloc_skb_array(struct qtnf_pcie_pearl_state *priv) return 0; } -static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv) +static int alloc_bd_table(struct qtnf_pcie_pearl_state *ps) { + struct qtnf_pcie_bus_priv *priv = &ps->base; dma_addr_t paddr; void *vaddr; int len; @@ -503,12 +460,12 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv) memset(vaddr, 0, len); - priv->bd_table_vaddr = vaddr; - priv->bd_table_paddr = paddr; - priv->bd_table_len = len; + ps->bd_table_vaddr = vaddr; + ps->bd_table_paddr = paddr; + ps->bd_table_len = len; - priv->tx_bd_vbase = vaddr; - priv->tx_bd_pbase = paddr; + ps->tx_bd_vbase = vaddr; + ps->tx_bd_pbase = paddr; pr_debug("TX descriptor table: vaddr=0x%p paddr=%pad\n", vaddr, &paddr); @@ -520,25 +477,26 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv) vaddr = ((struct qtnf_pearl_tx_bd *)vaddr) + priv->tx_bd_num; paddr += priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd); - priv->rx_bd_vbase = vaddr; - priv->rx_bd_pbase = paddr; + ps->rx_bd_vbase = vaddr; + ps->rx_bd_pbase = paddr; #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT writel(QTN_HOST_HI32(paddr), - PCIE_HDP_TX_HOST_Q_BASE_H(priv->pcie_reg_base)); + PCIE_HDP_TX_HOST_Q_BASE_H(ps->pcie_reg_base)); #endif writel(QTN_HOST_LO32(paddr), - PCIE_HDP_TX_HOST_Q_BASE_L(priv->pcie_reg_base)); + PCIE_HDP_TX_HOST_Q_BASE_L(ps->pcie_reg_base)); writel(priv->rx_bd_num | (sizeof(struct qtnf_pearl_rx_bd)) << 16, - PCIE_HDP_TX_HOST_Q_SZ_CTRL(priv->pcie_reg_base)); + PCIE_HDP_TX_HOST_Q_SZ_CTRL(ps->pcie_reg_base)); pr_debug("RX descriptor table: vaddr=0x%p paddr=%pad\n", vaddr, &paddr); return 0; } -static int skb2rbd_attach(struct qtnf_pcie_pearl_state *priv, u16 index) +static int skb2rbd_attach(struct qtnf_pcie_pearl_state *ps, u16 index) { + struct qtnf_pcie_bus_priv *priv = &ps->base; struct qtnf_pearl_rx_bd *rxbd; struct sk_buff *skb; dma_addr_t paddr; @@ -550,7 +508,7 @@ static int skb2rbd_attach(struct qtnf_pcie_pearl_state *priv, u16 index) } priv->rx_skb[index] = skb; - rxbd = &priv->rx_bd_vbase[index]; + rxbd = &ps->rx_bd_vbase[index]; paddr = pci_map_single(priv->pdev, skb->data, SKB_BUF_SIZE, PCI_DMA_FROMDEVICE); @@ -571,25 +529,25 @@ static int skb2rbd_attach(struct qtnf_pcie_pearl_state *priv, u16 index) #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT writel(QTN_HOST_HI32(paddr), - PCIE_HDP_HHBM_BUF_PTR_H(priv->pcie_reg_base)); + PCIE_HDP_HHBM_BUF_PTR_H(ps->pcie_reg_base)); #endif writel(QTN_HOST_LO32(paddr), - PCIE_HDP_HHBM_BUF_PTR(priv->pcie_reg_base)); + PCIE_HDP_HHBM_BUF_PTR(ps->pcie_reg_base)); - writel(index, PCIE_HDP_TX_HOST_Q_WR_PTR(priv->pcie_reg_base)); + writel(index, PCIE_HDP_TX_HOST_Q_WR_PTR(ps->pcie_reg_base)); return 0; } -static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *priv) +static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps) { u16 i; int ret = 0; - memset(priv->rx_bd_vbase, 0x0, - priv->rx_bd_num * sizeof(struct qtnf_pearl_rx_bd)); + memset(ps->rx_bd_vbase, 0x0, + ps->base.rx_bd_num * sizeof(struct qtnf_pearl_rx_bd)); - for (i = 0; i < priv->rx_bd_num; i++) { - ret = skb2rbd_attach(priv, i); + for (i = 0; i < ps->base.rx_bd_num; i++) { + ret = skb2rbd_attach(ps, i); if (ret) break; } @@ -598,8 +556,9 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *priv) } /* all rx/tx activity should have ceased before calling this function */ -static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *priv) +static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *ps) { + struct qtnf_pcie_bus_priv *priv = &ps->base; struct qtnf_pearl_tx_bd *txbd; struct qtnf_pearl_rx_bd *rxbd; struct sk_buff *skb; @@ -609,7 +568,7 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *priv) /* free rx buffers */ for (i = 0; i < priv->rx_bd_num; i++) { if (priv->rx_skb && priv->rx_skb[i]) { - rxbd = &priv->rx_bd_vbase[i]; + rxbd = &ps->rx_bd_vbase[i]; skb = priv->rx_skb[i]; paddr = QTN_HOST_ADDR(le32_to_cpu(rxbd->addr_h), le32_to_cpu(rxbd->addr)); @@ -623,7 +582,7 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *priv) /* free tx buffers */ for (i = 0; i < priv->tx_bd_num; i++) { if (priv->tx_skb && priv->tx_skb[i]) { - txbd = &priv->tx_bd_vbase[i]; + txbd = &ps->tx_bd_vbase[i]; skb = priv->tx_skb[i]; paddr = QTN_HOST_ADDR(le32_to_cpu(txbd->addr_h), le32_to_cpu(txbd->addr)); @@ -635,26 +594,27 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *priv) } } -static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state *priv) +static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state *ps) { u32 val; - val = readl(PCIE_HHBM_CONFIG(priv->pcie_reg_base)); + val = readl(PCIE_HHBM_CONFIG(ps->pcie_reg_base)); val |= HHBM_CONFIG_SOFT_RESET; - writel(val, PCIE_HHBM_CONFIG(priv->pcie_reg_base)); + writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base)); usleep_range(50, 100); val &= ~HHBM_CONFIG_SOFT_RESET; #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT val |= HHBM_64BIT; #endif - writel(val, PCIE_HHBM_CONFIG(priv->pcie_reg_base)); - writel(priv->rx_bd_num, PCIE_HHBM_Q_LIMIT_REG(priv->pcie_reg_base)); + writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base)); + writel(ps->base.rx_bd_num, PCIE_HHBM_Q_LIMIT_REG(ps->pcie_reg_base)); return 0; } -static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *priv) +static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *ps) { + struct qtnf_pcie_bus_priv *priv = &ps->base; int ret; u32 val; @@ -689,7 +649,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *priv) return -EINVAL; } - ret = qtnf_hhbm_init(priv); + ret = qtnf_hhbm_init(ps); if (ret) { pr_err("failed to init h/w queues\n"); return ret; @@ -701,13 +661,13 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *priv) return ret; } - ret = alloc_bd_table(priv); + ret = alloc_bd_table(ps); if (ret) { pr_err("failed to allocate bd table\n"); return ret; } - ret = alloc_rx_buffers(priv); + ret = alloc_rx_buffers(ps); if (ret) { pr_err("failed to allocate rx buffers\n"); return ret; @@ -716,8 +676,9 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *priv) return ret; } -static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *priv) +static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *ps) { + struct qtnf_pcie_bus_priv *priv = &ps->base; struct qtnf_pearl_tx_bd *txbd; struct sk_buff *skb; unsigned long flags; @@ -728,7 +689,7 @@ static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *priv) spin_lock_irqsave(&priv->tx_reclaim_lock, flags); - tx_done_index = readl(PCIE_HDP_RX0DMA_CNT(priv->pcie_reg_base)) + tx_done_index = readl(PCIE_HDP_RX0DMA_CNT(ps->pcie_reg_base)) & (priv->tx_bd_num - 1); i = priv->tx_bd_r_index; @@ -736,7 +697,7 @@ static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *priv) while (CIRC_CNT(tx_done_index, i, priv->tx_bd_num)) { skb = priv->tx_skb[i]; if (likely(skb)) { - txbd = &priv->tx_bd_vbase[i]; + txbd = &ps->tx_bd_vbase[i]; paddr = QTN_HOST_ADDR(le32_to_cpu(txbd->addr_h), le32_to_cpu(txbd->addr)); pci_unmap_single(priv->pdev, paddr, skb->len, @@ -767,11 +728,13 @@ static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *priv) spin_unlock_irqrestore(&priv->tx_reclaim_lock, flags); } -static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *priv) +static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *ps) { + struct qtnf_pcie_bus_priv *priv = &ps->base; + if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index, priv->tx_bd_num)) { - qtnf_pcie_data_tx_reclaim(priv); + qtnf_pcie_data_tx_reclaim(ps); if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index, priv->tx_bd_num)) { @@ -786,7 +749,8 @@ static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *priv) static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) { - struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); + struct qtnf_pcie_bus_priv *priv = &ps->base; dma_addr_t txbd_paddr, skb_paddr; struct qtnf_pearl_tx_bd *txbd; unsigned long flags; @@ -796,7 +760,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) spin_lock_irqsave(&priv->tx_lock, flags); - if (!qtnf_tx_queue_ready(priv)) { + if (!qtnf_tx_queue_ready(ps)) { if (skb->dev) { netif_tx_stop_all_queues(skb->dev); priv->tx_stopped = 1; @@ -818,7 +782,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) goto tx_done; } - txbd = &priv->tx_bd_vbase[i]; + txbd = &ps->tx_bd_vbase[i]; txbd->addr = cpu_to_le32(QTN_HOST_LO32(skb_paddr)); txbd->addr_h = cpu_to_le32(QTN_HOST_HI32(skb_paddr)); @@ -829,14 +793,14 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) dma_wmb(); /* write new TX descriptor to PCIE_RX_FIFO on EP */ - txbd_paddr = priv->tx_bd_pbase + i * sizeof(struct qtnf_pearl_tx_bd); + txbd_paddr = ps->tx_bd_pbase + i * sizeof(struct qtnf_pearl_tx_bd); #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT writel(QTN_HOST_HI32(txbd_paddr), - PCIE_HDP_HOST_WR_DESC0_H(priv->pcie_reg_base)); + PCIE_HDP_HOST_WR_DESC0_H(ps->pcie_reg_base)); #endif writel(QTN_HOST_LO32(txbd_paddr), - PCIE_HDP_HOST_WR_DESC0(priv->pcie_reg_base)); + PCIE_HDP_HOST_WR_DESC0(ps->pcie_reg_base)); if (++i >= priv->tx_bd_num) i = 0; @@ -854,14 +818,14 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) priv->tx_done_count++; spin_unlock_irqrestore(&priv->tx_lock, flags); - qtnf_pcie_data_tx_reclaim(priv); + qtnf_pcie_data_tx_reclaim(ps); return NETDEV_TX_OK; } static int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb) { - struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); int ret; ret = qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len); @@ -877,54 +841,55 @@ static int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb) static irqreturn_t qtnf_interrupt(int irq, void *data) { struct qtnf_bus *bus = (struct qtnf_bus *)data; - struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); + struct qtnf_pcie_bus_priv *priv = &ps->base; u32 status; priv->pcie_irq_count++; - status = readl(PCIE_HDP_INT_STATUS(priv->pcie_reg_base)); + status = readl(PCIE_HDP_INT_STATUS(ps->pcie_reg_base)); qtnf_shm_ipc_irq_handler(&priv->shm_ipc_ep_in); qtnf_shm_ipc_irq_handler(&priv->shm_ipc_ep_out); - if (!(status & priv->pcie_irq_mask)) + if (!(status & ps->pcie_irq_mask)) goto irq_done; if (status & PCIE_HDP_INT_RX_BITS) - priv->pcie_irq_rx_count++; + ps->pcie_irq_rx_count++; if (status & PCIE_HDP_INT_TX_BITS) - priv->pcie_irq_tx_count++; + ps->pcie_irq_tx_count++; if (status & PCIE_HDP_INT_HHBM_UF) - priv->pcie_irq_uf_count++; + ps->pcie_irq_uf_count++; if (status & PCIE_HDP_INT_RX_BITS) { - qtnf_dis_rxdone_irq(priv); + qtnf_dis_rxdone_irq(ps); napi_schedule(&bus->mux_napi); } if (status & PCIE_HDP_INT_TX_BITS) { - qtnf_dis_txdone_irq(priv); + qtnf_dis_txdone_irq(ps); tasklet_hi_schedule(&priv->reclaim_tq); } irq_done: /* H/W workaround: clean all bits, not only enabled */ - qtnf_non_posted_write(~0U, PCIE_HDP_INT_STATUS(priv->pcie_reg_base)); + qtnf_non_posted_write(~0U, PCIE_HDP_INT_STATUS(ps->pcie_reg_base)); if (!priv->msi_enabled) - qtnf_deassert_intx(priv); + qtnf_deassert_intx(ps); return IRQ_HANDLED; } -static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *priv) +static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *ps) { - u16 index = priv->rx_bd_r_index; + u16 index = ps->base.rx_bd_r_index; struct qtnf_pearl_rx_bd *rxbd; u32 descw; - rxbd = &priv->rx_bd_vbase[index]; + rxbd = &ps->rx_bd_vbase[index]; descw = le32_to_cpu(rxbd->info); if (descw & QTN_TXDONE_MASK) @@ -936,7 +901,8 @@ static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *priv) static int qtnf_rx_poll(struct napi_struct *napi, int budget) { struct qtnf_bus *bus = container_of(napi, struct qtnf_bus, mux_napi); - struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); + struct qtnf_pcie_bus_priv *priv = &ps->base; struct net_device *ndev = NULL; struct sk_buff *skb = NULL; int processed = 0; @@ -950,13 +916,11 @@ static int qtnf_rx_poll(struct napi_struct *napi, int budget) int ret; while (processed < budget) { - - - if (!qtnf_rx_data_ready(priv)) + if (!qtnf_rx_data_ready(ps)) goto rx_out; r_idx = priv->rx_bd_r_index; - rxbd = &priv->rx_bd_vbase[r_idx]; + rxbd = &ps->rx_bd_vbase[r_idx]; descw = le32_to_cpu(rxbd->info); skb = priv->rx_skb[r_idx]; @@ -1018,7 +982,7 @@ static int qtnf_rx_poll(struct napi_struct *napi, int budget) if (++w_idx >= priv->rx_bd_num) w_idx = 0; - ret = skb2rbd_attach(priv, w_idx); + ret = skb2rbd_attach(ps, w_idx); if (ret) { pr_err("failed to allocate new rx_skb[%d]\n", w_idx); @@ -1032,7 +996,7 @@ static int qtnf_rx_poll(struct napi_struct *napi, int budget) rx_out: if (processed < budget) { napi_complete(napi); - qtnf_en_rxdone_irq(priv); + qtnf_en_rxdone_irq(ps); } return processed; @@ -1041,25 +1005,25 @@ static int qtnf_rx_poll(struct napi_struct *napi, int budget) static void qtnf_pcie_data_tx_timeout(struct qtnf_bus *bus, struct net_device *ndev) { - struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); - tasklet_hi_schedule(&priv->reclaim_tq); + tasklet_hi_schedule(&ps->base.reclaim_tq); } static void qtnf_pcie_data_rx_start(struct qtnf_bus *bus) { - struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); - qtnf_enable_hdp_irqs(priv); + qtnf_enable_hdp_irqs(ps); napi_enable(&bus->mux_napi); } static void qtnf_pcie_data_rx_stop(struct qtnf_bus *bus) { - struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); napi_disable(&bus->mux_napi); - qtnf_disable_hdp_irqs(priv); + qtnf_disable_hdp_irqs(ps); } static const struct qtnf_bus_ops qtnf_pcie_bus_ops = { @@ -1076,7 +1040,7 @@ static const struct qtnf_bus_ops qtnf_pcie_bus_ops = { static int qtnf_dbg_mps_show(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); + struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); seq_printf(s, "%d\n", priv->mps); @@ -1086,7 +1050,7 @@ static int qtnf_dbg_mps_show(struct seq_file *s, void *data) static int qtnf_dbg_msi_show(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); + struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); seq_printf(s, "%u\n", priv->msi_enabled); @@ -1096,20 +1060,20 @@ static int qtnf_dbg_msi_show(struct seq_file *s, void *data) static int qtnf_dbg_irq_stats(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); - u32 reg = readl(PCIE_HDP_INT_EN(priv->pcie_reg_base)); + struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus); + u32 reg = readl(PCIE_HDP_INT_EN(ps->pcie_reg_base)); u32 status; - seq_printf(s, "pcie_irq_count(%u)\n", priv->pcie_irq_count); - seq_printf(s, "pcie_irq_tx_count(%u)\n", priv->pcie_irq_tx_count); + seq_printf(s, "pcie_irq_count(%u)\n", ps->base.pcie_irq_count); + seq_printf(s, "pcie_irq_tx_count(%u)\n", ps->pcie_irq_tx_count); status = reg & PCIE_HDP_INT_TX_BITS; seq_printf(s, "pcie_irq_tx_status(%s)\n", (status == PCIE_HDP_INT_TX_BITS) ? "EN" : "DIS"); - seq_printf(s, "pcie_irq_rx_count(%u)\n", priv->pcie_irq_rx_count); + seq_printf(s, "pcie_irq_rx_count(%u)\n", ps->pcie_irq_rx_count); status = reg & PCIE_HDP_INT_RX_BITS; seq_printf(s, "pcie_irq_rx_status(%s)\n", (status == PCIE_HDP_INT_RX_BITS) ? "EN" : "DIS"); - seq_printf(s, "pcie_irq_uf_count(%u)\n", priv->pcie_irq_uf_count); + seq_printf(s, "pcie_irq_uf_count(%u)\n", ps->pcie_irq_uf_count); status = reg & PCIE_HDP_INT_HHBM_UF; seq_printf(s, "pcie_irq_hhbm_uf_status(%s)\n", (status == PCIE_HDP_INT_HHBM_UF) ? "EN" : "DIS"); @@ -1120,7 +1084,8 @@ static int qtnf_dbg_irq_stats(struct seq_file *s, void *data) static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus); + struct qtnf_pcie_bus_priv *priv = &ps->base; seq_printf(s, "tx_full_count(%u)\n", priv->tx_full_count); seq_printf(s, "tx_done_count(%u)\n", priv->tx_done_count); @@ -1129,7 +1094,7 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data) seq_printf(s, "tx_bd_r_index(%u)\n", priv->tx_bd_r_index); seq_printf(s, "tx_bd_p_index(%u)\n", - readl(PCIE_HDP_RX0DMA_CNT(priv->pcie_reg_base)) + readl(PCIE_HDP_RX0DMA_CNT(ps->pcie_reg_base)) & (priv->tx_bd_num - 1)); seq_printf(s, "tx_bd_w_index(%u)\n", priv->tx_bd_w_index); seq_printf(s, "tx queue len(%u)\n", @@ -1138,7 +1103,7 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data) seq_printf(s, "rx_bd_r_index(%u)\n", priv->rx_bd_r_index); seq_printf(s, "rx_bd_p_index(%u)\n", - readl(PCIE_HDP_TX0DMA_CNT(priv->pcie_reg_base)) + readl(PCIE_HDP_TX0DMA_CNT(ps->pcie_reg_base)) & (priv->rx_bd_num - 1)); seq_printf(s, "rx_bd_w_index(%u)\n", priv->rx_bd_w_index); seq_printf(s, "rx alloc queue len(%u)\n", @@ -1151,7 +1116,7 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data) static int qtnf_dbg_shm_stats(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_pearl_state *priv = get_bus_priv(bus); + struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n", priv->shm_ipc_ep_in.tx_packet_count); @@ -1165,10 +1130,10 @@ static int qtnf_dbg_shm_stats(struct seq_file *s, void *data) return 0; } -static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *priv, uint32_t size, +static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *ps, uint32_t size, int blk, const u8 *pblk, const u8 *fw) { - struct pci_dev *pdev = priv->pdev; + struct pci_dev *pdev = ps->base.pdev; struct qtnf_bus *bus = pci_get_drvdata(pdev); struct qtnf_pearl_fw_hdr *hdr; @@ -1214,7 +1179,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *priv, uint32_t size, } static int -qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, const u8 *fw, u32 fw_size) +qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, const u8 *fw, u32 fw_size) { int blk_size = QTN_PCIE_FW_BUFSZ - sizeof(struct qtnf_pearl_fw_hdr); int blk_count = fw_size / blk_size + ((fw_size % blk_size) ? 1 : 0); @@ -1231,25 +1196,25 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, const u8 *fw, u32 fw_size) return -ETIMEDOUT; } - len = qtnf_ep_fw_send(priv, fw_size, blk, pblk, fw); + len = qtnf_ep_fw_send(ps, fw_size, blk, pblk, fw); if (len <= 0) continue; if (!((blk + 1) & QTN_PCIE_FW_DLMASK) || (blk == (blk_count - 1))) { - qtnf_set_state(&priv->bda->bda_rc_state, + qtnf_set_state(&ps->bda->bda_rc_state, QTN_RC_FW_SYNC); - if (qtnf_poll_state(&priv->bda->bda_ep_state, + if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_SYNC, QTN_FW_DL_TIMEOUT_MS)) { pr_err("FW upload failed: SYNC timed out\n"); return -ETIMEDOUT; } - qtnf_clear_state(&priv->bda->bda_ep_state, + qtnf_clear_state(&ps->bda->bda_ep_state, QTN_EP_FW_SYNC); - if (qtnf_is_state(&priv->bda->bda_ep_state, + if (qtnf_is_state(&ps->bda->bda_ep_state, QTN_EP_FW_RETRY)) { if (blk == (blk_count - 1)) { int last_round = @@ -1262,14 +1227,14 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, const u8 *fw, u32 fw_size) pblk -= QTN_PCIE_FW_DLMASK * blk_size; } - qtnf_clear_state(&priv->bda->bda_ep_state, + qtnf_clear_state(&ps->bda->bda_ep_state, QTN_EP_FW_RETRY); pr_warn("FW upload retry: block #%d\n", blk); continue; } - qtnf_pcie_data_tx_reclaim(priv); + qtnf_pcie_data_tx_reclaim(ps); } pblk += len; @@ -1283,8 +1248,8 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, const u8 *fw, u32 fw_size) static void qtnf_fw_work_handler(struct work_struct *work) { struct qtnf_bus *bus = container_of(work, struct qtnf_bus, fw_work); - struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); - struct pci_dev *pdev = priv->pdev; + struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); + struct pci_dev *pdev = ps->base.pdev; const struct firmware *fw; int ret; u32 state = QTN_RC_FW_LOADRDY | QTN_RC_FW_QLINK; @@ -1300,9 +1265,9 @@ static void qtnf_fw_work_handler(struct work_struct *work) } } - qtnf_set_state(&priv->bda->bda_rc_state, state); + qtnf_set_state(&ps->bda->bda_rc_state, state); - if (qtnf_poll_state(&priv->bda->bda_ep_state, QTN_EP_FW_LOADRDY, + if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY, QTN_FW_DL_TIMEOUT_MS)) { pr_err("card is not ready\n"); @@ -1312,14 +1277,14 @@ static void qtnf_fw_work_handler(struct work_struct *work) goto fw_load_fail; } - qtnf_clear_state(&priv->bda->bda_ep_state, QTN_EP_FW_LOADRDY); + qtnf_clear_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY); if (flashboot) { pr_info("booting firmware from flash\n"); } else { pr_info("starting firmware upload: %s\n", fwname); - ret = qtnf_ep_fw_load(priv, fw->data, fw->size); + ret = qtnf_ep_fw_load(ps, fw->data, fw->size); release_firmware(fw); if (ret) { pr_err("firmware upload error\n"); @@ -1327,7 +1292,7 @@ static void qtnf_fw_work_handler(struct work_struct *work) } } - if (qtnf_poll_state(&priv->bda->bda_ep_state, QTN_EP_FW_DONE, + if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_DONE, QTN_FW_DL_TIMEOUT_MS)) { pr_err("firmware bringup timed out\n"); goto fw_load_fail; @@ -1336,7 +1301,7 @@ static void qtnf_fw_work_handler(struct work_struct *work) bus->fw_state = QTNF_FW_STATE_FW_DNLD_DONE; pr_info("firmware is up and running\n"); - if (qtnf_poll_state(&priv->bda->bda_ep_state, + if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_QLINK_DONE, QTN_FW_QLINK_TIMEOUT_MS)) { pr_err("firmware runtime failure\n"); goto fw_load_fail; @@ -1367,7 +1332,7 @@ static void qtnf_fw_work_handler(struct work_struct *work) static void qtnf_bringup_fw_async(struct qtnf_bus *bus) { - struct qtnf_pcie_pearl_state *priv = (void *)get_bus_priv(bus); + struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); struct pci_dev *pdev = priv->pdev; get_device(&pdev->dev); @@ -1377,56 +1342,56 @@ static void qtnf_bringup_fw_async(struct qtnf_bus *bus) static void qtnf_reclaim_tasklet_fn(unsigned long data) { - struct qtnf_pcie_pearl_state *priv = (void *)data; + struct qtnf_pcie_pearl_state *ps = (void *)data; - qtnf_pcie_data_tx_reclaim(priv); - qtnf_en_txdone_irq(priv); + qtnf_pcie_data_tx_reclaim(ps); + qtnf_en_txdone_irq(ps); } static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) { - struct qtnf_pcie_pearl_state *pcie_priv; + struct qtnf_pcie_pearl_state *ps; struct qtnf_bus *bus; int ret; bus = devm_kzalloc(&pdev->dev, - sizeof(*bus) + sizeof(*pcie_priv), GFP_KERNEL); + sizeof(*bus) + sizeof(*ps), GFP_KERNEL); if (!bus) return -ENOMEM; - pcie_priv = get_bus_priv(bus); + ps = get_bus_priv(bus); pci_set_drvdata(pdev, bus); bus->bus_ops = &qtnf_pcie_bus_ops; bus->dev = &pdev->dev; bus->fw_state = QTNF_FW_STATE_RESET; - pcie_priv->pdev = pdev; + ps->base.pdev = pdev; init_completion(&bus->firmware_init_complete); mutex_init(&bus->bus_lock); - spin_lock_init(&pcie_priv->tx_lock); - spin_lock_init(&pcie_priv->irq_lock); - spin_lock_init(&pcie_priv->tx_reclaim_lock); + spin_lock_init(&ps->base.tx_lock); + spin_lock_init(&ps->irq_lock); + spin_lock_init(&ps->base.tx_reclaim_lock); /* init stats */ - pcie_priv->tx_full_count = 0; - pcie_priv->tx_done_count = 0; - pcie_priv->pcie_irq_count = 0; - pcie_priv->pcie_irq_rx_count = 0; - pcie_priv->pcie_irq_tx_count = 0; - pcie_priv->pcie_irq_uf_count = 0; - pcie_priv->tx_reclaim_done = 0; - pcie_priv->tx_reclaim_req = 0; - - tasklet_init(&pcie_priv->reclaim_tq, qtnf_reclaim_tasklet_fn, - (unsigned long)pcie_priv); + ps->base.tx_full_count = 0; + ps->base.tx_done_count = 0; + ps->base.pcie_irq_count = 0; + ps->pcie_irq_rx_count = 0; + ps->pcie_irq_tx_count = 0; + ps->pcie_irq_uf_count = 0; + ps->base.tx_reclaim_done = 0; + ps->base.tx_reclaim_req = 0; + + tasklet_init(&ps->base.reclaim_tq, qtnf_reclaim_tasklet_fn, + (unsigned long)ps); init_dummy_netdev(&bus->mux_dev); netif_napi_add(&bus->mux_dev, &bus->mux_napi, qtnf_rx_poll, 10); - pcie_priv->workqueue = create_singlethread_workqueue("QTNF_PEARL_PCIE"); - if (!pcie_priv->workqueue) { + ps->base.workqueue = create_singlethread_workqueue("QTNF_PEARL_PCIE"); + if (!ps->base.workqueue) { pr_err("failed to alloc bus workqueue\n"); ret = -ENODEV; goto err_init; @@ -1438,7 +1403,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_base; } - qtnf_tune_pcie_mps(pcie_priv); + qtnf_tune_pcie_mps(&ps->base); ret = pcim_enable_device(pdev); if (ret) { @@ -1459,9 +1424,9 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) } pci_set_master(pdev); - qtnf_pcie_init_irq(pcie_priv); + qtnf_pcie_init_irq(&ps->base); - ret = qtnf_pcie_init_memory(pcie_priv); + ret = qtnf_pcie_init_memory(ps); if (ret < 0) { pr_err("PCIE memory init failed\n"); goto err_base; @@ -1469,23 +1434,23 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_save_state(pdev); - ret = qtnf_pcie_init_shm_ipc(pcie_priv); + ret = qtnf_pcie_init_shm_ipc(ps); if (ret < 0) { pr_err("PCIE SHM IPC init failed\n"); goto err_base; } - ret = qtnf_pcie_init_xfer(pcie_priv); + ret = qtnf_pcie_init_xfer(ps); if (ret) { pr_err("PCIE xfer init failed\n"); goto err_ipc; } /* init default irq settings */ - qtnf_init_hdp_irqs(pcie_priv); + qtnf_init_hdp_irqs(ps); /* start with disabled irqs */ - qtnf_disable_hdp_irqs(pcie_priv); + qtnf_disable_hdp_irqs(ps); ret = devm_request_irq(&pdev->dev, pdev->irq, &qtnf_interrupt, 0, "qtnf_pcie_irq", (void *)bus); @@ -1499,18 +1464,18 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) return 0; err_xfer: - qtnf_free_xfer_buffers(pcie_priv); + qtnf_free_xfer_buffers(ps); err_ipc: - qtnf_pcie_free_shm_ipc(pcie_priv); + qtnf_pcie_free_shm_ipc(&ps->base); err_base: - flush_workqueue(pcie_priv->workqueue); - destroy_workqueue(pcie_priv->workqueue); - netif_napi_del(&bus->mux_napi); + flush_workqueue(ps->base.workqueue); + destroy_workqueue(ps->base.workqueue); err_init: - tasklet_kill(&pcie_priv->reclaim_tq); + tasklet_kill(&ps->base.reclaim_tq); + netif_napi_del(&bus->mux_napi); pci_set_drvdata(pdev, NULL); return ret; @@ -1518,7 +1483,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) static void qtnf_pcie_remove(struct pci_dev *pdev) { - struct qtnf_pcie_pearl_state *priv; + struct qtnf_pcie_pearl_state *ps; struct qtnf_bus *bus; bus = pci_get_drvdata(pdev); @@ -1531,18 +1496,16 @@ static void qtnf_pcie_remove(struct pci_dev *pdev) bus->fw_state == QTNF_FW_STATE_EP_DEAD) qtnf_core_detach(bus); - priv = get_bus_priv(bus); - + ps = get_bus_priv(bus); + qtnf_reset_card(ps); netif_napi_del(&bus->mux_napi); - flush_workqueue(priv->workqueue); - destroy_workqueue(priv->workqueue); - tasklet_kill(&priv->reclaim_tq); + flush_workqueue(ps->base.workqueue); + destroy_workqueue(ps->base.workqueue); + tasklet_kill(&ps->base.reclaim_tq); - qtnf_free_xfer_buffers(priv); + qtnf_free_xfer_buffers(ps); + qtnf_pcie_free_shm_ipc(&ps->base); qtnf_debugfs_remove(bus); - - qtnf_pcie_free_shm_ipc(priv); - qtnf_reset_card(priv); } #ifdef CONFIG_PM_SLEEP diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h index af528b8..b87505d 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h @@ -43,11 +43,6 @@ #define QTN_RC_FW_LOADRDY BIT(8) #define QTN_RC_FW_SYNC BIT(9) -/* state transition timeouts */ -#define QTN_FW_DL_TIMEOUT_MS 3000 -#define QTN_FW_QLINK_TIMEOUT_MS 30000 -#define QTN_EP_RESET_WAIT_MS 1000 - #define PCIE_HDP_INT_RX_BITS (0 \ | PCIE_HDP_INT_EP_TXDMA \ | PCIE_HDP_INT_EP_TXEMPTY \ @@ -77,8 +72,6 @@ #define PCIE_BDA_NAMELEN 32 #define PCIE_HHBM_MAX_SIZE 2048 -#define SKB_BUF_SIZE 2048 - #define QTN_PCIE_BOARDFLG "PCIEQTN" #define QTN_PCIE_FW_DLMASK 0xF #define QTN_PCIE_FW_BUFSZ 2048 From patchwork Mon Sep 24 22:15:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612939 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1BC8F161F for ; Mon, 24 Sep 2018 22:16:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0D6B5297F2 for ; Mon, 24 Sep 2018 22:16:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F2E92297EF; Mon, 24 Sep 2018 22:16:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1AFEA297EF for ; Mon, 24 Sep 2018 22:16:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728574AbeIYEUf (ORCPT ); Tue, 25 Sep 2018 00:20:35 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46852 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728585AbeIYETr (ORCPT ); Tue, 25 Sep 2018 00:19:47 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOH012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 07/11] qtnfmac_pcie: rename platform-specific functions Date: Mon, 24 Sep 2018 15:15:10 -0700 Message-Id: <20180924221514.4273-8-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Rename several functions to indicate that they are platform specific. Signed-off-by: Igor Mitsyanko --- .../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 101 +++++++++++---------- 1 file changed, 52 insertions(+), 49 deletions(-) diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c index 97f3001..fd11dd2 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c @@ -226,7 +226,7 @@ static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *ps) qtnf_non_posted_write(cfg, reg); } -static void qtnf_reset_card(struct qtnf_pcie_pearl_state *ps) +static void qtnf_pearl_reset_ep(struct qtnf_pcie_pearl_state *ps) { const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_EP_RESET); void __iomem *reg = ps->base.sysctl_bar + @@ -237,7 +237,7 @@ static void qtnf_reset_card(struct qtnf_pcie_pearl_state *ps) pci_restore_state(ps->base.pdev); } -static void qtnf_ipc_gen_ep_int(void *arg) +static void qtnf_pcie_pearl_ipc_gen_ep_int(void *arg) { const struct qtnf_pcie_pearl_state *ps = arg; const u32 data = QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_IPC_IRQ); @@ -297,7 +297,8 @@ static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pearl_state *ps) { struct qtnf_shm_ipc_region __iomem *ipc_tx_reg; struct qtnf_shm_ipc_region __iomem *ipc_rx_reg; - const struct qtnf_shm_ipc_int ipc_int = { qtnf_ipc_gen_ep_int, ps }; + const struct qtnf_shm_ipc_int ipc_int = { + qtnf_pcie_pearl_ipc_gen_ep_int, ps }; const struct qtnf_shm_ipc_rx_callback rx_callback = { qtnf_pcie_control_rx_callback, ps }; @@ -442,7 +443,7 @@ static int alloc_skb_array(struct qtnf_pcie_bus_priv *priv) return 0; } -static int alloc_bd_table(struct qtnf_pcie_pearl_state *ps) +static int pearl_alloc_bd_table(struct qtnf_pcie_pearl_state *ps) { struct qtnf_pcie_bus_priv *priv = &ps->base; dma_addr_t paddr; @@ -494,7 +495,7 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state *ps) return 0; } -static int skb2rbd_attach(struct qtnf_pcie_pearl_state *ps, u16 index) +static int pearl_skb2rbd_attach(struct qtnf_pcie_pearl_state *ps, u16 index) { struct qtnf_pcie_bus_priv *priv = &ps->base; struct qtnf_pearl_rx_bd *rxbd; @@ -538,7 +539,7 @@ static int skb2rbd_attach(struct qtnf_pcie_pearl_state *ps, u16 index) return 0; } -static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps) +static int pearl_alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps) { u16 i; int ret = 0; @@ -547,7 +548,7 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps) ps->base.rx_bd_num * sizeof(struct qtnf_pearl_rx_bd)); for (i = 0; i < ps->base.rx_bd_num; i++) { - ret = skb2rbd_attach(ps, i); + ret = pearl_skb2rbd_attach(ps, i); if (ret) break; } @@ -556,7 +557,7 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps) } /* all rx/tx activity should have ceased before calling this function */ -static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *ps) +static void qtnf_pearl_free_xfer_buffers(struct qtnf_pcie_pearl_state *ps) { struct qtnf_pcie_bus_priv *priv = &ps->base; struct qtnf_pearl_tx_bd *txbd; @@ -594,7 +595,7 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *ps) } } -static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state *ps) +static int pearl_hhbm_init(struct qtnf_pcie_pearl_state *ps) { u32 val; @@ -612,7 +613,7 @@ static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state *ps) return 0; } -static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *ps) +static int qtnf_pcie_pearl_init_xfer(struct qtnf_pcie_pearl_state *ps) { struct qtnf_pcie_bus_priv *priv = &ps->base; int ret; @@ -649,7 +650,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *ps) return -EINVAL; } - ret = qtnf_hhbm_init(ps); + ret = pearl_hhbm_init(ps); if (ret) { pr_err("failed to init h/w queues\n"); return ret; @@ -661,13 +662,13 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *ps) return ret; } - ret = alloc_bd_table(ps); + ret = pearl_alloc_bd_table(ps); if (ret) { pr_err("failed to allocate bd table\n"); return ret; } - ret = alloc_rx_buffers(ps); + ret = pearl_alloc_rx_buffers(ps); if (ret) { pr_err("failed to allocate rx buffers\n"); return ret; @@ -676,7 +677,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *ps) return ret; } -static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *ps) +static void qtnf_pearl_data_tx_reclaim(struct qtnf_pcie_pearl_state *ps) { struct qtnf_pcie_bus_priv *priv = &ps->base; struct qtnf_pearl_tx_bd *txbd; @@ -734,7 +735,7 @@ static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *ps) if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index, priv->tx_bd_num)) { - qtnf_pcie_data_tx_reclaim(ps); + qtnf_pearl_data_tx_reclaim(ps); if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index, priv->tx_bd_num)) { @@ -818,7 +819,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) priv->tx_done_count++; spin_unlock_irqrestore(&priv->tx_lock, flags); - qtnf_pcie_data_tx_reclaim(ps); + qtnf_pearl_data_tx_reclaim(ps); return NETDEV_TX_OK; } @@ -838,7 +839,7 @@ static int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb) return ret; } -static irqreturn_t qtnf_interrupt(int irq, void *data) +static irqreturn_t qtnf_pcie_pearl_interrupt(int irq, void *data) { struct qtnf_bus *bus = (struct qtnf_bus *)data; struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); @@ -898,7 +899,7 @@ static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *ps) return 0; } -static int qtnf_rx_poll(struct napi_struct *napi, int budget) +static int qtnf_pcie_pearl_rx_poll(struct napi_struct *napi, int budget) { struct qtnf_bus *bus = container_of(napi, struct qtnf_bus, mux_napi); struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); @@ -982,7 +983,7 @@ static int qtnf_rx_poll(struct napi_struct *napi, int budget) if (++w_idx >= priv->rx_bd_num) w_idx = 0; - ret = skb2rbd_attach(ps, w_idx); + ret = pearl_skb2rbd_attach(ps, w_idx); if (ret) { pr_err("failed to allocate new rx_skb[%d]\n", w_idx); @@ -1026,7 +1027,7 @@ static void qtnf_pcie_data_rx_stop(struct qtnf_bus *bus) qtnf_disable_hdp_irqs(ps); } -static const struct qtnf_bus_ops qtnf_pcie_bus_ops = { +static const struct qtnf_bus_ops qtnf_pcie_pearl_bus_ops = { /* control path methods */ .control_tx = qtnf_pcie_control_tx, @@ -1234,7 +1235,7 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, const u8 *fw, u32 fw_size) continue; } - qtnf_pcie_data_tx_reclaim(ps); + qtnf_pearl_data_tx_reclaim(ps); } pblk += len; @@ -1245,7 +1246,7 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, const u8 *fw, u32 fw_size) return 0; } -static void qtnf_fw_work_handler(struct work_struct *work) +static void qtnf_pearl_fw_work_handler(struct work_struct *work) { struct qtnf_bus *bus = container_of(work, struct qtnf_bus, fw_work); struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); @@ -1336,19 +1337,20 @@ static void qtnf_bringup_fw_async(struct qtnf_bus *bus) struct pci_dev *pdev = priv->pdev; get_device(&pdev->dev); - INIT_WORK(&bus->fw_work, qtnf_fw_work_handler); + INIT_WORK(&bus->fw_work, qtnf_pearl_fw_work_handler); schedule_work(&bus->fw_work); } -static void qtnf_reclaim_tasklet_fn(unsigned long data) +static void qtnf_pearl_reclaim_tasklet_fn(unsigned long data) { struct qtnf_pcie_pearl_state *ps = (void *)data; - qtnf_pcie_data_tx_reclaim(ps); + qtnf_pearl_data_tx_reclaim(ps); qtnf_en_txdone_irq(ps); } -static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) +static int qtnf_pcie_pearl_probe(struct pci_dev *pdev, + const struct pci_device_id *id) { struct qtnf_pcie_pearl_state *ps; struct qtnf_bus *bus; @@ -1362,7 +1364,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) ps = get_bus_priv(bus); pci_set_drvdata(pdev, bus); - bus->bus_ops = &qtnf_pcie_bus_ops; + bus->bus_ops = &qtnf_pcie_pearl_bus_ops; bus->dev = &pdev->dev; bus->fw_state = QTNF_FW_STATE_RESET; ps->base.pdev = pdev; @@ -1383,12 +1385,12 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) ps->base.tx_reclaim_done = 0; ps->base.tx_reclaim_req = 0; - tasklet_init(&ps->base.reclaim_tq, qtnf_reclaim_tasklet_fn, + tasklet_init(&ps->base.reclaim_tq, qtnf_pearl_reclaim_tasklet_fn, (unsigned long)ps); init_dummy_netdev(&bus->mux_dev); netif_napi_add(&bus->mux_dev, &bus->mux_napi, - qtnf_rx_poll, 10); + qtnf_pcie_pearl_rx_poll, 10); ps->base.workqueue = create_singlethread_workqueue("QTNF_PEARL_PCIE"); if (!ps->base.workqueue) { @@ -1440,7 +1442,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_base; } - ret = qtnf_pcie_init_xfer(ps); + ret = qtnf_pcie_pearl_init_xfer(ps); if (ret) { pr_err("PCIE xfer init failed\n"); goto err_ipc; @@ -1452,7 +1454,8 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) /* start with disabled irqs */ qtnf_disable_hdp_irqs(ps); - ret = devm_request_irq(&pdev->dev, pdev->irq, &qtnf_interrupt, 0, + ret = devm_request_irq(&pdev->dev, pdev->irq, + &qtnf_pcie_pearl_interrupt, 0, "qtnf_pcie_irq", (void *)bus); if (ret) { pr_err("failed to request pcie irq %d\n", pdev->irq); @@ -1464,7 +1467,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) return 0; err_xfer: - qtnf_free_xfer_buffers(ps); + qtnf_pearl_free_xfer_buffers(ps); err_ipc: qtnf_pcie_free_shm_ipc(&ps->base); @@ -1481,7 +1484,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) return ret; } -static void qtnf_pcie_remove(struct pci_dev *pdev) +static void qtnf_pcie_pearl_remove(struct pci_dev *pdev) { struct qtnf_pcie_pearl_state *ps; struct qtnf_bus *bus; @@ -1497,24 +1500,24 @@ static void qtnf_pcie_remove(struct pci_dev *pdev) qtnf_core_detach(bus); ps = get_bus_priv(bus); - qtnf_reset_card(ps); + qtnf_pearl_reset_ep(ps); netif_napi_del(&bus->mux_napi); flush_workqueue(ps->base.workqueue); destroy_workqueue(ps->base.workqueue); tasklet_kill(&ps->base.reclaim_tq); - qtnf_free_xfer_buffers(ps); + qtnf_pearl_free_xfer_buffers(ps); qtnf_pcie_free_shm_ipc(&ps->base); qtnf_debugfs_remove(bus); } #ifdef CONFIG_PM_SLEEP -static int qtnf_pcie_suspend(struct device *dev) +static int qtnf_pcie_pearl_suspend(struct device *dev) { return -EOPNOTSUPP; } -static int qtnf_pcie_resume(struct device *dev) +static int qtnf_pcie_pearl_resume(struct device *dev) { return 0; } @@ -1522,8 +1525,8 @@ static int qtnf_pcie_resume(struct device *dev) #ifdef CONFIG_PM_SLEEP /* Power Management Hooks */ -static SIMPLE_DEV_PM_OPS(qtnf_pcie_pm_ops, qtnf_pcie_suspend, - qtnf_pcie_resume); +static SIMPLE_DEV_PM_OPS(qtnf_pcie_pearl_pm_ops, qtnf_pcie_pearl_suspend, + qtnf_pcie_pearl_resume); #endif static const struct pci_device_id qtnf_pcie_devid_table[] = { @@ -1536,32 +1539,32 @@ static const struct pci_device_id qtnf_pcie_devid_table[] = { MODULE_DEVICE_TABLE(pci, qtnf_pcie_devid_table); -static struct pci_driver qtnf_pcie_drv_data = { +static struct pci_driver qtnf_pcie_pearl_drv_data = { .name = DRV_NAME, .id_table = qtnf_pcie_devid_table, - .probe = qtnf_pcie_probe, - .remove = qtnf_pcie_remove, + .probe = qtnf_pcie_pearl_probe, + .remove = qtnf_pcie_pearl_remove, #ifdef CONFIG_PM_SLEEP .driver = { - .pm = &qtnf_pcie_pm_ops, + .pm = &qtnf_pcie_pearl_pm_ops, }, #endif }; -static int __init qtnf_pcie_register(void) +static int __init qtnf_pcie_pearl_register(void) { pr_info("register Quantenna QSR10g FullMAC PCIE driver\n"); - return pci_register_driver(&qtnf_pcie_drv_data); + return pci_register_driver(&qtnf_pcie_pearl_drv_data); } -static void __exit qtnf_pcie_exit(void) +static void __exit qtnf_pcie_pearl_exit(void) { pr_info("unregister Quantenna QSR10g FullMAC PCIE driver\n"); - pci_unregister_driver(&qtnf_pcie_drv_data); + pci_unregister_driver(&qtnf_pcie_pearl_drv_data); } -module_init(qtnf_pcie_register); -module_exit(qtnf_pcie_exit); +module_init(qtnf_pcie_pearl_register); +module_exit(qtnf_pcie_pearl_exit); MODULE_AUTHOR("Quantenna Communications"); MODULE_DESCRIPTION("Quantenna QSR10g PCIe bus driver for 802.11 wireless LAN."); From patchwork Mon Sep 24 22:15:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612921 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1687112B for ; Mon, 24 Sep 2018 22:15:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D659A297EF for ; Mon, 24 Sep 2018 22:15:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CAEDD2988A; Mon, 24 Sep 2018 22:15:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71844297EF for ; Mon, 24 Sep 2018 22:15:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728752AbeIYET4 (ORCPT ); Tue, 25 Sep 2018 00:19:56 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46860 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728720AbeIYETx (ORCPT ); Tue, 25 Sep 2018 00:19:53 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOI012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 08/11] qtnfmac: add missing header includes to bus.h Date: Mon, 24 Sep 2018 15:15:11 -0700 Message-Id: <20180924221514.4273-9-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A few include directives were missing in bus.h resulting in dependency of include order in other modules. Add missing includes. Signed-off-by: Igor Mitsyanko --- drivers/net/wireless/quantenna/qtnfmac/bus.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/wireless/quantenna/qtnfmac/bus.h b/drivers/net/wireless/quantenna/qtnfmac/bus.h index 2beca5b..7c4f856 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/bus.h +++ b/drivers/net/wireless/quantenna/qtnfmac/bus.h @@ -20,6 +20,9 @@ #include #include +#include "trans.h" +#include "core.h" + #define QTNF_MAX_MAC 3 enum qtnf_fw_state { From patchwork Mon Sep 24 22:15:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612943 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95096112B for ; Mon, 24 Sep 2018 22:16:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 88020297EF for ; Mon, 24 Sep 2018 22:16:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7C29E2988A; Mon, 24 Sep 2018 22:16:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D4BED297EF for ; Mon, 24 Sep 2018 22:16:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727650AbeIYEUe (ORCPT ); Tue, 25 Sep 2018 00:20:34 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46854 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728636AbeIYETr (ORCPT ); Tue, 25 Sep 2018 00:19:47 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOJ012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 09/11] qtnfmac_pcie: extract platform-independent PCIe code Date: Mon, 24 Sep 2018 15:15:12 -0700 Message-Id: <20180924221514.4273-10-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Extract platform-independent PCIe driver code into a separate file, and use it from platform-specific modules. Signed-off-by: Igor Mitsyanko --- drivers/net/wireless/quantenna/qtnfmac/Makefile | 1 + drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c | 393 +++++++++++++++++++ .../wireless/quantenna/qtnfmac/pcie/pcie_priv.h | 15 + .../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 425 +++------------------ .../quantenna/qtnfmac/pcie/pearl_pcie_ipc.h | 4 - 5 files changed, 455 insertions(+), 383 deletions(-) create mode 100644 drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c diff --git a/drivers/net/wireless/quantenna/qtnfmac/Makefile b/drivers/net/wireless/quantenna/qtnfmac/Makefile index 9eeddea..17cd7ad 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/Makefile +++ b/drivers/net/wireless/quantenna/qtnfmac/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_QTNFMAC_PEARL_PCIE) += qtnfmac_pearl_pcie.o qtnfmac_pearl_pcie-objs += \ shm_ipc.o \ + pcie/pcie.o \ pcie/pearl_pcie.o qtnfmac_pearl_pcie-$(CONFIG_DEBUG_FS) += debug.o diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c new file mode 100644 index 0000000..f83951c --- /dev/null +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie_priv.h" +#include "bus.h" +#include "shm_ipc.h" +#include "core.h" +#include "debug.h" + +#undef pr_fmt +#define pr_fmt(fmt) "qtnf_pcie: %s: " fmt, __func__ + +#define QTN_SYSCTL_BAR 0 +#define QTN_SHMEM_BAR 2 +#define QTN_DMA_BAR 3 + +int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb) +{ + struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + int ret; + + ret = qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len); + + if (ret == -ETIMEDOUT) { + pr_err("EP firmware is dead\n"); + bus->fw_state = QTNF_FW_STATE_EP_DEAD; + } + + return ret; +} + +int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv) +{ + struct sk_buff **vaddr; + int len; + + len = priv->tx_bd_num * sizeof(*priv->tx_skb) + + priv->rx_bd_num * sizeof(*priv->rx_skb); + vaddr = devm_kzalloc(&priv->pdev->dev, len, GFP_KERNEL); + + if (!vaddr) + return -ENOMEM; + + priv->tx_skb = vaddr; + + vaddr += priv->tx_bd_num; + priv->rx_skb = vaddr; + + return 0; +} + +void qtnf_pcie_bringup_fw_async(struct qtnf_bus *bus) +{ + struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + struct pci_dev *pdev = priv->pdev; + + get_device(&pdev->dev); + schedule_work(&bus->fw_work); +} + +static int qtnf_dbg_mps_show(struct seq_file *s, void *data) +{ + struct qtnf_bus *bus = dev_get_drvdata(s->private); + struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + + seq_printf(s, "%d\n", priv->mps); + + return 0; +} + +static int qtnf_dbg_msi_show(struct seq_file *s, void *data) +{ + struct qtnf_bus *bus = dev_get_drvdata(s->private); + struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + + seq_printf(s, "%u\n", priv->msi_enabled); + + return 0; +} + +static int qtnf_dbg_shm_stats(struct seq_file *s, void *data) +{ + struct qtnf_bus *bus = dev_get_drvdata(s->private); + struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + + seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n", + priv->shm_ipc_ep_in.tx_packet_count); + seq_printf(s, "shm_ipc_ep_in.rx_packet_count(%zu)\n", + priv->shm_ipc_ep_in.rx_packet_count); + seq_printf(s, "shm_ipc_ep_out.tx_packet_count(%zu)\n", + priv->shm_ipc_ep_out.tx_timeout_count); + seq_printf(s, "shm_ipc_ep_out.rx_packet_count(%zu)\n", + priv->shm_ipc_ep_out.rx_packet_count); + + return 0; +} + +void qtnf_pcie_fw_boot_done(struct qtnf_bus *bus, bool boot_success, + const char *drv_name) +{ + struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); + struct pci_dev *pdev = priv->pdev; + int ret; + + if (boot_success) { + bus->fw_state = QTNF_FW_STATE_FW_DNLD_DONE; + + ret = qtnf_core_attach(bus); + if (ret) { + pr_err("failed to attach core\n"); + boot_success = false; + } + } + + if (boot_success) { + qtnf_debugfs_init(bus, drv_name); + qtnf_debugfs_add_entry(bus, "mps", qtnf_dbg_mps_show); + qtnf_debugfs_add_entry(bus, "msi_enabled", qtnf_dbg_msi_show); + qtnf_debugfs_add_entry(bus, "shm_stats", qtnf_dbg_shm_stats); + } else { + bus->fw_state = QTNF_FW_STATE_DETACHED; + } + + complete(&bus->firmware_init_complete); + put_device(&pdev->dev); +} + +static void qtnf_tune_pcie_mps(struct qtnf_pcie_bus_priv *priv) +{ + struct pci_dev *pdev = priv->pdev; + struct pci_dev *parent; + int mps_p, mps_o, mps_m, mps; + int ret; + + /* current mps */ + mps_o = pcie_get_mps(pdev); + + /* maximum supported mps */ + mps_m = 128 << pdev->pcie_mpss; + + /* suggested new mps value */ + mps = mps_m; + + if (pdev->bus && pdev->bus->self) { + /* parent (bus) mps */ + parent = pdev->bus->self; + + if (pci_is_pcie(parent)) { + mps_p = pcie_get_mps(parent); + mps = min(mps_m, mps_p); + } + } + + ret = pcie_set_mps(pdev, mps); + if (ret) { + pr_err("failed to set mps to %d, keep using current %d\n", + mps, mps_o); + priv->mps = mps_o; + return; + } + + pr_debug("set mps to %d (was %d, max %d)\n", mps, mps_o, mps_m); + priv->mps = mps; +} + +static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv, bool use_msi) +{ + struct pci_dev *pdev = priv->pdev; + + /* fall back to legacy INTx interrupts by default */ + priv->msi_enabled = 0; + + /* check if MSI capability is available */ + if (use_msi) { + if (!pci_enable_msi(pdev)) { + pr_debug("enabled MSI interrupt\n"); + priv->msi_enabled = 1; + } else { + pr_warn("failed to enable MSI interrupts"); + } + } + + if (!priv->msi_enabled) { + pr_warn("legacy PCIE interrupts enabled\n"); + pci_intx(pdev, 1); + } +} + +static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 index) +{ + void __iomem *vaddr; + dma_addr_t busaddr; + size_t len; + int ret; + + ret = pcim_iomap_regions(priv->pdev, 1 << index, "qtnfmac_pcie"); + if (ret) + return IOMEM_ERR_PTR(ret); + + busaddr = pci_resource_start(priv->pdev, index); + len = pci_resource_len(priv->pdev, index); + vaddr = pcim_iomap_table(priv->pdev)[index]; + if (!vaddr) + return IOMEM_ERR_PTR(-ENOMEM); + + pr_debug("BAR%u vaddr=0x%p busaddr=%pad len=%u\n", + index, vaddr, &busaddr, (int)len); + + return vaddr; +} + +static int qtnf_pcie_init_memory(struct qtnf_pcie_bus_priv *priv) +{ + int ret = -ENOMEM; + + priv->sysctl_bar = qtnf_map_bar(priv, QTN_SYSCTL_BAR); + if (IS_ERR(priv->sysctl_bar)) { + pr_err("failed to map BAR%u\n", QTN_SYSCTL_BAR); + return ret; + } + + priv->dmareg_bar = qtnf_map_bar(priv, QTN_DMA_BAR); + if (IS_ERR(priv->dmareg_bar)) { + pr_err("failed to map BAR%u\n", QTN_DMA_BAR); + return ret; + } + + priv->epmem_bar = qtnf_map_bar(priv, QTN_SHMEM_BAR); + if (IS_ERR(priv->epmem_bar)) { + pr_err("failed to map BAR%u\n", QTN_SHMEM_BAR); + return ret; + } + + return 0; +} + +static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t len) +{ + struct qtnf_pcie_bus_priv *priv = arg; + struct qtnf_bus *bus = pci_get_drvdata(priv->pdev); + struct sk_buff *skb; + + if (unlikely(len == 0)) { + pr_warn("zero length packet received\n"); + return; + } + + skb = __dev_alloc_skb(len, GFP_KERNEL); + + if (unlikely(!skb)) { + pr_err("failed to allocate skb\n"); + return; + } + + skb_put_data(skb, buf, len); + + qtnf_trans_handle_rx_ctl_packet(bus, skb); +} + +void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv, + struct qtnf_shm_ipc_region __iomem *ipc_tx_reg, + struct qtnf_shm_ipc_region __iomem *ipc_rx_reg, + const struct qtnf_shm_ipc_int *ipc_int) +{ + const struct qtnf_shm_ipc_rx_callback rx_callback = { + qtnf_pcie_control_rx_callback, priv }; + + qtnf_shm_ipc_init(&priv->shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND, + ipc_tx_reg, priv->workqueue, + ipc_int, &rx_callback); + qtnf_shm_ipc_init(&priv->shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND, + ipc_rx_reg, priv->workqueue, + ipc_int, &rx_callback); +} + +int qtnf_pcie_probe(struct pci_dev *pdev, size_t priv_size, + const struct qtnf_bus_ops *bus_ops, u64 dma_mask, + bool use_msi) +{ + struct qtnf_pcie_bus_priv *pcie_priv; + struct qtnf_bus *bus; + int ret; + + bus = devm_kzalloc(&pdev->dev, + sizeof(*bus) + priv_size, GFP_KERNEL); + if (!bus) + return -ENOMEM; + + pcie_priv = get_bus_priv(bus); + + pci_set_drvdata(pdev, bus); + bus->bus_ops = bus_ops; + bus->dev = &pdev->dev; + bus->fw_state = QTNF_FW_STATE_RESET; + pcie_priv->pdev = pdev; + pcie_priv->tx_stopped = 0; + + init_completion(&bus->firmware_init_complete); + mutex_init(&bus->bus_lock); + spin_lock_init(&pcie_priv->tx_lock); + spin_lock_init(&pcie_priv->tx_reclaim_lock); + + pcie_priv->tx_full_count = 0; + pcie_priv->tx_done_count = 0; + pcie_priv->pcie_irq_count = 0; + pcie_priv->tx_reclaim_done = 0; + pcie_priv->tx_reclaim_req = 0; + + pcie_priv->workqueue = create_singlethread_workqueue("QTNF_PCIE"); + if (!pcie_priv->workqueue) { + pr_err("failed to alloc bus workqueue\n"); + ret = -ENODEV; + goto err_init; + } + + init_dummy_netdev(&bus->mux_dev); + + if (!pci_is_pcie(pdev)) { + pr_err("device %s is not PCI Express\n", pci_name(pdev)); + ret = -EIO; + goto err_base; + } + + qtnf_tune_pcie_mps(pcie_priv); + + ret = pcim_enable_device(pdev); + if (ret) { + pr_err("failed to init PCI device %x\n", pdev->device); + goto err_base; + } else { + pr_debug("successful init of PCI device %x\n", pdev->device); + } + + ret = dma_set_mask_and_coherent(&pdev->dev, dma_mask); + if (ret) { + pr_err("PCIE DMA coherent mask init failed\n"); + goto err_base; + } + + pci_set_master(pdev); + qtnf_pcie_init_irq(pcie_priv, use_msi); + + ret = qtnf_pcie_init_memory(pcie_priv); + if (ret < 0) { + pr_err("PCIE memory init failed\n"); + goto err_base; + } + + pci_save_state(pdev); + + return 0; + +err_base: + flush_workqueue(pcie_priv->workqueue); + destroy_workqueue(pcie_priv->workqueue); +err_init: + pci_set_drvdata(pdev, NULL); + + return ret; +} + +static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv) +{ + qtnf_shm_ipc_free(&priv->shm_ipc_ep_in); + qtnf_shm_ipc_free(&priv->shm_ipc_ep_out); +} + +void qtnf_pcie_remove(struct qtnf_bus *bus, struct qtnf_pcie_bus_priv *priv) +{ + wait_for_completion(&bus->firmware_init_complete); + + if (bus->fw_state == QTNF_FW_STATE_ACTIVE || + bus->fw_state == QTNF_FW_STATE_EP_DEAD) + qtnf_core_detach(bus); + + netif_napi_del(&bus->mux_napi); + flush_workqueue(priv->workqueue); + destroy_workqueue(priv->workqueue); + tasklet_kill(&priv->reclaim_tq); + + qtnf_pcie_free_shm_ipc(priv); + qtnf_debugfs_remove(bus); + pci_set_drvdata(priv->pdev, NULL); +} diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h index 8da9612..5c70fb4 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h @@ -12,6 +12,7 @@ #include #include "shm_ipc.h" +#include "bus.h" #define SKB_BUF_SIZE 2048 @@ -59,6 +60,20 @@ struct qtnf_pcie_bus_priv { u8 tx_stopped; }; +int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb); +int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv); +void qtnf_pcie_bringup_fw_async(struct qtnf_bus *bus); +void qtnf_pcie_fw_boot_done(struct qtnf_bus *bus, bool boot_success, + const char *drv_name); +void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv, + struct qtnf_shm_ipc_region __iomem *ipc_tx_reg, + struct qtnf_shm_ipc_region __iomem *ipc_rx_reg, + const struct qtnf_shm_ipc_int *ipc_int); +int qtnf_pcie_probe(struct pci_dev *pdev, size_t priv_size, + const struct qtnf_bus_ops *bus_ops, u64 dma_mask, + bool use_msi); +void qtnf_pcie_remove(struct qtnf_bus *bus, struct qtnf_pcie_bus_priv *priv); + static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg) { writel(val, basereg); diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c index fd11dd2..6d72a9d 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c @@ -193,29 +193,6 @@ static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_pearl_state *ps) spin_unlock_irqrestore(&ps->irq_lock, flags); } -static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv) -{ - struct pci_dev *pdev = priv->pdev; - - /* fall back to legacy INTx interrupts by default */ - priv->msi_enabled = 0; - - /* check if MSI capability is available */ - if (use_msi) { - if (!pci_enable_msi(pdev)) { - pr_debug("MSI interrupt enabled\n"); - priv->msi_enabled = 1; - } else { - pr_warn("failed to enable MSI interrupts"); - } - } - - if (!priv->msi_enabled) { - pr_warn("legacy PCIE interrupts enabled\n"); - pci_intx(pdev, 1); - } -} - static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *ps) { void __iomem *reg = ps->base.sysctl_bar + PEARL_PCIE_CFG0_OFFSET; @@ -247,148 +224,6 @@ static void qtnf_pcie_pearl_ipc_gen_ep_int(void *arg) qtnf_non_posted_write(data, reg); } -static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 index) -{ - void __iomem *vaddr; - dma_addr_t busaddr; - size_t len; - int ret; - - ret = pcim_iomap_regions(priv->pdev, 1 << index, DRV_NAME); - if (ret) - return IOMEM_ERR_PTR(ret); - - busaddr = pci_resource_start(priv->pdev, index); - len = pci_resource_len(priv->pdev, index); - vaddr = pcim_iomap_table(priv->pdev)[index]; - if (!vaddr) - return IOMEM_ERR_PTR(-ENOMEM); - - pr_debug("BAR%u vaddr=0x%p busaddr=%pad len=%u\n", - index, vaddr, &busaddr, (int)len); - - return vaddr; -} - -static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t len) -{ - struct qtnf_pcie_bus_priv *priv = arg; - struct qtnf_bus *bus = pci_get_drvdata(priv->pdev); - struct sk_buff *skb; - - if (unlikely(len == 0)) { - pr_warn("zero length packet received\n"); - return; - } - - skb = __dev_alloc_skb(len, GFP_KERNEL); - - if (unlikely(!skb)) { - pr_err("failed to allocate skb\n"); - return; - } - - skb_put_data(skb, buf, len); - - qtnf_trans_handle_rx_ctl_packet(bus, skb); -} - -static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pearl_state *ps) -{ - struct qtnf_shm_ipc_region __iomem *ipc_tx_reg; - struct qtnf_shm_ipc_region __iomem *ipc_rx_reg; - const struct qtnf_shm_ipc_int ipc_int = { - qtnf_pcie_pearl_ipc_gen_ep_int, ps }; - const struct qtnf_shm_ipc_rx_callback rx_callback = { - qtnf_pcie_control_rx_callback, ps }; - - ipc_tx_reg = &ps->bda->bda_shm_reg1; - ipc_rx_reg = &ps->bda->bda_shm_reg2; - - qtnf_shm_ipc_init(&ps->base.shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND, - ipc_tx_reg, ps->base.workqueue, - &ipc_int, &rx_callback); - qtnf_shm_ipc_init(&ps->base.shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND, - ipc_rx_reg, ps->base.workqueue, - &ipc_int, &rx_callback); - - return 0; -} - -static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv) -{ - qtnf_shm_ipc_free(&priv->shm_ipc_ep_in); - qtnf_shm_ipc_free(&priv->shm_ipc_ep_out); -} - -static int qtnf_pcie_init_memory(struct qtnf_pcie_pearl_state *ps) -{ - struct qtnf_pcie_bus_priv *priv = &ps->base; - int ret = -ENOMEM; - - priv->sysctl_bar = qtnf_map_bar(priv, QTN_SYSCTL_BAR); - if (IS_ERR(priv->sysctl_bar)) { - pr_err("failed to map BAR%u\n", QTN_SYSCTL_BAR); - return ret; - } - - priv->dmareg_bar = qtnf_map_bar(priv, QTN_DMA_BAR); - if (IS_ERR(priv->dmareg_bar)) { - pr_err("failed to map BAR%u\n", QTN_DMA_BAR); - return ret; - } - - priv->epmem_bar = qtnf_map_bar(priv, QTN_SHMEM_BAR); - if (IS_ERR(priv->epmem_bar)) { - pr_err("failed to map BAR%u\n", QTN_SHMEM_BAR); - return ret; - } - - ps->pcie_reg_base = priv->dmareg_bar; - ps->bda = priv->epmem_bar; - writel(priv->msi_enabled, &ps->bda->bda_rc_msi_enabled); - - return 0; -} - -static void qtnf_tune_pcie_mps(struct qtnf_pcie_bus_priv *priv) -{ - struct pci_dev *pdev = priv->pdev; - struct pci_dev *parent; - int mps_p, mps_o, mps_m, mps; - int ret; - - /* current mps */ - mps_o = pcie_get_mps(pdev); - - /* maximum supported mps */ - mps_m = 128 << pdev->pcie_mpss; - - /* suggested new mps value */ - mps = mps_m; - - if (pdev->bus && pdev->bus->self) { - /* parent (bus) mps */ - parent = pdev->bus->self; - - if (pci_is_pcie(parent)) { - mps_p = pcie_get_mps(parent); - mps = min(mps_m, mps_p); - } - } - - ret = pcie_set_mps(pdev, mps); - if (ret) { - pr_err("failed to set mps to %d, keep using current %d\n", - mps, mps_o); - priv->mps = mps_o; - return; - } - - pr_debug("set mps to %d (was %d, max %d)\n", mps, mps_o, mps_m); - priv->mps = mps; -} - static int qtnf_is_state(__le32 __iomem *reg, u32 state) { u32 s = readl(reg); @@ -423,26 +258,6 @@ static int qtnf_poll_state(__le32 __iomem *reg, u32 state, u32 delay_in_ms) return 0; } -static int alloc_skb_array(struct qtnf_pcie_bus_priv *priv) -{ - struct sk_buff **vaddr; - int len; - - len = priv->tx_bd_num * sizeof(*priv->tx_skb) + - priv->rx_bd_num * sizeof(*priv->rx_skb); - vaddr = devm_kzalloc(&priv->pdev->dev, len, GFP_KERNEL); - - if (!vaddr) - return -ENOMEM; - - priv->tx_skb = vaddr; - - vaddr += priv->tx_bd_num; - priv->rx_skb = vaddr; - - return 0; -} - static int pearl_alloc_bd_table(struct qtnf_pcie_pearl_state *ps) { struct qtnf_pcie_bus_priv *priv = &ps->base; @@ -656,7 +471,7 @@ static int qtnf_pcie_pearl_init_xfer(struct qtnf_pcie_pearl_state *ps) return ret; } - ret = alloc_skb_array(priv); + ret = qtnf_pcie_alloc_skb_array(priv); if (ret) { pr_err("failed to allocate skb array\n"); return ret; @@ -750,7 +565,7 @@ static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *ps) static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) { - struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus); struct qtnf_pcie_bus_priv *priv = &ps->base; dma_addr_t txbd_paddr, skb_paddr; struct qtnf_pearl_tx_bd *txbd; @@ -824,25 +639,10 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb) return NETDEV_TX_OK; } -static int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb) -{ - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); - int ret; - - ret = qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len); - - if (ret == -ETIMEDOUT) { - pr_err("EP firmware is dead\n"); - bus->fw_state = QTNF_FW_STATE_EP_DEAD; - } - - return ret; -} - static irqreturn_t qtnf_pcie_pearl_interrupt(int irq, void *data) { struct qtnf_bus *bus = (struct qtnf_bus *)data; - struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus); struct qtnf_pcie_bus_priv *priv = &ps->base; u32 status; @@ -902,7 +702,7 @@ static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *ps) static int qtnf_pcie_pearl_rx_poll(struct napi_struct *napi, int budget) { struct qtnf_bus *bus = container_of(napi, struct qtnf_bus, mux_napi); - struct qtnf_pcie_pearl_state *ps = (void *)get_bus_priv(bus); + struct qtnf_pcie_pearl_state *ps = get_bus_priv(bus); struct qtnf_pcie_bus_priv *priv = &ps->base; struct net_device *ndev = NULL; struct sk_buff *skb = NULL; @@ -1038,26 +838,6 @@ static const struct qtnf_bus_ops qtnf_pcie_pearl_bus_ops = { .data_rx_stop = qtnf_pcie_data_rx_stop, }; -static int qtnf_dbg_mps_show(struct seq_file *s, void *data) -{ - struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); - - seq_printf(s, "%d\n", priv->mps); - - return 0; -} - -static int qtnf_dbg_msi_show(struct seq_file *s, void *data) -{ - struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); - - seq_printf(s, "%u\n", priv->msi_enabled); - - return 0; -} - static int qtnf_dbg_irq_stats(struct seq_file *s, void *data) { struct qtnf_bus *bus = dev_get_drvdata(s->private); @@ -1114,27 +894,9 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data) return 0; } -static int qtnf_dbg_shm_stats(struct seq_file *s, void *data) -{ - struct qtnf_bus *bus = dev_get_drvdata(s->private); - struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus); - - seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n", - priv->shm_ipc_ep_in.tx_packet_count); - seq_printf(s, "shm_ipc_ep_in.rx_packet_count(%zu)\n", - priv->shm_ipc_ep_in.rx_packet_count); - seq_printf(s, "shm_ipc_ep_out.tx_packet_count(%zu)\n", - priv->shm_ipc_ep_out.tx_timeout_count); - seq_printf(s, "shm_ipc_ep_out.rx_packet_count(%zu)\n", - priv->shm_ipc_ep_out.rx_packet_count); - - return 0; -} - -static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *ps, uint32_t size, +static int qtnf_ep_fw_send(struct pci_dev *pdev, uint32_t size, int blk, const u8 *pblk, const u8 *fw) { - struct pci_dev *pdev = ps->base.pdev; struct qtnf_bus *bus = pci_get_drvdata(pdev); struct qtnf_pearl_fw_hdr *hdr; @@ -1197,7 +959,7 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, const u8 *fw, u32 fw_size) return -ETIMEDOUT; } - len = qtnf_ep_fw_send(ps, fw_size, blk, pblk, fw); + len = qtnf_ep_fw_send(ps->base.pdev, fw_size, blk, pblk, fw); if (len <= 0) continue; @@ -1255,6 +1017,7 @@ static void qtnf_pearl_fw_work_handler(struct work_struct *work) int ret; u32 state = QTN_RC_FW_LOADRDY | QTN_RC_FW_QLINK; const char *fwname = QTN_PCI_PEARL_FW_NAME; + bool fw_boot_success = false; if (flashboot) { state |= QTN_RC_FW_FLASHBOOT; @@ -1262,7 +1025,7 @@ static void qtnf_pearl_fw_work_handler(struct work_struct *work) ret = request_firmware(&fw, fwname, &pdev->dev); if (ret < 0) { pr_err("failed to get firmware %s\n", fwname); - goto fw_load_fail; + goto fw_load_exit; } } @@ -1275,13 +1038,14 @@ static void qtnf_pearl_fw_work_handler(struct work_struct *work) if (!flashboot) release_firmware(fw); - goto fw_load_fail; + goto fw_load_exit; } qtnf_clear_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY); if (flashboot) { pr_info("booting firmware from flash\n"); + } else { pr_info("starting firmware upload: %s\n", fwname); @@ -1289,56 +1053,33 @@ static void qtnf_pearl_fw_work_handler(struct work_struct *work) release_firmware(fw); if (ret) { pr_err("firmware upload error\n"); - goto fw_load_fail; + goto fw_load_exit; } } if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_DONE, QTN_FW_DL_TIMEOUT_MS)) { pr_err("firmware bringup timed out\n"); - goto fw_load_fail; + goto fw_load_exit; } - bus->fw_state = QTNF_FW_STATE_FW_DNLD_DONE; pr_info("firmware is up and running\n"); if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_QLINK_DONE, QTN_FW_QLINK_TIMEOUT_MS)) { pr_err("firmware runtime failure\n"); - goto fw_load_fail; - } - - ret = qtnf_core_attach(bus); - if (ret) { - pr_err("failed to attach core\n"); - goto fw_load_fail; + goto fw_load_exit; } - qtnf_debugfs_init(bus, DRV_NAME); - qtnf_debugfs_add_entry(bus, "mps", qtnf_dbg_mps_show); - qtnf_debugfs_add_entry(bus, "msi_enabled", qtnf_dbg_msi_show); - qtnf_debugfs_add_entry(bus, "hdp_stats", qtnf_dbg_hdp_stats); - qtnf_debugfs_add_entry(bus, "irq_stats", qtnf_dbg_irq_stats); - qtnf_debugfs_add_entry(bus, "shm_stats", qtnf_dbg_shm_stats); - - goto fw_load_exit; - -fw_load_fail: - bus->fw_state = QTNF_FW_STATE_DETACHED; + fw_boot_success = true; fw_load_exit: - complete(&bus->firmware_init_complete); - put_device(&pdev->dev); -} + qtnf_pcie_fw_boot_done(bus, fw_boot_success, DRV_NAME); -static void qtnf_bringup_fw_async(struct qtnf_bus *bus) -{ - struct qtnf_pcie_bus_priv *priv = (void *)get_bus_priv(bus); - struct pci_dev *pdev = priv->pdev; - - get_device(&pdev->dev); - INIT_WORK(&bus->fw_work, qtnf_pearl_fw_work_handler); - schedule_work(&bus->fw_work); + if (fw_boot_success) { + qtnf_debugfs_add_entry(bus, "hdp_stats", qtnf_dbg_hdp_stats); + qtnf_debugfs_add_entry(bus, "irq_stats", qtnf_dbg_irq_stats); + } } static void qtnf_pearl_reclaim_tasklet_fn(unsigned long data) @@ -1352,100 +1093,47 @@ static void qtnf_pearl_reclaim_tasklet_fn(unsigned long data) static int qtnf_pcie_pearl_probe(struct pci_dev *pdev, const struct pci_device_id *id) { + struct qtnf_shm_ipc_int ipc_int; struct qtnf_pcie_pearl_state *ps; struct qtnf_bus *bus; int ret; + u64 dma_mask; - bus = devm_kzalloc(&pdev->dev, - sizeof(*bus) + sizeof(*ps), GFP_KERNEL); - if (!bus) - return -ENOMEM; +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + dma_mask = DMA_BIT_MASK(64); +#else + dma_mask = DMA_BIT_MASK(32); +#endif - ps = get_bus_priv(bus); + ret = qtnf_pcie_probe(pdev, sizeof(*ps), &qtnf_pcie_pearl_bus_ops, + dma_mask, use_msi); + if (ret) + return ret; - pci_set_drvdata(pdev, bus); - bus->bus_ops = &qtnf_pcie_pearl_bus_ops; - bus->dev = &pdev->dev; - bus->fw_state = QTNF_FW_STATE_RESET; - ps->base.pdev = pdev; + bus = pci_get_drvdata(pdev); + ps = get_bus_priv(bus); - init_completion(&bus->firmware_init_complete); - mutex_init(&bus->bus_lock); - spin_lock_init(&ps->base.tx_lock); spin_lock_init(&ps->irq_lock); - spin_lock_init(&ps->base.tx_reclaim_lock); - - /* init stats */ - ps->base.tx_full_count = 0; - ps->base.tx_done_count = 0; - ps->base.pcie_irq_count = 0; - ps->pcie_irq_rx_count = 0; - ps->pcie_irq_tx_count = 0; - ps->pcie_irq_uf_count = 0; - ps->base.tx_reclaim_done = 0; - ps->base.tx_reclaim_req = 0; tasklet_init(&ps->base.reclaim_tq, qtnf_pearl_reclaim_tasklet_fn, (unsigned long)ps); - - init_dummy_netdev(&bus->mux_dev); netif_napi_add(&bus->mux_dev, &bus->mux_napi, qtnf_pcie_pearl_rx_poll, 10); + INIT_WORK(&bus->fw_work, qtnf_pearl_fw_work_handler); - ps->base.workqueue = create_singlethread_workqueue("QTNF_PEARL_PCIE"); - if (!ps->base.workqueue) { - pr_err("failed to alloc bus workqueue\n"); - ret = -ENODEV; - goto err_init; - } - - if (!pci_is_pcie(pdev)) { - pr_err("device %s is not PCI Express\n", pci_name(pdev)); - ret = -EIO; - goto err_base; - } - - qtnf_tune_pcie_mps(&ps->base); - - ret = pcim_enable_device(pdev); - if (ret) { - pr_err("failed to init PCI device %x\n", pdev->device); - goto err_base; - } else { - pr_debug("successful init of PCI device %x\n", pdev->device); - } - -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT - ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); -#else - ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); -#endif - if (ret) { - pr_err("PCIE DMA coherent mask init failed\n"); - goto err_base; - } - - pci_set_master(pdev); - qtnf_pcie_init_irq(&ps->base); - - ret = qtnf_pcie_init_memory(ps); - if (ret < 0) { - pr_err("PCIE memory init failed\n"); - goto err_base; - } - - pci_save_state(pdev); + ps->pcie_reg_base = ps->base.dmareg_bar; + ps->bda = ps->base.epmem_bar; + writel(ps->base.msi_enabled, &ps->bda->bda_rc_msi_enabled); - ret = qtnf_pcie_init_shm_ipc(ps); - if (ret < 0) { - pr_err("PCIE SHM IPC init failed\n"); - goto err_base; - } + ipc_int.fn = qtnf_pcie_pearl_ipc_gen_ep_int; + ipc_int.arg = ps; + qtnf_pcie_init_shm_ipc(&ps->base, &ps->bda->bda_shm_reg1, + &ps->bda->bda_shm_reg2, &ipc_int); ret = qtnf_pcie_pearl_init_xfer(ps); if (ret) { pr_err("PCIE xfer init failed\n"); - goto err_ipc; + goto error; } /* init default irq settings */ @@ -1462,24 +1150,14 @@ static int qtnf_pcie_pearl_probe(struct pci_dev *pdev, goto err_xfer; } - qtnf_bringup_fw_async(bus); + qtnf_pcie_bringup_fw_async(bus); return 0; err_xfer: qtnf_pearl_free_xfer_buffers(ps); - -err_ipc: - qtnf_pcie_free_shm_ipc(&ps->base); - -err_base: - flush_workqueue(ps->base.workqueue); - destroy_workqueue(ps->base.workqueue); - -err_init: - tasklet_kill(&ps->base.reclaim_tq); - netif_napi_del(&bus->mux_napi); - pci_set_drvdata(pdev, NULL); +error: + qtnf_pcie_remove(bus, &ps->base); return ret; } @@ -1493,22 +1171,11 @@ static void qtnf_pcie_pearl_remove(struct pci_dev *pdev) if (!bus) return; - wait_for_completion(&bus->firmware_init_complete); - - if (bus->fw_state == QTNF_FW_STATE_ACTIVE || - bus->fw_state == QTNF_FW_STATE_EP_DEAD) - qtnf_core_detach(bus); - ps = get_bus_priv(bus); - qtnf_pearl_reset_ep(ps); - netif_napi_del(&bus->mux_napi); - flush_workqueue(ps->base.workqueue); - destroy_workqueue(ps->base.workqueue); - tasklet_kill(&ps->base.reclaim_tq); + qtnf_pcie_remove(bus, &ps->base); + qtnf_pearl_reset_ep(ps); qtnf_pearl_free_xfer_buffers(ps); - qtnf_pcie_free_shm_ipc(&ps->base); - qtnf_debugfs_remove(bus); } #ifdef CONFIG_PM_SLEEP diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h index b87505d..f21e97e 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h @@ -63,10 +63,6 @@ #define QTN_HOST_ADDR(h, l) ((u32)l) #endif -#define QTN_SYSCTL_BAR 0 -#define QTN_SHMEM_BAR 2 -#define QTN_DMA_BAR 3 - #define QTN_PCIE_BDA_VERSION 0x1002 #define PCIE_BDA_NAMELEN 32 From patchwork Mon Sep 24 22:15:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612927 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 42F7C161F for ; Mon, 24 Sep 2018 22:15:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3769F297EF for ; Mon, 24 Sep 2018 22:15:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2BFD12988A; Mon, 24 Sep 2018 22:15:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CE704297EF for ; Mon, 24 Sep 2018 22:15:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728683AbeIYETt (ORCPT ); Tue, 25 Sep 2018 00:19:49 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46858 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728653AbeIYETr (ORCPT ); Tue, 25 Sep 2018 00:19:47 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOK012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 10/11] qtnfmac: wait for FW load work to finish at PCIe remove Date: Mon, 24 Sep 2018 15:15:13 -0700 Message-Id: <20180924221514.4273-11-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Waiting for "completion" to be set in FW load thread can not be used in case PCIe remove is called before FW load work was scheduled. Just wait for work completion instead to avoid problems. Signed-off-by: Igor Mitsyanko --- drivers/net/wireless/quantenna/qtnfmac/bus.h | 1 - drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c | 4 +--- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/wireless/quantenna/qtnfmac/bus.h b/drivers/net/wireless/quantenna/qtnfmac/bus.h index 7c4f856..528ca7f 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/bus.h +++ b/drivers/net/wireless/quantenna/qtnfmac/bus.h @@ -62,7 +62,6 @@ struct qtnf_bus { struct qtnf_hw_info hw_info; struct napi_struct mux_napi; struct net_device mux_dev; - struct completion firmware_init_complete; struct workqueue_struct *workqueue; struct work_struct fw_work; struct work_struct event_work; diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c index f83951c..d1637f2 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c @@ -130,7 +130,6 @@ void qtnf_pcie_fw_boot_done(struct qtnf_bus *bus, bool boot_success, bus->fw_state = QTNF_FW_STATE_DETACHED; } - complete(&bus->firmware_init_complete); put_device(&pdev->dev); } @@ -304,7 +303,6 @@ int qtnf_pcie_probe(struct pci_dev *pdev, size_t priv_size, pcie_priv->pdev = pdev; pcie_priv->tx_stopped = 0; - init_completion(&bus->firmware_init_complete); mutex_init(&bus->bus_lock); spin_lock_init(&pcie_priv->tx_lock); spin_lock_init(&pcie_priv->tx_reclaim_lock); @@ -376,7 +374,7 @@ static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv) void qtnf_pcie_remove(struct qtnf_bus *bus, struct qtnf_pcie_bus_priv *priv) { - wait_for_completion(&bus->firmware_init_complete); + cancel_work_sync(&bus->fw_work); if (bus->fw_state == QTNF_FW_STATE_ACTIVE || bus->fw_state == QTNF_FW_STATE_EP_DEAD) From patchwork Mon Sep 24 22:15:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mitsyanko X-Patchwork-Id: 10612913 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D7AA3161F for ; Mon, 24 Sep 2018 22:15:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CAF9C297EF for ; Mon, 24 Sep 2018 22:15:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BF38829858; Mon, 24 Sep 2018 22:15:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 58F27297EF for ; Mon, 24 Sep 2018 22:15:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728674AbeIYETs (ORCPT ); Tue, 25 Sep 2018 00:19:48 -0400 Received: from [12.131.200.82] ([12.131.200.82]:46855 "EHLO fm-smtp01.quantenna.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728642AbeIYETr (ORCPT ); Tue, 25 Sep 2018 00:19:47 -0400 Received: from dodo-dell.quantenna.com ([10.10.23.208]) by fm-smtp01.quantenna.com (8.14.4/8.14.4) with ESMTP id w8OMFNOL012852; Mon, 24 Sep 2018 15:15:23 -0700 From: Igor Mitsyanko To: linux-wireless@vger.kernel.org Cc: sergey.matyukevich.os@quantenna.com, ashevchenko@quantenna.com, Igor Mitsyanko Subject: [PATCH V2 11/11] qtnfmac_pcie: check for correct CHIP ID at pcie probe Date: Mon, 24 Sep 2018 15:15:14 -0700 Message-Id: <20180924221514.4273-12-igor.mitsyanko.os@quantenna.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> References: <20180924221514.4273-1-igor.mitsyanko.os@quantenna.com> Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Make sure that wifi device is of supported variant by checking it's CHIP ID before completing a probe sequence. Signed-off-by: Igor Mitsyanko --- .../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 24 ++++++++++++++++++++++ .../net/wireless/quantenna/qtnfmac/qtn_hw_ids.h | 14 +++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c index 6d72a9d..5aca12a 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c +++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c @@ -1090,6 +1090,26 @@ static void qtnf_pearl_reclaim_tasklet_fn(unsigned long data) qtnf_en_txdone_irq(ps); } +static int qtnf_pearl_check_chip_id(struct qtnf_pcie_pearl_state *ps) +{ + unsigned int chipid; + + chipid = qtnf_chip_id_get(ps->base.sysctl_bar); + + switch (chipid) { + case QTN_CHIP_ID_PEARL: + case QTN_CHIP_ID_PEARL_B: + case QTN_CHIP_ID_PEARL_C: + pr_info("chip ID is 0x%x\n", chipid); + break; + default: + pr_err("incorrect chip ID 0x%x\n", chipid); + return -ENODEV; + } + + return 0; +} + static int qtnf_pcie_pearl_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -1130,6 +1150,10 @@ static int qtnf_pcie_pearl_probe(struct pci_dev *pdev, qtnf_pcie_init_shm_ipc(&ps->base, &ps->bda->bda_shm_reg1, &ps->bda->bda_shm_reg2, &ipc_int); + ret = qtnf_pearl_check_chip_id(ps); + if (ret) + goto error; + ret = qtnf_pcie_pearl_init_xfer(ps); if (ret) { pr_err("PCIE xfer init failed\n"); diff --git a/drivers/net/wireless/quantenna/qtnfmac/qtn_hw_ids.h b/drivers/net/wireless/quantenna/qtnfmac/qtn_hw_ids.h index c4ad40d..1fe798a 100644 --- a/drivers/net/wireless/quantenna/qtnfmac/qtn_hw_ids.h +++ b/drivers/net/wireless/quantenna/qtnfmac/qtn_hw_ids.h @@ -25,8 +25,22 @@ #define PCIE_DEVICE_ID_QTN_PEARL (0x0008) +#define QTN_REG_SYS_CTRL_CSR 0x14 +#define QTN_CHIP_ID_MASK 0xF0 +#define QTN_CHIP_ID_TOPAZ 0x40 +#define QTN_CHIP_ID_PEARL 0x50 +#define QTN_CHIP_ID_PEARL_B 0x60 +#define QTN_CHIP_ID_PEARL_C 0x70 + /* FW names */ #define QTN_PCI_PEARL_FW_NAME "qtn/fmac_qsr10g.img" +static inline unsigned int qtnf_chip_id_get(const void __iomem *regs_base) +{ + u32 board_rev = readl(regs_base + QTN_REG_SYS_CTRL_CSR); + + return board_rev & QTN_CHIP_ID_MASK; +} + #endif /* _QTN_HW_IDS_H_ */