From patchwork Thu Jan 9 03:28:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 11325055 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A6F81395 for ; Thu, 9 Jan 2020 03:29:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 030B720720 for ; Thu, 9 Jan 2020 03:29:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727549AbgAID27 (ORCPT ); Wed, 8 Jan 2020 22:28:59 -0500 Received: from mail.kernel.org ([198.145.29.99]:47968 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726913AbgAID27 (ORCPT ); Wed, 8 Jan 2020 22:28:59 -0500 Received: from localhost (98.142.130.235.16clouds.com [98.142.130.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id CD0F620705; Thu, 9 Jan 2020 03:28:58 +0000 (UTC) From: Shawn Guo To: Lorenzo Pieralisi , Bjorn Helgaas Cc: Jun Nie , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH v2 1/2] PCI: histb: Use gpio_desc for PCIe GPIO reset Date: Thu, 9 Jan 2020 11:28:50 +0800 Message-Id: <20200109032851.13377-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200109032851.13377-1-shawn.guo@linaro.org> References: <20200109032851.13377-1-shawn.guo@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It switches GPIO reset code to use gpio_desc, so that the code becomes simpler and cleaner. Signed-off-by: Shawn Guo --- drivers/pci/controller/dwc/pcie-histb.c | 29 +++++++++---------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c index 811b5c6d62ea..112254619ed0 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -60,7 +60,7 @@ struct histb_pcie { struct reset_control *sys_reset; struct reset_control *bus_reset; void __iomem *ctrl; - int reset_gpio; + struct gpio_desc *reset_gpio; struct regulator *vpcie; }; @@ -219,8 +219,8 @@ static void histb_pcie_host_disable(struct histb_pcie *hipcie) clk_disable_unprepare(hipcie->sys_clk); clk_disable_unprepare(hipcie->bus_clk); - if (gpio_is_valid(hipcie->reset_gpio)) - gpio_set_value_cansleep(hipcie->reset_gpio, 0); + if (hipcie->reset_gpio) + gpiod_set_value_cansleep(hipcie->reset_gpio, 0); if (hipcie->vpcie) regulator_disable(hipcie->vpcie); @@ -242,8 +242,8 @@ static int histb_pcie_host_enable(struct pcie_port *pp) } } - if (gpio_is_valid(hipcie->reset_gpio)) - gpio_set_value_cansleep(hipcie->reset_gpio, 1); + if (hipcie->reset_gpio) + gpiod_set_value_cansleep(hipcie->reset_gpio, 1); ret = clk_prepare_enable(hipcie->bus_clk); if (ret) { @@ -305,10 +305,7 @@ static int histb_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct pcie_port *pp; struct resource *res; - struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; - enum of_gpio_flags of_flags; - unsigned long flag = GPIOF_DIR_OUT; int ret; hipcie = devm_kzalloc(dev, sizeof(*hipcie), GFP_KERNEL); @@ -345,17 +342,11 @@ static int histb_pcie_probe(struct platform_device *pdev) hipcie->vpcie = NULL; } - hipcie->reset_gpio = of_get_named_gpio_flags(np, - "reset-gpios", 0, &of_flags); - if (of_flags & OF_GPIO_ACTIVE_LOW) - flag |= GPIOF_ACTIVE_LOW; - if (gpio_is_valid(hipcie->reset_gpio)) { - ret = devm_gpio_request_one(dev, hipcie->reset_gpio, - flag, "PCIe device power control"); - if (ret) { - dev_err(dev, "unable to request gpio\n"); - return ret; - } + hipcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(hipcie->reset_gpio)) { + ret = PTR_ERR(hipcie->reset_gpio); + return ret; } hipcie->aux_clk = devm_clk_get(dev, "aux"); From patchwork Thu Jan 9 03:28:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 11325059 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6F9201395 for ; Thu, 9 Jan 2020 03:29:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4F51320720 for ; Thu, 9 Jan 2020 03:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727591AbgAID3D (ORCPT ); Wed, 8 Jan 2020 22:29:03 -0500 Received: from mail.kernel.org ([198.145.29.99]:48166 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726913AbgAID3D (ORCPT ); Wed, 8 Jan 2020 22:29:03 -0500 Received: from localhost (98.142.130.235.16clouds.com [98.142.130.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id CDF77206F0; Thu, 9 Jan 2020 03:29:02 +0000 (UTC) From: Shawn Guo To: Lorenzo Pieralisi , Bjorn Helgaas Cc: Jun Nie , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH v2 2/2] PCI: histb: Correct PCIe reset operation Date: Thu, 9 Jan 2020 11:28:51 +0800 Message-Id: <20200109032851.13377-3-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200109032851.13377-1-shawn.guo@linaro.org> References: <20200109032851.13377-1-shawn.guo@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCIe reset via GPIO in the driver never worked as expected. Per "Power Sequencing and Reset Signal Timings" table in PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, the PERST# should be deasserted after minimum of 100us once REFCLK is stable. The assertion has been done when the GPIO is being requested, and deassertion should be done in host enabling rather than disabling. Also a bit wait is added to ensure device get ready after reset. Signed-off-by: Shawn Guo --- drivers/pci/controller/dwc/pcie-histb.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c index 112254619ed0..67c27a8036c7 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -219,9 +219,6 @@ static void histb_pcie_host_disable(struct histb_pcie *hipcie) clk_disable_unprepare(hipcie->sys_clk); clk_disable_unprepare(hipcie->bus_clk); - if (hipcie->reset_gpio) - gpiod_set_value_cansleep(hipcie->reset_gpio, 0); - if (hipcie->vpcie) regulator_disable(hipcie->vpcie); } @@ -242,9 +239,6 @@ static int histb_pcie_host_enable(struct pcie_port *pp) } } - if (hipcie->reset_gpio) - gpiod_set_value_cansleep(hipcie->reset_gpio, 1); - ret = clk_prepare_enable(hipcie->bus_clk); if (ret) { dev_err(dev, "cannot prepare/enable bus clk\n"); @@ -278,6 +272,20 @@ static int histb_pcie_host_enable(struct pcie_port *pp) reset_control_assert(hipcie->bus_reset); reset_control_deassert(hipcie->bus_reset); + if (hipcie->reset_gpio) { + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, indicates + * PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. + */ + usleep_range(100, 200); + gpiod_set_value_cansleep(hipcie->reset_gpio, 0); + + /* wait 1ms for device to be ready */ + usleep_range(1000, 2000); + } + return 0; err_aux_clk: