From patchwork Fri Jan 10 14:53:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327513 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33BCC6C1 for ; Fri, 10 Jan 2020 14:54:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 044442082E for ; Fri, 10 Jan 2020 14:54:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="SvFGWpfp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728209AbgAJOy3 (ORCPT ); Fri, 10 Jan 2020 09:54:29 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:60680 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728137AbgAJOy3 (ORCPT ); Fri, 10 Jan 2020 09:54:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578668068; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=g1Y7SAIkQ6YKL70iv+PevVOHVnPkk+5bW/+E3fVVoME=; b=SvFGWpfp3DVBDZfD4bM3aH/YFOrFPI6GT1BxVzDUMtp4MqSc96m5XvVWmenZhHsON659sC XLvKJzI05Cddvh2ajlWClozArJZTumC1AQn4DLAdK7K6vgY2hfSMdrYPPNZF/TxMpna2F3 3OB5xvJCGAlk7iC662MCE8jhFXqe5Eo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-364-H6w6yrkENFmG85vKwnY_Qg-1; Fri, 10 Jan 2020 09:54:27 -0500 X-MC-Unique: H6w6yrkENFmG85vKwnY_Qg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7B37618B9FEF; Fri, 10 Jan 2020 14:54:25 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id B178A7BA5F; Fri, 10 Jan 2020 14:54:20 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 01/16] libcflat: Add other size defines Date: Fri, 10 Jan 2020 15:53:57 +0100 Message-Id: <20200110145412.14937-2-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce additional SZ_256, SZ_8K, SZ_16K macros that will be used by ITS tests. Signed-off-by: Eric Auger Reviewed-by: Thomas Huth --- lib/libcflat.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/libcflat.h b/lib/libcflat.h index ea19f61..7092af2 100644 --- a/lib/libcflat.h +++ b/lib/libcflat.h @@ -36,7 +36,10 @@ #define ALIGN(x, a) __ALIGN((x), (a)) #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) +#define SZ_256 (1 << 8) #define SZ_4K (1 << 12) +#define SZ_8K (1 << 13) +#define SZ_16K (1 << 14) #define SZ_64K (1 << 16) #define SZ_2M (1 << 21) #define SZ_1G (1 << 30) From patchwork Fri Jan 10 14:53:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327531 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A324A921 for ; Fri, 10 Jan 2020 14:54:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 80D8D20882 for ; Fri, 10 Jan 2020 14:54:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="TWwPaLqN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728351AbgAJOyk (ORCPT ); Fri, 10 Jan 2020 09:54:40 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:25269 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728309AbgAJOyj (ORCPT ); Fri, 10 Jan 2020 09:54:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578668077; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hksWhfx/qjqLBl2kwSG6HIa1DnV2Yh8CnWY4dayzAHc=; b=TWwPaLqNjuisTNHbR4U+BXIxgzDnwYdd94Z3tY8iFkJZL8ACl5RLakr91MVo9f6F5ofi3V xXVmTPtLfmq4D+6epSFQOtxIF/zoQlxzoqxH3rYzIfDMh9qi41OqvQCq/SYmuPbpgexSl6 uPMoxWX2pl9TbEsdT2/z6VPN1umEDwI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-22-sLHCnH1HO6O3PHQlEJkQ_A-1; Fri, 10 Jan 2020 09:54:33 -0500 X-MC-Unique: sLHCnH1HO6O3PHQlEJkQ_A-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 328261AEEF5; Fri, 10 Jan 2020 14:54:32 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id D26397C407; Fri, 10 Jan 2020 14:54:25 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 02/16] arm: gic: Provide per-IRQ helper functions Date: Fri, 10 Jan 2020 15:53:58 +0100 Message-Id: <20200110145412.14937-3-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andre Przywara A common theme when accessing per-IRQ parameters in the GIC distributor is to set fields of a certain bit width in a range of MMIO registers. Examples are the enabled status (one bit per IRQ), the level/edge configuration (2 bits per IRQ) or the priority (8 bits per IRQ). Add a generic helper function which is able to mask and set the respective number of bits, given the IRQ number and the MMIO offset. Provide wrappers using this function to easily allow configuring an IRQ. For now assume that private IRQ numbers always refer to the current CPU. In a GICv2 accessing the "other" private IRQs is not easily doable (the registers are banked per CPU on the same MMIO address), so we impose the same limitation on GICv3, even though those registers are not banked there anymore. Signed-off-by: Andre Przywara --- initialize reg --- lib/arm/asm/gic-v3.h | 2 + lib/arm/asm/gic.h | 8 ++++ lib/arm/gic.c | 90 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 0dc838b..6beeab6 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -23,6 +23,8 @@ #define GICD_CTLR_ENABLE_G1A (1U << 1) #define GICD_CTLR_ENABLE_G1 (1U << 0) +#define GICD_IROUTER 0x6000 + /* Re-Distributor registers, offsets from RD_base */ #define GICR_TYPER 0x0008 diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 09826fd..21cdb58 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -74,5 +74,13 @@ extern void gic_write_eoir(u32 irqstat); extern void gic_ipi_send_single(int irq, int cpu); extern void gic_ipi_send_mask(int irq, const cpumask_t *dest); +void gic_set_irq_bit(int irq, int offset); +void gic_enable_irq(int irq); +void gic_disable_irq(int irq); +void gic_set_irq_priority(int irq, u8 prio); +void gic_set_irq_target(int irq, int cpu); +void gic_set_irq_group(int irq, int group); +int gic_get_irq_group(int irq); + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c index 9430116..aa9cb86 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -146,3 +146,93 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest) assert(gic_common_ops && gic_common_ops->ipi_send_mask); gic_common_ops->ipi_send_mask(irq, dest); } + +enum gic_bit_access { + ACCESS_READ, + ACCESS_SET, + ACCESS_RMW +}; + +static u8 gic_masked_irq_bits(int irq, int offset, int bits, u8 value, + enum gic_bit_access access) +{ + void *base; + int split = 32 / bits; + int shift = (irq % split) * bits; + u32 reg = 0, mask = ((1U << bits) - 1) << shift; + + switch (gic_version()) { + case 2: + base = gicv2_dist_base(); + break; + case 3: + if (irq < 32) + base = gicv3_sgi_base(); + else + base = gicv3_dist_base(); + break; + default: + return 0; + } + base += offset + (irq / split) * 4; + + switch (access) { + case ACCESS_READ: + return (readl(base) & mask) >> shift; + case ACCESS_SET: + reg = 0; + break; + case ACCESS_RMW: + reg = readl(base) & ~mask; + break; + } + + writel(reg | ((u32)value << shift), base); + + return 0; +} + +void gic_set_irq_bit(int irq, int offset) +{ + gic_masked_irq_bits(irq, offset, 1, 1, ACCESS_SET); +} + +void gic_enable_irq(int irq) +{ + gic_set_irq_bit(irq, GICD_ISENABLER); +} + +void gic_disable_irq(int irq) +{ + gic_set_irq_bit(irq, GICD_ICENABLER); +} + +void gic_set_irq_priority(int irq, u8 prio) +{ + gic_masked_irq_bits(irq, GICD_IPRIORITYR, 8, prio, ACCESS_RMW); +} + +void gic_set_irq_target(int irq, int cpu) +{ + if (irq < 32) + return; + + if (gic_version() == 2) { + gic_masked_irq_bits(irq, GICD_ITARGETSR, 8, 1U << cpu, + ACCESS_RMW); + + return; + } + + writeq(cpus[cpu], gicv3_dist_base() + GICD_IROUTER + irq * 8); +} + +void gic_set_irq_group(int irq, int group) +{ + gic_masked_irq_bits(irq, GICD_IGROUPR, 1, group, ACCESS_RMW); +} + +int gic_get_irq_group(int irq) +{ + return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ); +} From patchwork Fri Jan 10 14:53:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327543 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1C9713A0 for ; Fri, 10 Jan 2020 14:54:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A10202082E for ; Fri, 10 Jan 2020 14:54:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="SkPJEeaV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728339AbgAJOyj (ORCPT ); Fri, 10 Jan 2020 09:54:39 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:48289 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728310AbgAJOyj (ORCPT ); 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Fri, 10 Jan 2020 14:54:35 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 89C577BA5F; Fri, 10 Jan 2020 14:54:32 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 03/16] arm/arm64: gic: Introduce setup_irq() helper Date: Fri, 10 Jan 2020 15:53:59 +0100 Message-Id: <20200110145412.14937-4-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org ipi_enable() code would be reusable for other interrupts than IPI. Let's rename it setup_irq() and pass an interrupt handler pointer. We also export it to use it in other tests such as the PMU's one. Signed-off-by: Eric Auger --- arm/gic.c | 24 +++--------------------- lib/arm/asm/gic.h | 3 +++ lib/arm/gic.c | 11 +++++++++++ 3 files changed, 17 insertions(+), 21 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index fcf4c1f..ba43ae5 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -215,20 +215,9 @@ static void ipi_test_smp(void) report_prefix_pop(); } -static void ipi_enable(void) -{ - gic_enable_defaults(); -#ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, ipi_handler); -#else - install_irq_handler(EL1H_IRQ, ipi_handler); -#endif - local_irq_enable(); -} - static void ipi_send(void) { - ipi_enable(); + setup_irq(ipi_handler); wait_on_ready(); ipi_test_self(); ipi_test_smp(); @@ -238,7 +227,7 @@ static void ipi_send(void) static void ipi_recv(void) { - ipi_enable(); + setup_irq(ipi_handler); cpumask_set_cpu(smp_processor_id(), &ready); while (1) wfi(); @@ -295,14 +284,7 @@ static void ipi_clear_active_handler(struct pt_regs *regs __unused) static void run_active_clear_test(void) { report_prefix_push("active"); - gic_enable_defaults(); -#ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, ipi_clear_active_handler); -#else - install_irq_handler(EL1H_IRQ, ipi_clear_active_handler); -#endif - local_irq_enable(); - + setup_irq(ipi_clear_active_handler); ipi_test_self(); report_prefix_pop(); } diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 21cdb58..55dd84b 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -82,5 +82,8 @@ void gic_set_irq_target(int irq, int cpu); void gic_set_irq_group(int irq, int group); int gic_get_irq_group(int irq); +typedef void (*handler_t)(struct pt_regs *regs __unused); +extern void setup_irq(handler_t handler); + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c index aa9cb86..8416dde 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -236,3 +236,14 @@ int gic_get_irq_group(int irq) { return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ); } + +void setup_irq(handler_t handler) +{ + gic_enable_defaults(); +#ifdef __arm__ + install_exception_handler(EXCPTN_IRQ, handler); +#else + install_irq_handler(EL1H_IRQ, handler); +#endif + local_irq_enable(); +} From patchwork Fri Jan 10 14:54:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327537 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 29B2B921 for ; Fri, 10 Jan 2020 14:54:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F3D0120880 for ; Fri, 10 Jan 2020 14:54:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Iw/PRM+p" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728370AbgAJOyv (ORCPT ); Fri, 10 Jan 2020 09:54:51 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:44383 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728121AbgAJOyo (ORCPT ); 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Fri, 10 Jan 2020 14:54:41 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id C87D77BA5F; Fri, 10 Jan 2020 14:54:35 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 04/16] arm/arm64: gicv3: Add some re-distributor defines Date: Fri, 10 Jan 2020 15:54:00 +0100 Message-Id: <20200110145412.14937-5-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org PROPBASER, PENDBASE and GICR_CTRL will be used for LPI management. Signed-off-by: Eric Auger --- lib/arm/asm/gic-v3.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 6beeab6..ffb2e26 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -18,6 +18,7 @@ * We expect to be run in Non-secure mode, thus we define the * group1 enable bits with respect to that view. */ +#define GICD_CTLR 0x0000 #define GICD_CTLR_RWP (1U << 31) #define GICD_CTLR_ARE_NS (1U << 4) #define GICD_CTLR_ENABLE_G1A (1U << 1) @@ -36,6 +37,11 @@ #define GICR_ICENABLER0 GICD_ICENABLER #define GICR_IPRIORITYR0 GICD_IPRIORITYR +#define GICR_PROPBASER 0x0070 +#define GICR_PENDBASER 0x0078 +#define GICR_CTLR GICD_CTLR +#define GICR_CTLR_ENABLE_LPIS (1UL << 0) + #define ICC_SGI1R_AFFINITY_1_SHIFT 16 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 From patchwork Fri Jan 10 14:54:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327555 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB4BA6C1 for ; Fri, 10 Jan 2020 14:55:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AF26C2072E for ; Fri, 10 Jan 2020 14:55:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Aq+blKxO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727866AbgAJOzH (ORCPT ); Fri, 10 Jan 2020 09:55:07 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:28306 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728387AbgAJOyv (ORCPT ); Fri, 10 Jan 2020 09:54:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578668089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=q7MPK1t30Z5djTdluJykFTXQQrRrfUnQCdFQY6sF4hY=; b=Aq+blKxOfJMfpnKf5gHeIc0zqh30skQkFYXWL5g6jbTaNywcCreCJJBj9osPR5symDdSEd r7HCnKELZwsxokrXZ/s4GOKdT4CiEua5RBLvrm2na9BPUU1gAl/0i0JLvz5agbECv2uMSv GKrlfjnAYzmpXxrV7ee0QZrwDc8DRIM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-218-7wnKzNqjO_CU3kGdYYfErg-1; Fri, 10 Jan 2020 09:54:48 -0500 X-MC-Unique: 7wnKzNqjO_CU3kGdYYfErg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id ACC4E8C71A3; Fri, 10 Jan 2020 14:54:46 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 745617BA5F; Fri, 10 Jan 2020 14:54:41 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 05/16] arm/arm64: ITS: Introspection tests Date: Fri, 10 Jan 2020 15:54:01 +0100 Message-Id: <20200110145412.14937-6-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Detect the presence of an ITS as part of the GICv3 init routine, initialize its base address and read few registers the IIDR, the TYPER to store its dimensioning parameters. This is our first ITS test, belonging to a new "its" group. Signed-off-by: Eric Auger --- v1 -> v2: - clean GITS_TYPER macros and unused fields in typer struct - remove memory attribute related macros --- arm/Makefile.common | 1 + arm/gic.c | 34 ++++++++++++++++ arm/unittests.cfg | 6 +++ lib/arm/asm/gic-v3-its.h | 81 ++++++++++++++++++++++++++++++++++++++ lib/arm/asm/gic.h | 1 + lib/arm/gic-v3-its.c | 39 ++++++++++++++++++ lib/arm/gic.c | 31 ++++++++++++--- lib/arm64/asm/gic-v3-its.h | 1 + 8 files changed, 189 insertions(+), 5 deletions(-) create mode 100644 lib/arm/asm/gic-v3-its.h create mode 100644 lib/arm/gic-v3-its.c create mode 100644 lib/arm64/asm/gic-v3-its.h diff --git a/arm/Makefile.common b/arm/Makefile.common index b8988f2..1aae5a3 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -52,6 +52,7 @@ cflatobjs += lib/arm/psci.o cflatobjs += lib/arm/smp.o cflatobjs += lib/arm/delay.o cflatobjs += lib/arm/gic.o lib/arm/gic-v2.o lib/arm/gic-v3.o +cflatobjs += lib/arm/gic-v3-its.o OBJDIRS += lib/arm diff --git a/arm/gic.c b/arm/gic.c index ba43ae5..adeb981 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -506,6 +506,36 @@ static void gic_test_mmio(void) test_targets(nr_irqs); } +static void test_its_introspection(void) +{ + struct its_typer *typer = &its_data.typer; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return; + } + + /* IIDR */ + report(test_readonly_32(gicv3_its_base() + GITS_IIDR, false), + "GITS_IIDR is read-only"), + + /* TYPER */ + report(test_readonly_32(gicv3_its_base() + GITS_TYPER, false), + "GITS_TYPER is read-only"); + + report(typer->phys_lpi, "ITS supports physical LPIs"); + report_info("vLPI support: %s", typer->virt_lpi ? "yes" : "no"); + report_info("ITT entry size = 0x%x", typer->ite_size); + report_info("Bit Count: EventID=%d DeviceId=%d CollId=%d", + typer->eventid_bits, typer->deviceid_bits, + typer->collid_bits); + report(typer->eventid_bits && typer->deviceid_bits && + typer->collid_bits, "ID spaces"); + report(!typer->hw_collections, "collections only in ext memory"); + report_info("Target address format %s", + typer->pta ? "Redist basse address" : "PE #"); +} + int main(int argc, char **argv) { if (!gic_init()) { @@ -537,6 +567,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); gic_test_mmio(); report_prefix_pop(); + } else if (strcmp(argv[1], "its-introspection") == 0) { + report_prefix_push(argv[1]); + test_its_introspection(); + report_prefix_pop(); } else { report_abort("Unknown subtest '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index daeb5a0..bd20460 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -122,6 +122,12 @@ smp = $MAX_SMP extra_params = -machine gic-version=3 -append 'active' groups = gic +[its-introspection] +file = gic.flat +smp = $MAX_SMP +extra_params = -machine gic-version=3 -append 'its-introspection' +groups = its + # Test PSCI emulation [psci] file = psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h new file mode 100644 index 0000000..8816d57 --- /dev/null +++ b/lib/arm/asm/gic-v3-its.h @@ -0,0 +1,81 @@ +/* + * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h + * + * Copyright (C) 2016, Red Hat Inc, Andrew Jones + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#ifndef _ASMARM_GIC_V3_ITS_H_ +#define _ASMARM_GIC_V3_ITS_H_ + +#ifndef __ASSEMBLY__ + +#define GITS_CTLR 0x0000 +#define GITS_IIDR 0x0004 +#define GITS_TYPER 0x0008 +#define GITS_CBASER 0x0080 +#define GITS_CWRITER 0x0088 +#define GITS_CREADR 0x0090 +#define GITS_BASER 0x0100 + +#define GITS_TYPER_PLPIS BIT(0) +#define GITS_TYPER_VLPIS BIT(1) +#define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4) +#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 +#define GITS_TYPER_IDBITS GENMASK_ULL(8, 12) +#define GITS_TYPER_IDBITS_SHIFT 8 +#define GITS_TYPER_DEVBITS GENMASK_ULL(13, 17) +#define GITS_TYPER_DEVBITS_SHIFT 13 +#define GITS_TYPER_PTA BIT(19) +#define GITS_TYPER_CIDBITS GENMASK_ULL(32, 35) +#define GITS_TYPER_CIDBITS_SHIFT 32 +#define GITS_TYPER_CIL BIT(36) + +#define GITS_CTLR_ENABLE (1U << 0) + +#define GITS_CBASER_VALID (1UL << 63) + +#define GITS_BASER_NR_REGS 8 +#define GITS_BASER_VALID BIT(63) +#define GITS_BASER_INDIRECT BIT(62) +#define GITS_BASER_TYPE_SHIFT (56) +#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) +#define GITS_BASER_ENTRY_SIZE_SHIFT (48) +#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) +#define GITS_BASER_PAGE_SIZE_SHIFT (8) +#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGES_MAX 256 +#define GITS_BASER_PAGES_SHIFT (0) +#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) +#define GITS_BASER_PHYS_ADDR_MASK 0xFFFFFFFFF000 +#define GITS_BASER_TYPE_NONE 0 +#define GITS_BASER_TYPE_DEVICE 1 +#define GITS_BASER_TYPE_COLLECTION 4 + +struct its_typer { + unsigned int ite_size; + unsigned int eventid_bits; + unsigned int deviceid_bits; + unsigned int collid_bits; + bool pta; + bool phys_lpi; + bool virt_lpi; +}; + +struct its_data { + void *base; + struct its_typer typer; +}; + +extern struct its_data its_data; + +#define gicv3_its_base() (its_data.base) + +extern void its_parse_typer(void); +extern void its_init(void); + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 55dd84b..b44da9c 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -40,6 +40,7 @@ #include #include +#include #define PPI(irq) ((irq) + 16) #define SPI(irq) ((irq) + GIC_FIRST_SPI) diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c new file mode 100644 index 0000000..ce607bb --- /dev/null +++ b/lib/arm/gic-v3-its.c @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2016, Red Hat Inc, Eric Auger + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include + +struct its_data its_data; + +void its_parse_typer(void) +{ + u64 typer = readq(gicv3_its_base() + GITS_TYPER); + + its_data.typer.ite_size = ((typer & GITS_TYPER_ITT_ENTRY_SIZE) >> + GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) + 1; + its_data.typer.pta = typer & GITS_TYPER_PTA; + its_data.typer.eventid_bits = ((typer & GITS_TYPER_IDBITS) >> + GITS_TYPER_IDBITS_SHIFT) + 1; + its_data.typer.deviceid_bits = ((typer & GITS_TYPER_DEVBITS) >> + GITS_TYPER_DEVBITS_SHIFT) + 1; + + if (typer & GITS_TYPER_CIL) + its_data.typer.collid_bits = ((typer & GITS_TYPER_CIDBITS) >> + GITS_TYPER_CIDBITS_SHIFT) + 1; + else + its_data.typer.collid_bits = 16; + + its_data.typer.virt_lpi = typer & GITS_TYPER_VLPIS; + its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS; +} + +void its_init(void) +{ + if (!its_data.base) + return; + + its_parse_typer(); +} + diff --git a/lib/arm/gic.c b/lib/arm/gic.c index 8416dde..f9a6f57 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -6,6 +6,7 @@ #include #include #include +#include struct gicv2_data gicv2_data; struct gicv3_data gicv3_data; @@ -44,12 +45,14 @@ static const struct gic_common_ops gicv3_common_ops = { * Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt */ static bool -gic_get_dt_bases(const char *compatible, void **base1, void **base2) +gic_get_dt_bases(const char *compatible, void **base1, void **base2, + void **base3) { struct dt_pbus_reg reg; - struct dt_device gic; + struct dt_device gic, its; struct dt_bus bus; - int node, ret, i; + int node, subnode, ret, i, len; + const void *fdt = dt_fdt(); dt_bus_init_defaults(&bus); dt_device_init(&gic, &bus, NULL); @@ -74,19 +77,36 @@ gic_get_dt_bases(const char *compatible, void **base1, void **base2) base2[i] = ioremap(reg.addr, reg.size); } + if (base3 && !strcmp(compatible, "arm,gic-v3")) { + dt_for_each_subnode(node, subnode) { + const struct fdt_property *prop; + + prop = fdt_get_property(fdt, subnode, + "compatible", &len); + if (!strcmp((char *)prop->data, "arm,gic-v3-its")) { + dt_device_bind_node(&its, subnode); + ret = dt_pbus_translate(&its, 0, ®); + assert(ret == 0); + *base3 = ioremap(reg.addr, reg.size); + break; + } + } + + } + return true; } int gicv2_init(void) { return gic_get_dt_bases("arm,cortex-a15-gic", - &gicv2_data.dist_base, &gicv2_data.cpu_base); + &gicv2_data.dist_base, &gicv2_data.cpu_base, NULL); } int gicv3_init(void) { return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base, - &gicv3_data.redist_bases[0]); + &gicv3_data.redist_bases[0], &its_data.base); } int gic_version(void) @@ -104,6 +124,7 @@ int gic_init(void) gic_common_ops = &gicv2_common_ops; else if (gicv3_init()) gic_common_ops = &gicv3_common_ops; + its_init(); return gic_version(); } diff --git a/lib/arm64/asm/gic-v3-its.h b/lib/arm64/asm/gic-v3-its.h new file mode 100644 index 0000000..083cba4 --- /dev/null +++ b/lib/arm64/asm/gic-v3-its.h @@ -0,0 +1 @@ +#include "../../arm/asm/gic-v3-its.h" From patchwork Fri Jan 10 14:54:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327553 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3CC5B921 for ; Fri, 10 Jan 2020 14:55:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1282120880 for ; Fri, 10 Jan 2020 14:55:06 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Fri, 10 Jan 2020 09:54:51 -0500 X-MC-Unique: t4h7zcAyMMmPAqIqHvdivw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id EF2CE107ACC9; Fri, 10 Jan 2020 14:54:49 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 106DB7BA5F; Fri, 10 Jan 2020 14:54:46 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 06/16] arm/arm64: ITS: Test BASER Date: Fri, 10 Jan 2020 15:54:02 +0100 Message-Id: <20200110145412.14937-7-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add helper routines to parse and set up BASER registers. Add a new test dedicated to BASER accesses. Signed-off-by: Eric Auger --- v2 -> v3: - remove everything related to memory attributes - s/dev_baser/coll_baser/ in report_info - add extra line - removed index filed in its_baser --- arm/gic.c | 21 ++++++++++- arm/unittests.cfg | 6 +++ lib/arm/asm/gic-v3-its.h | 14 +++++++ lib/arm/gic-v3-its.c | 80 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 120 insertions(+), 1 deletion(-) diff --git a/arm/gic.c b/arm/gic.c index adeb981..3597ac3 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -531,11 +531,26 @@ static void test_its_introspection(void) typer->collid_bits); report(typer->eventid_bits && typer->deviceid_bits && typer->collid_bits, "ID spaces"); - report(!typer->hw_collections, "collections only in ext memory"); report_info("Target address format %s", typer->pta ? "Redist basse address" : "PE #"); } +static void test_its_baser(void) +{ + struct its_baser *dev_baser, *coll_baser; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return; + } + + dev_baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE); + coll_baser = its_lookup_baser(GITS_BASER_TYPE_COLLECTION); + report(dev_baser && coll_baser, "detect device and collection BASER"); + report_info("device baser entry_size = 0x%x", dev_baser->esz); + report_info("collection baser entry_size = 0x%x", coll_baser->esz); +} + int main(int argc, char **argv) { if (!gic_init()) { @@ -571,6 +586,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); test_its_introspection(); report_prefix_pop(); + } else if (strcmp(argv[1], "its-baser") == 0) { + report_prefix_push(argv[1]); + test_its_baser(); + report_prefix_pop(); } else { report_abort("Unknown subtest '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index bd20460..2234a0f 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -128,6 +128,12 @@ smp = $MAX_SMP extra_params = -machine gic-version=3 -append 'its-introspection' groups = its +[its-baser] +file = gic.flat +smp = $MAX_SMP +extra_params = -machine gic-version=3 -append 'its-baser' +groups = its + # Test PSCI emulation [psci] file = psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 8816d57..5a4dfe9 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -65,9 +65,20 @@ struct its_typer { bool virt_lpi; }; +struct its_baser { + int type; + size_t psz; + int nr_pages; + bool indirect; + phys_addr_t table_addr; + bool valid; + int esz; +}; + struct its_data { void *base; struct its_typer typer; + struct its_baser baser[GITS_BASER_NR_REGS]; }; extern struct its_data its_data; @@ -76,6 +87,9 @@ extern struct its_data its_data; extern void its_parse_typer(void); extern void its_init(void); +extern int its_parse_baser(int i, struct its_baser *baser); +extern void its_setup_baser(int i, struct its_baser *baser); +extern struct its_baser *its_lookup_baser(int type); #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index ce607bb..79946c3 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -4,6 +4,7 @@ * This work is licensed under the terms of the GNU LGPL, version 2. */ #include +#include struct its_data its_data; @@ -29,11 +30,90 @@ void its_parse_typer(void) its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS; } +int its_parse_baser(int i, struct its_baser *baser) +{ + void *reg_addr = gicv3_its_base() + GITS_BASER + i * 8; + u64 val = readq(reg_addr); + + if (!val) { + memset(baser, 0, sizeof(*baser)); + return -1; + } + + baser->valid = val & GITS_BASER_VALID; + baser->indirect = val & GITS_BASER_INDIRECT; + baser->type = GITS_BASER_TYPE(val); + baser->esz = GITS_BASER_ENTRY_SIZE(val); + baser->nr_pages = GITS_BASER_NR_PAGES(val); + baser->table_addr = val & GITS_BASER_PHYS_ADDR_MASK; + switch (val & GITS_BASER_PAGE_SIZE_MASK) { + case GITS_BASER_PAGE_SIZE_4K: + baser->psz = SZ_4K; + break; + case GITS_BASER_PAGE_SIZE_16K: + baser->psz = SZ_16K; + break; + case GITS_BASER_PAGE_SIZE_64K: + baser->psz = SZ_64K; + break; + default: + baser->psz = SZ_64K; + } + return 0; +} + +struct its_baser *its_lookup_baser(int type) +{ + int i; + + for (i = 0; i < GITS_BASER_NR_REGS; i++) { + struct its_baser *baser = &its_data.baser[i]; + + if (baser->type == type) + return baser; + } + return NULL; +} + void its_init(void) { + int i; + if (!its_data.base) return; its_parse_typer(); + for (i = 0; i < GITS_BASER_NR_REGS; i++) + its_parse_baser(i, &its_data.baser[i]); +} + +void its_setup_baser(int i, struct its_baser *baser) +{ + unsigned long n = (baser->nr_pages * baser->psz) >> PAGE_SHIFT; + unsigned long order = is_power_of_2(n) ? fls(n) : fls(n) + 1; + u64 val; + + baser->table_addr = (u64)virt_to_phys(alloc_pages(order)); + + val = ((u64)baser->table_addr | + ((u64)baser->type << GITS_BASER_TYPE_SHIFT) | + ((u64)(baser->esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | + ((baser->nr_pages - 1) << GITS_BASER_PAGES_SHIFT) | + (u64)baser->indirect << 62 | + (u64)baser->valid << 63); + + switch (baser->psz) { + case SZ_4K: + val |= GITS_BASER_PAGE_SIZE_4K; + break; + case SZ_16K: + val |= GITS_BASER_PAGE_SIZE_16K; + break; + case SZ_64K: + val |= GITS_BASER_PAGE_SIZE_64K; + break; + } + + writeq(val, gicv3_its_base() + GITS_BASER + i * 8); } From patchwork Fri Jan 10 14:54:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327547 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9452E921 for ; Fri, 10 Jan 2020 14:55:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 739AE2082E for ; Fri, 10 Jan 2020 14:55:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="dTiq6sRM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728410AbgAJOy6 (ORCPT ); Fri, 10 Jan 2020 09:54:58 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:30908 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728223AbgAJOy5 (ORCPT ); Fri, 10 Jan 2020 09:54:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578668096; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hnzALuqyh0uZ601oQnRmWo1hHMGDJqgYfkqYRybw578=; b=dTiq6sRM+EpnTaav4mR8F2LEqwoi2QL60RXCksdtSroJEsVcnqc/cl/rE5vME8147whV3y jfgURfQ/NB3VcnaJot8RBYXDhXYALs6fP3iVb6xQdGNSCn9ArqUPv9XaVhkNyXUDTW1VEx 2/5svbpNJJo99585GmFnNlSSI7RR81E= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-33-L6q4vxrGMBe3EPeq3xolFw-1; Fri, 10 Jan 2020 09:54:55 -0500 X-MC-Unique: L6q4vxrGMBe3EPeq3xolFw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 408CE2F63; Fri, 10 Jan 2020 14:54:53 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 520987BA5F; Fri, 10 Jan 2020 14:54:50 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 07/16] arm/arm64: ITS: Set the LPI config and pending tables Date: Fri, 10 Jan 2020 15:54:03 +0100 Message-Id: <20200110145412.14937-8-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by default in the config table. Also introduce a helper routine that allows to set the pending table bit for a given LPI. Signed-off-by: Eric Auger --- v1 -> v2: - remove memory attributes --- lib/arm/asm/gic-v3-its.h | 3 ++ lib/arm/asm/gic-v3.h | 12 ++++++++ lib/arm/gic-v3-its.c | 60 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 5a4dfe9..2f8b8f1 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -90,6 +90,9 @@ extern void its_init(void); extern int its_parse_baser(int i, struct its_baser *baser); extern void its_setup_baser(int i, struct its_baser *baser); extern struct its_baser *its_lookup_baser(int type); +extern void set_lpi_config(int n, u8 val); +extern u8 get_lpi_config(int n); +extern void set_pending_table_bit(int rdist, int n, bool set); #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index ffb2e26..90a7304 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -48,6 +48,16 @@ #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ (MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level ## _SHIFT) +#define GICR_PROPBASER_IDBITS_MASK (0x1f) + +#define GICR_PENDBASER_PTZ BIT_ULL(62) + +#define LPI_PROP_GROUP1 (1 << 1) +#define LPI_PROP_ENABLED (1 << 0) +#define LPI_PROP_DEFAULT_PRIO 0xa0 +#define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | \ + LPI_PROP_ENABLED) + #include #ifndef __ASSEMBLY__ @@ -64,6 +74,8 @@ struct gicv3_data { void *dist_base; void *redist_bases[GICV3_NR_REDISTS]; void *redist_base[NR_CPUS]; + void *lpi_prop; + void *lpi_pend[NR_CPUS]; unsigned int irq_nr; }; extern struct gicv3_data gicv3_data; diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 79946c3..6c97569 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -117,3 +117,63 @@ void its_setup_baser(int i, struct its_baser *baser) writeq(val, gicv3_its_base() + GITS_BASER + i * 8); } +inline void set_lpi_config(int n, u8 value) +{ + u8 *entry = (u8 *)(gicv3_data.lpi_prop + (n - 8192)); + *entry = value; +} + +inline u8 get_lpi_config(int n) +{ + u8 *entry = (u8 *)(gicv3_data.lpi_prop + (n - 8192)); + return *entry; +} + +/* alloc_lpi_tables: Allocate LPI config and pending tables */ +void alloc_lpi_tables(void); +void alloc_lpi_tables(void) +{ + unsigned long n = SZ_64K >> PAGE_SHIFT; + unsigned long order = fls(n); + u64 prop_val; + int cpu; + + gicv3_data.lpi_prop = (void *)virt_to_phys(alloc_pages(order)); + + /* ID bits = 13, ie. up to 14b LPI INTID */ + prop_val = (u64)gicv3_data.lpi_prop | 13; + + /* + * Allocate pending tables for each redistributor + * and set PROPBASER and PENDBASER + */ + for_each_present_cpu(cpu) { + u64 pend_val; + void *ptr; + + ptr = gicv3_data.redist_base[cpu]; + + writeq(prop_val, ptr + GICR_PROPBASER); + + gicv3_data.lpi_pend[cpu] = + (void *)virt_to_phys(alloc_pages(order)); + + pend_val = (u64)gicv3_data.lpi_pend[cpu]; + + writeq(pend_val, ptr + GICR_PENDBASER); + } +} + +void set_pending_table_bit(int rdist, int n, bool set) +{ + u8 *ptr = phys_to_virt((phys_addr_t)gicv3_data.lpi_pend[rdist]); + u8 mask = 1 << (n % 8), byte; + + ptr += (n / 8); + byte = *ptr; + if (set) + byte |= mask; + else + byte &= ~mask; + *ptr = byte; +} From patchwork Fri Jan 10 14:54:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327551 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C50F921 for ; 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b=K8BdgWuptBdYE63G3iqJD0xUVK+55fFiMNY3cb5QeXGzqdkHoCtTuOnMup+u/NfdX++aZ0 6BxadmuhF1hyPkRzRughHJguWLS2MMb5Sr3MWZZLj/AOaaUDP3CHeqvVVam+SgH8yDbiLZ 53cpcB3Zb7g6D/0UDY4+bekf/uzlqDc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-208-DYg8o0oeNLOx-mCafe7VpQ-1; Fri, 10 Jan 2020 09:55:00 -0500 X-MC-Unique: DYg8o0oeNLOx-mCafe7VpQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 068151085984; Fri, 10 Jan 2020 14:54:59 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 989097BA5F; Fri, 10 Jan 2020 14:54:53 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 08/16] arm/arm64: ITS: Init the command queue Date: Fri, 10 Jan 2020 15:54:04 +0100 Message-Id: <20200110145412.14937-9-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Allocate the command queue and initialize related registers: CBASER, CREADR, CWRITER. The command queue is 64kB. This aims at not bothing with fullness. Signed-off-by: Eric Auger --- v2 -> v3: - removed readr --- lib/arm/asm/gic-v3-its.h | 6 ++++++ lib/arm/gic-v3-its.c | 22 ++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 2f8b8f1..93814f7 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -75,10 +75,16 @@ struct its_baser { int esz; }; +struct its_cmd_block { + u64 raw_cmd[4]; +}; + struct its_data { void *base; struct its_typer typer; struct its_baser baser[GITS_BASER_NR_REGS]; + struct its_cmd_block *cmd_base; + struct its_cmd_block *cmd_write; }; extern struct its_data its_data; diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 6c97569..3037c84 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -177,3 +177,25 @@ void set_pending_table_bit(int rdist, int n, bool set) byte &= ~mask; *ptr = byte; } + +/** + * init_cmd_queue: Allocate the command queue and initialize + * CBASER, CREADR, CWRITER + */ +void init_cmd_queue(void); +void init_cmd_queue(void) +{ + unsigned long n = SZ_64K >> PAGE_SHIFT; + unsigned long order = fls(n); + u64 cbaser; + + its_data.cmd_base = (void *)virt_to_phys(alloc_pages(order)); + + cbaser = ((u64)its_data.cmd_base | (SZ_64K / SZ_4K - 1) | + GITS_CBASER_VALID); + + writeq(cbaser, its_data.base + GITS_CBASER); + + its_data.cmd_write = its_data.cmd_base; + writeq(0, its_data.base + GITS_CWRITER); +} From patchwork Fri Jan 10 14:54:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327557 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8717C921 for ; Fri, 10 Jan 2020 14:55:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 663402084D for ; Fri, 10 Jan 2020 14:55:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="RNJzlCon" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728442AbgAJOzN (ORCPT ); Fri, 10 Jan 2020 09:55:13 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:48584 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728422AbgAJOzM (ORCPT ); Fri, 10 Jan 2020 09:55:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578668111; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gBKAcnxc2MYZzCoP970ndMhL3JY30iNVMqi2oK57oys=; b=RNJzlConDDNJyLKfAVOIcB28NlVTMKWNNfwAP1WZ9wxnoAS9E+xe4A9SndEUoZx3SrHtBW HUvjkqVQauMzL0NSNQSYT9lpbCeb9X97jCr4IEFZjEBFGVT4HAGPioUP7LzCdRCRFifDzG yxbNrCcpHsD8lwvicvKTmzrFHqIvYkE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-137-JQMSqK-yNEazhUrjO_r2Cg-1; Fri, 10 Jan 2020 09:55:10 -0500 X-MC-Unique: JQMSqK-yNEazhUrjO_r2Cg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 841A6108838E; Fri, 10 Jan 2020 14:55:07 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5DB427BA5F; Fri, 10 Jan 2020 14:54:59 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 09/16] arm/arm64: ITS: Enable/Disable LPIs at re-distributor level Date: Fri, 10 Jan 2020 15:54:05 +0100 Message-Id: <20200110145412.14937-10-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This helper function enables or disables the signaling of LPIs at redistributor level. Signed-off-by: Eric Auger --- lib/arm/asm/gic-v3-its.h | 1 + lib/arm/gic-v3-its.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 93814f7..d2db292 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -99,6 +99,7 @@ extern struct its_baser *its_lookup_baser(int type); extern void set_lpi_config(int n, u8 val); extern u8 get_lpi_config(int n); extern void set_pending_table_bit(int rdist, int n, bool set); +extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set); #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 3037c84..c7c6f80 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -199,3 +199,21 @@ void init_cmd_queue(void) its_data.cmd_write = its_data.cmd_base; writeq(0, its_data.base + GITS_CWRITER); } + +void gicv3_rdist_ctrl_lpi(u32 redist, bool set) +{ + void *ptr; + u64 val; + + if (redist >= nr_cpus) + report_abort("%s redist=%d >= cpu_count=%d\n", + __func__, redist, nr_cpus); + + ptr = gicv3_data.redist_base[redist]; + val = readl(ptr + GICR_CTLR); + if (set) + val |= GICR_CTLR_ENABLE_LPIS; + else + val &= ~GICR_CTLR_ENABLE_LPIS; + writel(val, ptr + GICR_CTLR); +} From patchwork Fri Jan 10 14:54:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327559 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4D469921 for ; Fri, 10 Jan 2020 14:55:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2DB8D2084D for ; Fri, 10 Jan 2020 14:55:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="T++sQJcY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728451AbgAJOzQ (ORCPT ); Fri, 10 Jan 2020 09:55:16 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:24304 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727363AbgAJOzP (ORCPT ); Fri, 10 Jan 2020 09:55:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578668114; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A9N2aRoAuhJExNcXHHKcgXxx/GMzDOlebGq7Fw5BkDk=; b=T++sQJcYvd6/4QW72EImRHQF1qU08x/Q92C75XduFj0EAD1fLR7IcXZ4xoI/q+Fi9rKieS wjzf2ATHJR440JM8SdI1Y0w9xt8q3Zw8OqBMVfbIBVN0TEkenDZ5Ok9vChIm8f0m/RYHEd C0TO78eU7Ny6s4yce+MNGoD2fVNmC8s= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-242-ePoRKuSlMn2JcuCbsgeOXA-1; Fri, 10 Jan 2020 09:55:13 -0500 X-MC-Unique: ePoRKuSlMn2JcuCbsgeOXA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id D690318C43CF; Fri, 10 Jan 2020 14:55:10 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id DC5647C3E2; Fri, 10 Jan 2020 14:55:07 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 10/16] arm/arm64: ITS: its_enable_defaults Date: Fri, 10 Jan 2020 15:54:06 +0100 Message-Id: <20200110145412.14937-11-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org its_enable_defaults() is the top init function that allocates all the requested tables (device, collection, lpi config and pending tables), enable LPIs at distributor level and ITS level. gicv3_enable_defaults must be called before. Signed-off-by: Eric Auger --- lib/arm/asm/gic-v3-its.h | 1 + lib/arm/gic-v3-its.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index d2db292..0e31848 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -100,6 +100,7 @@ extern void set_lpi_config(int n, u8 val); extern u8 get_lpi_config(int n); extern void set_pending_table_bit(int rdist, int n, bool set); extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set); +extern void its_enable_defaults(void); #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index c7c6f80..f488cca 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -217,3 +217,43 @@ void gicv3_rdist_ctrl_lpi(u32 redist, bool set) val &= ~GICR_CTLR_ENABLE_LPIS; writel(val, ptr + GICR_CTLR); } + +void its_enable_defaults(void) +{ + unsigned int i; + + its_parse_typer(); + + /* Allocate BASER tables (device and collection tables) */ + for (i = 0; i < GITS_BASER_NR_REGS; i++) { + struct its_baser *baser = &its_data.baser[i]; + int ret; + + ret = its_parse_baser(i, baser); + if (ret) + continue; + + switch (baser->type) { + case GITS_BASER_TYPE_DEVICE: + baser->valid = true; + its_setup_baser(i, baser); + break; + case GITS_BASER_TYPE_COLLECTION: + baser->valid = true; + its_setup_baser(i, baser); + break; + default: + break; + } + } + + /* Allocate LPI config and pending tables */ + alloc_lpi_tables(); + + init_cmd_queue(); + + for (i = 0; i < nr_cpus; i++) + gicv3_rdist_ctrl_lpi(i, true); + + writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR); +} From patchwork Fri Jan 10 14:54:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327561 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 949BA6C1 for ; Fri, 10 Jan 2020 14:55:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 73F3A2084D for ; Fri, 10 Jan 2020 14:55:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="BhUTnWx4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728438AbgAJOzT (ORCPT ); Fri, 10 Jan 2020 09:55:19 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:31705 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728422AbgAJOzS (ORCPT ); Fri, 10 Jan 2020 09:55:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578668117; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X4Gf0sfl6C9fhnClEr3mTacurTeinVm4glIO0ZFtMoc=; b=BhUTnWx4pBxsb4bKuYNPdj5C9WRq9Mexhs5DWARGd3U4cEY/NUvcHPb5NXI97NaQS+KYNS npGxT5A2nVCoS2Dgto0/FMPrKRxU7+w+NbNNmRKU4CPrAi07orpe1fOXwx6VhICO9bNLFY 4Q1F9NfXZrSZh8ZxLpq5F16diENgJ78= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-350-vHCJMhfmO8mXr5V5KEzNWA-1; Fri, 10 Jan 2020 09:55:15 -0500 X-MC-Unique: vHCJMhfmO8mXr5V5KEzNWA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 272A380257A; Fri, 10 Jan 2020 14:55:14 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3A9E07BA5F; Fri, 10 Jan 2020 14:55:11 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 11/16] arm/arm64: ITS: Device and collection Initialization Date: Fri, 10 Jan 2020 15:54:07 +0100 Message-Id: <20200110145412.14937-12-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce an helper functions to register - a new device, characterized by its device id and the max number of event IDs that dimension its ITT (Interrupt Translation Table). The function allocates the ITT. - a new collection, characterized by its ID and the target processing engine (PE). Signed-off-by: Eric Auger --- v2 -> v3: - s/nb_/nr_ --- lib/arm/asm/gic-v3-its.h | 20 +++++++++++++++++ lib/arm/gic-v3-its.c | 46 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 0e31848..0497a78 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -55,6 +55,9 @@ #define GITS_BASER_TYPE_DEVICE 1 #define GITS_BASER_TYPE_COLLECTION 4 +#define GITS_MAX_DEVICES 8 +#define GITS_MAX_COLLECTIONS 8 + struct its_typer { unsigned int ite_size; unsigned int eventid_bits; @@ -79,12 +82,27 @@ struct its_cmd_block { u64 raw_cmd[4]; }; +struct its_device { + u32 device_id; /* device ID */ + u32 nr_ites; /* Max Interrupt Translation Entries */ + void *itt; /* Interrupt Translation Table GPA */ +}; + +struct its_collection { + u64 target_address; + u16 col_id; +}; + struct its_data { void *base; struct its_typer typer; struct its_baser baser[GITS_BASER_NR_REGS]; struct its_cmd_block *cmd_base; struct its_cmd_block *cmd_write; + struct its_device devices[GITS_MAX_DEVICES]; + u32 nr_devices; /* Allocated Devices */ + struct its_collection collections[GITS_MAX_COLLECTIONS]; + u32 nr_collections; /* Allocated Collections */ }; extern struct its_data its_data; @@ -101,6 +119,8 @@ extern u8 get_lpi_config(int n); extern void set_pending_table_bit(int rdist, int n, bool set); extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set); extern void its_enable_defaults(void); +extern struct its_device *its_create_device(u32 dev_id, int nr_ites); +extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe); #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index f488cca..88c08ee 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -257,3 +257,49 @@ void its_enable_defaults(void) writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR); } + +struct its_device *its_create_device(u32 device_id, int nr_ites) +{ + struct its_baser *baser; + struct its_device *new; + unsigned long n, order; + + if (its_data.nr_devices >= GITS_MAX_DEVICES) + report_abort("%s redimension GITS_MAX_DEVICES", __func__); + + baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE); + if (!baser) + return NULL; + + new = &its_data.devices[its_data.nr_devices]; + + new->device_id = device_id; + new->nr_ites = nr_ites; + + n = (its_data.typer.ite_size * nr_ites) >> PAGE_SHIFT; + order = is_power_of_2(n) ? fls(n) : fls(n) + 1; + new->itt = (void *)virt_to_phys(alloc_pages(order)); + + its_data.nr_devices++; + return new; +} + +struct its_collection *its_create_collection(u32 col_id, u32 pe) +{ + struct its_collection *new; + + if (its_data.nr_collections >= GITS_MAX_COLLECTIONS) + report_abort("%s redimension GITS_MAX_COLLECTIONS", __func__); + + new = &its_data.collections[its_data.nr_collections]; + + new->col_id = col_id; + + if (its_data.typer.pta) + new->target_address = (u64)gicv3_data.redist_base[pe]; + else + new->target_address = pe << 16; + + its_data.nr_collections++; + return new; +} From patchwork Fri Jan 10 14:54:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327565 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3F72B6C1 for ; Fri, 10 Jan 2020 14:55:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 079652072E for ; Fri, 10 Jan 2020 14:55:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="WkFL1KY1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728468AbgAJOzW (ORCPT ); Fri, 10 Jan 2020 09:55:22 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:23546 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728464AbgAJOzW (ORCPT ); Fri, 10 Jan 2020 09:55:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578668120; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aTriFbjg+KTXFXNVq3B1F0AYstGQbF6Xm4dB+5LymY0=; b=WkFL1KY1kqx0Y8qhonlvDk0YTHIK34zX57raDgy2OKbQXysnIJO8thFV2fpZFSSLW4YZPe ZHmGmFTWPiSuMNIUMDA9ktOdc+KvwfWRj5mEiGj4Hi9FAR4hFxK/1/ui2hW4lcjenfMx1s QKFKymKLB03VzYnrsEJQlkkvzUEOdCA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-168-rCA5sDRrOg-dIHWM7zytDA-1; Fri, 10 Jan 2020 09:55:19 -0500 X-MC-Unique: rCA5sDRrOg-dIHWM7zytDA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6DB5F10883A1; Fri, 10 Jan 2020 14:55:17 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7EF2D7BA5F; Fri, 10 Jan 2020 14:55:14 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 12/16] arm/arm64: ITS: commands Date: Fri, 10 Jan 2020 15:54:08 +0100 Message-Id: <20200110145412.14937-13-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Implement main ITS commands. The code is largely inherited from the ITS driver. Signed-off-by: Eric Auger --- v1 -> v2: - removed its_print_cmd_state --- arm/Makefile.common | 2 +- lib/arm/asm/gic-v3-its.h | 35 +++ lib/arm/gic-v3-its-cmd.c | 453 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 489 insertions(+), 1 deletion(-) create mode 100644 lib/arm/gic-v3-its-cmd.c diff --git a/arm/Makefile.common b/arm/Makefile.common index 1aae5a3..7cc0f04 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -52,7 +52,7 @@ cflatobjs += lib/arm/psci.o cflatobjs += lib/arm/smp.o cflatobjs += lib/arm/delay.o cflatobjs += lib/arm/gic.o lib/arm/gic-v2.o lib/arm/gic-v3.o -cflatobjs += lib/arm/gic-v3-its.o +cflatobjs += lib/arm/gic-v3-its.o lib/arm/gic-v3-its-cmd.o OBJDIRS += lib/arm diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 0497a78..463174f 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -58,6 +58,24 @@ #define GITS_MAX_DEVICES 8 #define GITS_MAX_COLLECTIONS 8 +/* + * ITS commands + */ +#define GITS_CMD_MAPD 0x08 +#define GITS_CMD_MAPC 0x09 +#define GITS_CMD_MAPTI 0x0a +/* older GIC documentation used MAPVI for this command */ +#define GITS_CMD_MAPVI GITS_CMD_MAPTI +#define GITS_CMD_MAPI 0x0b +#define GITS_CMD_MOVI 0x01 +#define GITS_CMD_DISCARD 0x0f +#define GITS_CMD_INV 0x0c +#define GITS_CMD_MOVALL 0x0e +#define GITS_CMD_INVALL 0x0d +#define GITS_CMD_INT 0x03 +#define GITS_CMD_CLEAR 0x04 +#define GITS_CMD_SYNC 0x05 + struct its_typer { unsigned int ite_size; unsigned int eventid_bits; @@ -122,5 +140,22 @@ extern void its_enable_defaults(void); extern struct its_device *its_create_device(u32 dev_id, int nr_ites); extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe); +extern void its_send_mapd(struct its_device *dev, int valid); +extern void its_send_mapc(struct its_collection *col, int valid); +extern void its_send_mapti(struct its_device *dev, u32 irq_id, + u32 event_id, struct its_collection *col); +extern void its_send_int(struct its_device *dev, u32 event_id); +extern void its_send_inv(struct its_device *dev, u32 event_id); +extern void its_send_discard(struct its_device *dev, u32 event_id); +extern void its_send_clear(struct its_device *dev, u32 event_id); +extern void its_send_invall(struct its_collection *col); +extern void its_send_movi(struct its_device *dev, + struct its_collection *col, u32 id); +extern void its_send_sync(struct its_collection *col); + +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) +#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) +#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_ITS_H_ */ diff --git a/lib/arm/gic-v3-its-cmd.c b/lib/arm/gic-v3-its-cmd.c new file mode 100644 index 0000000..9c6cbc6 --- /dev/null +++ b/lib/arm/gic-v3-its-cmd.c @@ -0,0 +1,453 @@ +/* + * Copyright (C) 2016, Red Hat Inc, Eric Auger + * + * Most of the code is copy-pasted from: + * drivers/irqchip/irq-gic-v3-its.c + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include +#include + +#define ITS_ITT_ALIGN SZ_256 + +static const char * const its_cmd_string[] = { + [GITS_CMD_MAPD] = "MAPD", + [GITS_CMD_MAPC] = "MAPC", + [GITS_CMD_MAPTI] = "MAPTI", + [GITS_CMD_MAPI] = "MAPI", + [GITS_CMD_MOVI] = "MOVI", + [GITS_CMD_DISCARD] = "DISCARD", + [GITS_CMD_INV] = "INV", + [GITS_CMD_MOVALL] = "MOVALL", + [GITS_CMD_INVALL] = "INVALL", + [GITS_CMD_INT] = "INT", + [GITS_CMD_CLEAR] = "CLEAR", + [GITS_CMD_SYNC] = "SYNC", +}; + +struct its_cmd_desc { + union { + struct { + struct its_device *dev; + u32 event_id; + } its_inv_cmd; + + struct { + struct its_device *dev; + u32 event_id; + } its_int_cmd; + + struct { + struct its_device *dev; + bool valid; + } its_mapd_cmd; + + struct { + struct its_collection *col; + bool valid; + } its_mapc_cmd; + + struct { + struct its_device *dev; + u32 phys_id; + u32 event_id; + u32 col_id; + } its_mapti_cmd; + + struct { + struct its_device *dev; + struct its_collection *col; + u32 event_id; + } its_movi_cmd; + + struct { + struct its_device *dev; + u32 event_id; + } its_discard_cmd; + + struct { + struct its_device *dev; + u32 event_id; + } its_clear_cmd; + + struct { + struct its_collection *col; + } its_invall_cmd; + + struct { + struct its_collection *col; + } its_sync_cmd; + }; +}; + +typedef void (*its_cmd_builder_t)(struct its_cmd_block *, + struct its_cmd_desc *); + +/* ITS COMMANDS */ + +static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) +{ + cmd->raw_cmd[0] &= ~0xffUL; + cmd->raw_cmd[0] |= cmd_nr; +} + +static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) +{ + cmd->raw_cmd[0] &= BIT_ULL(32) - 1; + cmd->raw_cmd[0] |= ((u64)devid) << 32; +} + +static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) +{ + cmd->raw_cmd[1] &= ~0xffffffffUL; + cmd->raw_cmd[1] |= id; +} + +static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) +{ + cmd->raw_cmd[1] &= 0xffffffffUL; + cmd->raw_cmd[1] |= ((u64)phys_id) << 32; +} + +static void its_encode_size(struct its_cmd_block *cmd, u8 size) +{ + cmd->raw_cmd[1] &= ~0x1fUL; + cmd->raw_cmd[1] |= size & 0x1f; +} + +static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) +{ + cmd->raw_cmd[2] &= ~0xffffffffffffUL; + cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL; +} + +static void its_encode_valid(struct its_cmd_block *cmd, int valid) +{ + cmd->raw_cmd[2] &= ~(1UL << 63); + cmd->raw_cmd[2] |= ((u64)!!valid) << 63; +} + +static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) +{ + cmd->raw_cmd[2] &= ~(0xfffffffffUL << 16); + cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16)); +} + +static void its_encode_collection(struct its_cmd_block *cmd, u16 col) +{ + cmd->raw_cmd[2] &= ~0xffffUL; + cmd->raw_cmd[2] |= col; +} + +static inline void its_fixup_cmd(struct its_cmd_block *cmd) +{ + /* Let's fixup BE commands */ + cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); + cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); + cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); + cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); +} + +static u64 its_cmd_ptr_to_offset(struct its_cmd_block *ptr) +{ + return (ptr - its_data.cmd_base) * sizeof(*ptr); +} + +static struct its_cmd_block *its_post_commands(void) +{ + u64 wr = its_cmd_ptr_to_offset(its_data.cmd_write); + + writeq(wr, its_data.base + GITS_CWRITER); + return its_data.cmd_write; +} + + +/* We just assume the queue is large enough */ +static struct its_cmd_block *its_allocate_entry(void) +{ + struct its_cmd_block *cmd; + + cmd = its_data.cmd_write++; + return cmd; +} + +static void its_wait_for_range_completion(struct its_cmd_block *from, + struct its_cmd_block *to) +{ + u64 rd_idx, from_idx, to_idx; + u32 count = 1000000; /* 1s! */ + + from_idx = its_cmd_ptr_to_offset(from); + to_idx = its_cmd_ptr_to_offset(to); + while (1) { + rd_idx = readq(its_data.base + GITS_CREADR); + if (rd_idx >= to_idx || rd_idx < from_idx) + break; + + count--; + if (!count) { + unsigned int cmd_id = from->raw_cmd[0] & 0xFF; + + report(false, "%s timeout!", + cmd_id <= 0xF ? its_cmd_string[cmd_id] : + "Unexpected"); + return; + } + cpu_relax(); + udelay(1); + } +} + +static void its_send_single_command(its_cmd_builder_t builder, + struct its_cmd_desc *desc) +{ + struct its_cmd_block *cmd, *next_cmd; + + cmd = its_allocate_entry(); + builder(cmd, desc); + next_cmd = its_post_commands(); + + its_wait_for_range_completion(cmd, next_cmd); +} + + +static void its_build_mapd_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + unsigned long itt_addr; + u8 size = 12; //TODO ilog2(desc->its_mapd_cmd.dev->nr_ites); + + itt_addr = (unsigned long)desc->its_mapd_cmd.dev->itt; + itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); + + its_encode_cmd(cmd, GITS_CMD_MAPD); + its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); + its_encode_size(cmd, size - 1); + its_encode_itt(cmd, itt_addr); + its_encode_valid(cmd, desc->its_mapd_cmd.valid); + + its_fixup_cmd(cmd); + report_info("MAPD devid=%d size = 0x%x itt=0x%lx valid=%d", + desc->its_mapd_cmd.dev->device_id, + size, itt_addr, desc->its_mapd_cmd.valid); + +} + +static void its_build_mapc_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_MAPC); + its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); + its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); + its_encode_valid(cmd, desc->its_mapc_cmd.valid); + + its_fixup_cmd(cmd); + report_info("MAPC col_id=%d target_addr = 0x%lx valid=%d", + desc->its_mapc_cmd.col->col_id, + desc->its_mapc_cmd.col->target_address, + desc->its_mapc_cmd.valid); +} + +static void its_build_mapti_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_MAPTI); + its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); + its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); + its_encode_collection(cmd, desc->its_mapti_cmd.col_id); + + its_fixup_cmd(cmd); + report_info("MAPTI dev_id=%d event_id=%d -> phys_id=%d, col_id=%d", + desc->its_mapti_cmd.dev->device_id, + desc->its_mapti_cmd.event_id, + desc->its_mapti_cmd.phys_id, + desc->its_mapti_cmd.col_id); +} + +static void its_build_invall_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_INVALL); + its_encode_collection(cmd, desc->its_invall_cmd.col->col_id); + + its_fixup_cmd(cmd); + report_info("INVALL col_id=%d", desc->its_invall_cmd.col->col_id); +} + +static void its_build_clear_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_CLEAR); + its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_clear_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("CLEAR col_id=%d", desc->its_invall_cmd.col->col_id); +} + +static void its_build_discard_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_DISCARD); + its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_discard_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("DISCARD col_id=%d", desc->its_invall_cmd.col->col_id); +} + +static void its_build_inv_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_INV); + its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_inv_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("INV dev_id=%d event_id=%d", + desc->its_inv_cmd.dev->device_id, + desc->its_inv_cmd.event_id); +} + +static void its_build_int_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_INT); + its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_int_cmd.event_id); + + its_fixup_cmd(cmd); + report_info("INT dev_id=%d event_id=%d", + desc->its_int_cmd.dev->device_id, + desc->its_int_cmd.event_id); +} + +static void its_build_sync_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_SYNC); + its_encode_target(cmd, desc->its_sync_cmd.col->target_address); + its_fixup_cmd(cmd); + report_info("SYNC target_addr = 0x%lx", + desc->its_sync_cmd.col->target_address); +} + +static void its_build_movi_cmd(struct its_cmd_block *cmd, + struct its_cmd_desc *desc) +{ + its_encode_cmd(cmd, GITS_CMD_MOVI); + its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); + its_encode_event_id(cmd, desc->its_movi_cmd.event_id); + its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); + + its_fixup_cmd(cmd); + report_info("MOVI dev_id=%d event_id = %d col_id=%d", + desc->its_movi_cmd.dev->device_id, + desc->its_movi_cmd.event_id, + desc->its_movi_cmd.col->col_id); +} + +void its_send_mapd(struct its_device *dev, int valid) +{ + struct its_cmd_desc desc; + + desc.its_mapd_cmd.dev = dev; + desc.its_mapd_cmd.valid = !!valid; + + its_send_single_command(its_build_mapd_cmd, &desc); +} + +void its_send_mapc(struct its_collection *col, int valid) +{ + struct its_cmd_desc desc; + + desc.its_mapc_cmd.col = col; + desc.its_mapc_cmd.valid = !!valid; + + its_send_single_command(its_build_mapc_cmd, &desc); +} + +void its_send_mapti(struct its_device *dev, u32 irq_id, + u32 event_id, struct its_collection *col) +{ + struct its_cmd_desc desc; + + desc.its_mapti_cmd.dev = dev; + desc.its_mapti_cmd.phys_id = irq_id; + desc.its_mapti_cmd.event_id = event_id; + desc.its_mapti_cmd.col_id = col->col_id; + + its_send_single_command(its_build_mapti_cmd, &desc); +} + +void its_send_int(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_int_cmd.dev = dev; + desc.its_int_cmd.event_id = event_id; + + its_send_single_command(its_build_int_cmd, &desc); +} + +void its_send_movi(struct its_device *dev, + struct its_collection *col, u32 id) +{ + struct its_cmd_desc desc; + + desc.its_movi_cmd.dev = dev; + desc.its_movi_cmd.col = col; + desc.its_movi_cmd.event_id = id; + + its_send_single_command(its_build_movi_cmd, &desc); +} + +void its_send_invall(struct its_collection *col) +{ + struct its_cmd_desc desc; + + desc.its_invall_cmd.col = col; + + its_send_single_command(its_build_invall_cmd, &desc); +} + +void its_send_inv(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_inv_cmd.dev = dev; + desc.its_inv_cmd.event_id = event_id; + + its_send_single_command(its_build_inv_cmd, &desc); +} + +void its_send_discard(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_discard_cmd.dev = dev; + desc.its_discard_cmd.event_id = event_id; + + its_send_single_command(its_build_discard_cmd, &desc); +} + +void its_send_clear(struct its_device *dev, u32 event_id) +{ + struct its_cmd_desc desc; + + desc.its_clear_cmd.dev = dev; + desc.its_clear_cmd.event_id = event_id; + + its_send_single_command(its_build_clear_cmd, &desc); +} + +void its_send_sync(struct its_collection *col) +{ + struct its_cmd_desc desc; + + desc.its_sync_cmd.col = col; + + its_send_single_command(its_build_sync_cmd, &desc); +} + From patchwork Fri Jan 10 14:54:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327567 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67D3E6C1 for ; Fri, 10 Jan 2020 14:55:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3C0B42084D for ; Fri, 10 Jan 2020 14:55:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="fcTdnrN8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728455AbgAJOz1 (ORCPT ); Fri, 10 Jan 2020 09:55:27 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:51039 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728422AbgAJOz1 (ORCPT ); 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Fri, 10 Jan 2020 14:55:22 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id C5B417BA5F; Fri, 10 Jan 2020 14:55:17 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 13/16] arm/arm64: ITS: INT functional tests Date: Fri, 10 Jan 2020 15:54:09 +0100 Message-Id: <20200110145412.14937-14-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Triggers LPIs through the INT command. the test checks the LPI hits the right CPU and triggers the right LPI intid, ie. the translation is correct. Updates to the config table also are tested, along with inv and invall commands. Signed-off-by: Eric Auger --- arm/gic.c | 174 +++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 6 ++ lib/arm/asm/gic-v3-its.h | 14 ++++ 3 files changed, 194 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 3597ac3..7f701a1 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -34,6 +34,7 @@ static struct gic *gic; static int acked[NR_CPUS], spurious[NR_CPUS]; static int bad_sender[NR_CPUS], bad_irq[NR_CPUS]; static cpumask_t ready; +static struct its_stats lpi_stats; static void nr_cpu_check(int nr) { @@ -158,6 +159,54 @@ static void ipi_handler(struct pt_regs *regs __unused) } } +static void lpi_handler(struct pt_regs *regs __unused) +{ + u32 irqstat = gic_read_iar(); + int irqnr = gic_iar_irqnr(irqstat); + + gic_write_eoir(irqstat); + if (irqnr < 8192) + report(false, "Unexpected non LPI interrupt received"); + smp_rmb(); /* pairs with wmb in lpi_stats_expect */ + lpi_stats.observed.cpu_id = smp_processor_id(); + lpi_stats.observed.lpi_id = irqnr; + smp_wmb(); /* pairs with rmb in check_lpi_stats */ +} + +static void lpi_stats_expect(int exp_cpu_id, int exp_lpi_id) +{ + lpi_stats.expected.cpu_id = exp_cpu_id; + lpi_stats.expected.lpi_id = exp_lpi_id; + lpi_stats.observed.cpu_id = -1; + lpi_stats.observed.lpi_id = -1; + smp_wmb(); /* pairs with rmb in handler */ +} + +static void check_lpi_stats(void) +{ + mdelay(100); + smp_rmb(); /* pairs with wmb in lpi_handler */ + if ((lpi_stats.observed.cpu_id != lpi_stats.expected.cpu_id) || + (lpi_stats.observed.lpi_id != lpi_stats.expected.lpi_id)) { + if (lpi_stats.observed.cpu_id == -1 && + lpi_stats.observed.lpi_id == -1) { + report(false, + "No LPI received whereas (cpuid=%d, intid=%d) " + "was expected", lpi_stats.expected.cpu_id, + lpi_stats.expected.lpi_id); + } else { + report(false, "Unexpected LPI (cpuid=%d, intid=%d)", + lpi_stats.observed.cpu_id, + lpi_stats.observed.lpi_id); + } + } else if (lpi_stats.expected.lpi_id != -1) { + report(true, "LPI %d on CPU %d", lpi_stats.observed.lpi_id, + lpi_stats.observed.cpu_id); + } else { + report(true, "no LPI received, as expected"); + } +} + static void gicv2_ipi_send_self(void) { writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); @@ -241,6 +290,14 @@ static void ipi_test(void *data __unused) ipi_recv(); } +static void secondary_lpi_test(void) +{ + setup_irq(lpi_handler); + cpumask_set_cpu(smp_processor_id(), &ready); + while (1) + wfi(); +} + static struct gic gicv2 = { .ipi = { .send_self = gicv2_ipi_send_self, @@ -551,6 +608,120 @@ static void test_its_baser(void) report_info("collection baser entry_size = 0x%x", coll_baser->esz); } +static int its_prerequisites(int nb_cpus) +{ + int cpu; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return -1; + } + + if (nr_cpus < 4) { + report_skip("Test requires at least %d vcpus", nb_cpus); + return -1; + } + + stats_reset(); + + setup_irq(lpi_handler); + + for_each_present_cpu(cpu) { + if (cpu == 0) + continue; + smp_boot_secondary(cpu, secondary_lpi_test); + } + wait_on_ready(); + + its_enable_defaults(); + + lpi_stats_expect(-1, -1); + check_lpi_stats(); + + return 0; +} + +static void test_its_trigger(void) +{ + struct its_collection *col3, *col2; + struct its_device *dev2, *dev7; + + if (its_prerequisites(4)) + return; + + dev2 = its_create_device(2 /* dev id */, 8 /* nb_ites */); + dev7 = its_create_device(7 /* dev id */, 8 /* nb_ites */); + + col3 = its_create_collection(3 /* col id */, 3/* target PE */); + col2 = its_create_collection(2 /* col id */, 2/* target PE */); + + set_lpi_config(8195, LPI_PROP_DEFAULT); + set_lpi_config(8196, LPI_PROP_DEFAULT); + + its_send_invall(col2); + its_send_invall(col3); + + report_prefix_push("int"); + + its_send_mapd(dev2, true); + its_send_mapd(dev7, true); + + its_send_mapc(col3, true); + its_send_mapc(col2, true); + + its_send_mapti(dev2, 8195 /* lpi id */, + 20 /* event id */, col3); + its_send_mapti(dev7, 8196 /* lpi id */, + 255 /* event id */, col2); + + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats(); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats(); + + report_prefix_pop(); + + report_prefix_push("inv/invall"); + + /* disable 8195 */ + set_lpi_config(8195, LPI_PROP_DEFAULT & ~0x1); + its_send_inv(dev2, 20); + + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats(); + + set_lpi_config(8195, LPI_PROP_DEFAULT); + /* willingly forget the INVALL*/ + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats(); + + its_send_invall(col3); + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats(); + + report_prefix_pop(); + + report_prefix_push("mapd valid=false"); + its_send_mapd(dev2, false); + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats(); + report_prefix_pop(); + + report_prefix_push("mapc valid=false"); + its_send_mapc(col2, false); + lpi_stats_expect(-1, -1); + its_send_int(dev7, 255); + check_lpi_stats(); +} + + int main(int argc, char **argv) { if (!gic_init()) { @@ -581,6 +752,9 @@ int main(int argc, char **argv) } else if (strcmp(argv[1], "mmio") == 0) { report_prefix_push(argv[1]); gic_test_mmio(); + } else if (!strcmp(argv[1], "its-trigger")) { + report_prefix_push(argv[1]); + test_its_trigger(); report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") == 0) { report_prefix_push(argv[1]); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 2234a0f..80a1d27 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -134,6 +134,12 @@ smp = $MAX_SMP extra_params = -machine gic-version=3 -append 'its-baser' groups = its +[its-trigger] +file = gic.flat +smp = $MAX_SMP +extra_params = -machine gic-version=3 -append 'its-trigger' +groups = its + # Test PSCI emulation [psci] file = psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 463174f..7d6f8fd 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -123,6 +123,16 @@ struct its_data { u32 nr_collections; /* Allocated Collections */ }; +struct its_event { + int cpu_id; + int lpi_id; +}; + +struct its_stats { + struct its_event expected; + struct its_event observed; +}; + extern struct its_data its_data; #define gicv3_its_base() (its_data.base) @@ -139,6 +149,10 @@ extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set); extern void its_enable_defaults(void); extern struct its_device *its_create_device(u32 dev_id, int nr_ites); extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe); +extern struct its_collection *its_create_collection(u32 col_id, u32 target); + +extern void set_lpi_config(int n, u8 val); +extern u8 get_lpi_config(int n); extern void its_send_mapd(struct its_device *dev, int valid); extern void its_send_mapc(struct its_collection *col, int valid); From patchwork Fri Jan 10 14:54:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327569 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 27119921 for ; Fri, 10 Jan 2020 14:55:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 05C8020842 for ; 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Fri, 10 Jan 2020 09:55:31 -0500 X-MC-Unique: deHWbyOWMj6ZZi6hu3Q_TA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C366B10883B3; Fri, 10 Jan 2020 14:55:28 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 391467BA5F; Fri, 10 Jan 2020 14:55:23 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 14/16] arm/run: Allow Migration tests Date: Fri, 10 Jan 2020 15:54:10 +0100 Message-Id: <20200110145412.14937-15-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Let's link getchar.o to use puts and getchar from the tests. Then allow tests belonging to the migration group to trigger the migration from the test code by putting "migrate" into the uart. Then the code can wait for the migration completion by using getchar(). The __getchar implement is minimalist as it just reads the data register. It is just meant to read the single character emitted at the end of the migration by the runner script. It is not meant to read more data (FIFOs are not enabled). Signed-off-by: Eric Auger Reviewed-by: Thomas Huth --- arm/Makefile.common | 2 +- arm/run | 2 +- lib/arm/io.c | 13 +++++++++++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arm/Makefile.common b/arm/Makefile.common index 7cc0f04..327f112 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -32,7 +32,7 @@ CFLAGS += -I $(SRCDIR)/lib -I $(SRCDIR)/lib/libfdt -I lib asm-offsets = lib/$(ARCH)/asm-offsets.h include $(SRCDIR)/scripts/asm-offsets.mak -cflatobjs += lib/util.o +cflatobjs += lib/util.o lib/getchar.o cflatobjs += lib/alloc_phys.o cflatobjs += lib/alloc_page.o cflatobjs += lib/vmalloc.o diff --git a/arm/run b/arm/run index 277db9b..a390ca5 100755 --- a/arm/run +++ b/arm/run @@ -61,6 +61,6 @@ fi M+=",accel=$ACCEL" command="$qemu -nodefaults $M -cpu $processor $chr_testdev $pci_testdev" command+=" -display none -serial stdio -kernel" -command="$(timeout_cmd) $command" +command="$(migration_cmd) $(timeout_cmd) $command" run_qemu $command "$@" diff --git a/lib/arm/io.c b/lib/arm/io.c index 99fd315..ed89e19 100644 --- a/lib/arm/io.c +++ b/lib/arm/io.c @@ -87,6 +87,19 @@ void puts(const char *s) spin_unlock(&uart_lock); } +/* + * Minimalist implementation for migration completion detection. + * Needs to be improved for more advanced Rx cases + */ +int __getchar(void) +{ + int ret; + + ret = readb(uart0_base); + if (!ret) + return -1; + return ret; +} /* * Defining halt to take 'code' as an argument guarantees that it will From patchwork Fri Jan 10 14:54:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327573 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F20796C1 for ; Fri, 10 Jan 2020 14:55:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D0C9D20842 for ; Fri, 10 Jan 2020 14:55:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="BvjzlCAV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728473AbgAJOzg (ORCPT ); Fri, 10 Jan 2020 09:55:36 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:49168 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728445AbgAJOzg (ORCPT ); Fri, 10 Jan 2020 09:55:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578668134; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zF7fowIzQfdh49LNbLzBDFVCiRf9n/Gerf/OzX8S1GQ=; b=BvjzlCAVd7IkjGHvlp0qLwRmHmCYO/dKNDS9VKh+kgAV8keb0FirOc061+P7k86LLQ90qv 4HAuPp/xHsTkA9DkDR4WccB2sE40tzwDvEjSiujNCMTKM/zB0lq0xbed2Qzq6GuURtptp1 CO0fdKG3QPvFdr/ElvgRovvdU8QoCiQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-26-wpRgzfHKM1yF0u2giuJ9zg-1; Fri, 10 Jan 2020 09:55:33 -0500 X-MC-Unique: wpRgzfHKM1yF0u2giuJ9zg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 092E11083E84; Fri, 10 Jan 2020 14:55:32 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 22B837C3EB; Fri, 10 Jan 2020 14:55:28 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 15/16] arm/arm64: ITS: migration tests Date: Fri, 10 Jan 2020 15:54:11 +0100 Message-Id: <20200110145412.14937-16-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This test maps LPIs (populates the device table, the collection table, interrupt translation tables, configuration table), migrates and make sure the translation is correct on the destination. Signed-off-by: Eric Auger --- arm/gic.c | 55 +++++++++++++++++++++++++++++++++++++--- arm/unittests.cfg | 7 +++++ lib/arm/asm/gic-v3-its.h | 2 ++ lib/arm/gic-v3-its.c | 22 ++++++++++++++++ 4 files changed, 82 insertions(+), 4 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 7f701a1..bf4b5ba 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -641,13 +641,19 @@ static int its_prerequisites(int nb_cpus) return 0; } -static void test_its_trigger(void) +/* + * Setup the configuration for those mappings: + * dev_id=2 event=20 -> vcpu 3, intid=8195 + * dev_id=7 event=255 -> vcpu 2, intid=8196 + * LPIs ready to hit + */ +static int its_setup1(void) { struct its_collection *col3, *col2; struct its_device *dev2, *dev7; if (its_prerequisites(4)) - return; + return -1; dev2 = its_create_device(2 /* dev id */, 8 /* nb_ites */); dev7 = its_create_device(7 /* dev id */, 8 /* nb_ites */); @@ -661,8 +667,6 @@ static void test_its_trigger(void) its_send_invall(col2); its_send_invall(col3); - report_prefix_push("int"); - its_send_mapd(dev2, true); its_send_mapd(dev7, true); @@ -673,6 +677,23 @@ static void test_its_trigger(void) 20 /* event id */, col3); its_send_mapti(dev7, 8196 /* lpi id */, 255 /* event id */, col2); + return 0; +} + +static void test_its_trigger(void) +{ + struct its_collection *col3, *col2; + struct its_device *dev2, *dev7; + + if (its_setup1()) + return; + + col3 = its_get_collection(3); + col2 = its_get_collection(2); + dev2 = its_get_device(2); + dev7 = its_get_device(7); + + report_prefix_push("int"); lpi_stats_expect(3, 8195); its_send_int(dev2, 20); @@ -721,6 +742,28 @@ static void test_its_trigger(void) check_lpi_stats(); } +static void test_its_migration(void) +{ + struct its_device *dev2, *dev7; + + if (its_setup1()) + return; + + dev2 = its_get_device(2); + dev7 = its_get_device(7); + + puts("Now migrate the VM, then press a key to continue...\n"); + (void)getchar(); + report(true, "Migration complete"); + + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats(); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats(); +} int main(int argc, char **argv) { @@ -756,6 +799,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); test_its_trigger(); report_prefix_pop(); + } else if (!strcmp(argv[1], "its-migration")) { + report_prefix_push(argv[1]); + test_its_migration(); + report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") == 0) { report_prefix_push(argv[1]); test_its_introspection(); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 80a1d27..29e2efc 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -140,6 +140,13 @@ smp = $MAX_SMP extra_params = -machine gic-version=3 -append 'its-trigger' groups = its +[its-migration] +file = gic.flat +smp = $MAX_SMP +accel = kvm +extra_params = -machine gic-version=3 -append 'its-migration' +groups = its migration + # Test PSCI emulation [psci] file = psci.flat diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h index 7d6f8fd..7838a11 100644 --- a/lib/arm/asm/gic-v3-its.h +++ b/lib/arm/asm/gic-v3-its.h @@ -166,6 +166,8 @@ extern void its_send_invall(struct its_collection *col); extern void its_send_movi(struct its_device *dev, struct its_collection *col, u32 id); extern void its_send_sync(struct its_collection *col); +extern struct its_device *its_get_device(u32 id); +extern struct its_collection *its_get_collection(u32 id); #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 88c08ee..315aedb 100644 --- a/lib/arm/gic-v3-its.c +++ b/lib/arm/gic-v3-its.c @@ -303,3 +303,25 @@ struct its_collection *its_create_collection(u32 col_id, u32 pe) its_data.nr_collections++; return new; } + +struct its_device *its_get_device(u32 id) +{ + int i; + + for (i = 0; i < GITS_MAX_DEVICES; i++) { + if (its_data.devices[i].device_id == id) + return &its_data.devices[i]; + } + return NULL; +} + +struct its_collection *its_get_collection(u32 id) +{ + int i; + + for (i = 0; i < GITS_MAX_COLLECTIONS; i++) { + if (its_data.collections[i].col_id == id) + return &its_data.collections[i]; + } + return NULL; +} From patchwork Fri Jan 10 14:54:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11327575 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7BE36C1 for ; Fri, 10 Jan 2020 14:55:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BA6CE20842 for ; Fri, 10 Jan 2020 14:55:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="JW1RDjmp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728475AbgAJOzk (ORCPT ); Fri, 10 Jan 2020 09:55:40 -0500 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:43375 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728458AbgAJOzk (ORCPT ); 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Fri, 10 Jan 2020 14:55:35 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-108.ams2.redhat.com [10.36.117.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 615E67C3EB; Fri, 10 Jan 2020 14:55:32 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v2 16/16] arm/arm64: ITS: pending table migration test Date: Fri, 10 Jan 2020 15:54:12 +0100 Message-Id: <20200110145412.14937-17-eric.auger@redhat.com> In-Reply-To: <20200110145412.14937-1-eric.auger@redhat.com> References: <20200110145412.14937-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add two new migration tests. One testing the migration of a topology where collection were unmapped. The second test checks the migration of the pending table. Signed-off-by: Eric Auger --- arm/gic.c | 148 ++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 16 ++++- 2 files changed, 163 insertions(+), 1 deletion(-) diff --git a/arm/gic.c b/arm/gic.c index bf4b5ba..cb976c3 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -170,6 +170,7 @@ static void lpi_handler(struct pt_regs *regs __unused) smp_rmb(); /* pairs with wmb in lpi_stats_expect */ lpi_stats.observed.cpu_id = smp_processor_id(); lpi_stats.observed.lpi_id = irqnr; + acked[lpi_stats.observed.cpu_id]++; smp_wmb(); /* pairs with rmb in check_lpi_stats */ } @@ -207,6 +208,18 @@ static void check_lpi_stats(void) } } +static void check_lpi_hits(int *expected) +{ + int i; + + for (i = 0; i < nr_cpus; i++) { + if (acked[i] != expected[i]) + report(false, "expected %d LPIs on PE #%d, %d observed", + expected[i], i, acked[i]); + } + report(true, "check LPI on all vcpus"); +} + static void gicv2_ipi_send_self(void) { writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); @@ -641,6 +654,18 @@ static int its_prerequisites(int nb_cpus) return 0; } +static void set_lpi(struct its_device *dev, u32 eventid, u32 physid, + struct its_collection *col) +{ + if (!dev || !col) + report_abort("wrong device or collection"); + + its_send_mapti(dev, physid, eventid, col); + + set_lpi_config(physid, LPI_PROP_DEFAULT); + its_send_invall(col); +} + /* * Setup the configuration for those mappings: * dev_id=2 event=20 -> vcpu 3, intid=8195 @@ -765,6 +790,121 @@ static void test_its_migration(void) check_lpi_stats(); } +static void test_migrate_unmapped_collection(void) +{ + struct its_collection *col; + struct its_device *dev2, *dev7; + u8 config; + + if (its_setup1()) + return; + + col = its_create_collection(nr_cpus - 1, nr_cpus - 1); + dev2 = its_get_device(2); + dev7 = its_get_device(7); + + /* MAPTI with the collection unmapped */ + set_lpi(dev2, 0, 8192, col); + + puts("Now migrate the VM, then press a key to continue...\n"); + (void)getchar(); + report(true, "Migration complete"); + + /* on the destination, map the collection */ + its_send_mapc(col, true); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats(); + + config = get_lpi_config(8192); + report(config == LPI_PROP_DEFAULT, + "Config of LPI 8192 was properly migrated"); + + lpi_stats_expect(nr_cpus - 1, 8192); + its_send_int(dev2, 0); + check_lpi_stats(); + + /* unmap the collection */ + its_send_mapc(col, false); + + lpi_stats_expect(-1, -1); + its_send_int(dev2, 0); + check_lpi_stats(); + + /* remap event 0 onto lpiid 8193 */ + set_lpi(dev2, 0, 8193, col); + lpi_stats_expect(-1, -1); + its_send_int(dev2, 0); + check_lpi_stats(); + + /* remap the collection */ + its_send_mapc(col, true); + lpi_stats_expect(nr_cpus - 1, 8193); +} + +static void test_its_pending_migration(void) +{ + struct its_device *dev; + struct its_collection *collection[2]; + int expected[NR_CPUS]; + u64 pendbaser; + void *ptr; + int i; + + if (its_prerequisites(4)) + return; + + dev = its_create_device(2 /* dev id */, 8 /* nb_ites */); + its_send_mapd(dev, true); + + collection[0] = its_create_collection(nr_cpus - 1, nr_cpus - 1); + collection[1] = its_create_collection(nr_cpus - 2, nr_cpus - 2); + its_send_mapc(collection[0], true); + its_send_mapc(collection[1], true); + + /* disable lpi at redist level */ + gicv3_rdist_ctrl_lpi(nr_cpus - 1, false); + gicv3_rdist_ctrl_lpi(nr_cpus - 2, false); + + /* even lpis are assigned to even cpu */ + for (i = 0; i < 256; i++) { + struct its_collection *col = i % 2 ? collection[0] : + collection[1]; + int vcpu = col->target_address >> 16; + + its_send_mapti(dev, 8192 + i, i, col); + set_lpi_config(8192 + i, LPI_PROP_DEFAULT); + set_pending_table_bit(vcpu, 8192 + i, true); + } + its_send_invall(collection[0]); + its_send_invall(collection[1]); + + /* Set the PTZ bit on each pendbaser */ + + expected[nr_cpus - 1] = 128; + expected[nr_cpus - 2] = 128; + + ptr = gicv3_data.redist_base[nr_cpus - 1] + GICR_PENDBASER; + pendbaser = readq(ptr); + writeq(pendbaser & ~GICR_PENDBASER_PTZ, ptr); + + ptr = gicv3_data.redist_base[nr_cpus - 2] + GICR_PENDBASER; + pendbaser = readq(ptr); + writeq(pendbaser & ~GICR_PENDBASER_PTZ, ptr); + + gicv3_rdist_ctrl_lpi(nr_cpus - 1, true); + gicv3_rdist_ctrl_lpi(nr_cpus - 2, true); + + puts("Now migrate the VM, then press a key to continue...\n"); + (void)getchar(); + report(true, "Migration complete"); + + mdelay(1000); + + check_lpi_hits(expected); +} + int main(int argc, char **argv) { if (!gic_init()) { @@ -803,6 +943,14 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); test_its_migration(); report_prefix_pop(); + } else if (!strcmp(argv[1], "its-pending-migration")) { + report_prefix_push(argv[1]); + test_its_pending_migration(); + report_prefix_pop(); + } else if (!strcmp(argv[1], "its-migrate-unmapped-collection")) { + report_prefix_push(argv[1]); + test_migrate_unmapped_collection(); + report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") == 0) { report_prefix_push(argv[1]); test_its_introspection(); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 29e2efc..911f0b7 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -145,7 +145,21 @@ file = gic.flat smp = $MAX_SMP accel = kvm extra_params = -machine gic-version=3 -append 'its-migration' -groups = its migration +groups = migration + +[its-pending-migration] +file = gic.flat +smp = $MAX_SMP +accel = kvm +extra_params = -machine gic-version=3 -append 'its-pending-migration' +groups = migration + +[its-migrate-unmapped-collection] +file = gic.flat +smp = $MAX_SMP +accel = kvm +extra_params = -machine gic-version=3 -append 'its-migrate-unmapped-collection' +groups = migration # Test PSCI emulation [psci]