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spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1ipwmA-0008VV-QW; Fri, 10 Jan 2020 16:04:42 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1ipwm8-0008V2-Nw for xen-devel@lists.xenproject.org; Fri, 10 Jan 2020 16:04:40 +0000 X-Inumbo-ID: e149b272-33c2-11ea-ac27-bc764e2007e4 Received: from esa6.hc3370-68.iphmx.com (unknown [216.71.155.175]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id e149b272-33c2-11ea-ac27-bc764e2007e4; Fri, 10 Jan 2020 16:04:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1578672268; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=odR4T7FdyMjtoMTFg7NqDhU7Y+0hx1R2vtuLmii667A=; b=VA9PIlOBFaV0Eh4FLtK+MwRLlIC5mHz79x6s6sE3wVGwr6ZG9d2lspkh PUhJf/StlvmCc1FRiCHW0X3pYR/3YVeEEwGiE5p6NdXOJaVSPLyJ6+4io k8VAZnuz97ZB82+psMDSM+/bKpowl47B0pLKkk7Lp9B6Eq4VYukHb7Tuu M=; Authentication-Results: esa6.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none; spf=None smtp.pra=roger.pau@citrix.com; spf=Pass smtp.mailfrom=roger.pau@citrix.com; spf=None smtp.helo=postmaster@mail.citrix.com Received-SPF: None (esa6.hc3370-68.iphmx.com: no sender authenticity information available from domain of roger.pau@citrix.com) identity=pra; client-ip=162.221.158.21; receiver=esa6.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="roger.pau@citrix.com"; x-conformance=sidf_compatible Received-SPF: Pass (esa6.hc3370-68.iphmx.com: domain of roger.pau@citrix.com designates 162.221.158.21 as permitted sender) identity=mailfrom; client-ip=162.221.158.21; receiver=esa6.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="roger.pau@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ip4:168.245.78.127 ~all" Received-SPF: None (esa6.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa6.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: JGMoYIdgPrgc0P5P+OJOW5EvTjhm9zcc15ZBYKBDI837paWXkPEMTWlJTngcH9BUCgk9AmYby7 e/rPaYG0WoF7OJmtls47gPPmiFB0h9LCXcSWsRxclKZopoySyvIVUIRjMvZ8ktus1uQg8Vqnbp iFQPdbDmf2126T+zB1gBxzUUmBH1Rww0v31YxgBsqH6u6AVTuLTbYRymbKnzMmzn/pUcbN+qZB H3n1U5GHwrWmE6YXILGiJ9CSXeVE19UVMEeXdGOTIEkqN9icE/s9u4zLYUgBCX2uUsxoBLqyvZ 8YM= X-SBRS: 2.7 X-MesageID: 11183715 X-Ironport-Server: esa6.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,417,1571716800"; d="scan'208";a="11183715" From: Roger Pau Monne To: Date: Fri, 10 Jan 2020 17:04:02 +0100 Message-ID: <20200110160404.15573-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200110160404.15573-1-roger.pau@citrix.com> References: <20200110160404.15573-1-roger.pau@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v2 1/3] x86/hvm: allow ASID flush when v != current X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , Roger Pau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Current implementation of hvm_asid_flush_vcpu is not safe to use unless the target vCPU is either paused or the currently running one, as it modifies the generation without any locking. Fix this by using atomic operations when accessing the generation field, both in hvm_asid_flush_vcpu_asid and other ASID functions. This allows to safely flush the current ASID generation. Note that for the flush to take effect if the vCPU is currently running a vmexit is required. Note the same could be achieved by introducing an extra field to hvm_vcpu_asid that signals hvm_asid_handle_vmenter the need to call hvm_asid_flush_vcpu on the given vCPU before vmentry, this however seems unnecessary as hvm_asid_flush_vcpu itself only sets two vCPU fields to 0, so there's no need to delay this to the vmentry ASID helper. This is not a bugfix as no callers that would violate the assumptions listed in the first paragraph have been found, but a preparatory change in order to allow remote flushing of HVM vCPUs. Signed-off-by: Roger Pau Monné --- xen/arch/x86/hvm/asid.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/hvm/asid.c b/xen/arch/x86/hvm/asid.c index 9d3c671a5f..80b73da89b 100644 --- a/xen/arch/x86/hvm/asid.c +++ b/xen/arch/x86/hvm/asid.c @@ -82,7 +82,7 @@ void hvm_asid_init(int nasids) void hvm_asid_flush_vcpu_asid(struct hvm_vcpu_asid *asid) { - asid->generation = 0; + write_atomic(&asid->generation, 0); } void hvm_asid_flush_vcpu(struct vcpu *v) @@ -120,7 +120,7 @@ bool_t hvm_asid_handle_vmenter(struct hvm_vcpu_asid *asid) goto disabled; /* Test if VCPU has valid ASID. */ - if ( asid->generation == data->core_asid_generation ) + if ( read_atomic(&asid->generation) == data->core_asid_generation ) return 0; /* If there are no free ASIDs, need to go to a new generation */ @@ -134,7 +134,7 @@ bool_t hvm_asid_handle_vmenter(struct hvm_vcpu_asid *asid) /* Now guaranteed to be a free ASID. */ asid->asid = data->next_asid++; - asid->generation = data->core_asid_generation; + write_atomic(&asid->generation, data->core_asid_generation); /* * When we assign ASID 1, flush all TLB entries as we are starting a new From patchwork Fri Jan 10 16:04:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 11327807 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4018E109A for ; Fri, 10 Jan 2020 16:05:54 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D47320848 for ; Fri, 10 Jan 2020 16:05:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=citrix.com header.i=@citrix.com header.b="A6bO+Yij" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1D47320848 Authentication-Results: mail.kernel.org; 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x-sender="roger.pau@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ip4:168.245.78.127 ~all" Received-SPF: None (esa2.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa2.hc3370-68.iphmx.com; envelope-from="roger.pau@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: WmDL46PVUoig6h4e32hSapGFRT2gaFR+FJglJu1iIP63NJt14MG61ZclX4w+2HruI6MwYGN7u/ f98pqjcI/0HwzixxKT0AvGIVAZOZ8rq8pRJKMRBSj2Cke8B4goam8YZGuH3VdoyX2LTSIHFQiE b/L3pzeHTnBgYemeMk/D3HNHF1OXG+Bv5w/7DjcelZXu6sbsluzhBSV0DrC8A5PxATUr/DEhjU vZVPSGLzgmPoPObiptLAe6F5/g4H4P8icwVjdcnZ0q4bizxmWjxyrdCP2XjwdwoNC/6HPo/b/b ePA= X-SBRS: 2.7 X-MesageID: 10766849 X-Ironport-Server: esa2.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,417,1571716800"; d="scan'208";a="10766849" From: Roger Pau Monne To: Date: Fri, 10 Jan 2020 17:04:03 +0100 Message-ID: <20200110160404.15573-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200110160404.15573-1-roger.pau@citrix.com> References: <20200110160404.15573-1-roger.pau@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v2 2/3] x86/hvm: rework HVMOP_flush_tlbs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Paul Durrant , Wei Liu , Jan Beulich , Roger Pau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Current implementation of hvm_flush_vcpu_tlb is highly inefficient. First of all the call to flush_tlb_mask is completely useless when trying to flush the TLB of HVM guests, as this TLB flush is executed in root mode, and hence doesn't flush any guest state cache. Secondly, calling paging_update_cr3 albeit correct, is much more expensive than strictly required. Instead a TLB flush can be achieved by calling hvm_asid_flush_vcpu on each pCPU that has a domain vCPU state currently loaded. This call will invalidate the current non-root context, thus forcing a clean cache state on vmentry. If the guest is not using ASIDs, the vmexit caused by the on_selected_cpus IPI will already force a TLB flush. Signed-off-by: Roger Pau Monné --- xen/arch/x86/hvm/hvm.c | 54 ++++++++++++---------------- xen/arch/x86/hvm/viridian/viridian.c | 7 +--- xen/include/asm-x86/hvm/hvm.h | 2 +- 3 files changed, 25 insertions(+), 38 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4723f5d09c..e4fef0afcd 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3973,7 +3973,21 @@ static void hvm_s3_resume(struct domain *d) } } -bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v), +static void do_flush(void *data) +{ + cpumask_t *mask = data; + unsigned int cpu = smp_processor_id(); + + ASSERT(cpumask_test_cpu(cpu, mask)); + /* + * A vmexit/vmenter (caused by the IPI issued to execute this function) is + * enough to force a TLB flush since we have already ticked the vCPU ASID + * prior to issuing the IPI. + */ + cpumask_clear_cpu(cpu, mask); +} + +void hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v), void *ctxt) { static DEFINE_PER_CPU(cpumask_t, flush_cpumask); @@ -3981,27 +3995,8 @@ bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v), struct domain *d = current->domain; struct vcpu *v; - /* Avoid deadlock if more than one vcpu tries this at the same time. */ - if ( !spin_trylock(&d->hypercall_deadlock_mutex) ) - return false; - - /* Pause all other vcpus. */ - for_each_vcpu ( d, v ) - if ( v != current && flush_vcpu(ctxt, v) ) - vcpu_pause_nosync(v); - - /* Now that all VCPUs are signalled to deschedule, we wait... */ - for_each_vcpu ( d, v ) - if ( v != current && flush_vcpu(ctxt, v) ) - while ( !vcpu_runnable(v) && v->is_running ) - cpu_relax(); - - /* All other vcpus are paused, safe to unlock now. */ - spin_unlock(&d->hypercall_deadlock_mutex); - cpumask_clear(mask); - /* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */ for_each_vcpu ( d, v ) { unsigned int cpu; @@ -4009,22 +4004,17 @@ bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v), if ( !flush_vcpu(ctxt, v) ) continue; - paging_update_cr3(v, false); + hvm_asid_flush_vcpu(v); cpu = read_atomic(&v->dirty_cpu); - if ( is_vcpu_dirty_cpu(cpu) ) + if ( cpu != smp_processor_id() && is_vcpu_dirty_cpu(cpu) ) __cpumask_set_cpu(cpu, mask); } - /* Flush TLBs on all CPUs with dirty vcpu state. */ - flush_tlb_mask(mask); + on_selected_cpus(mask, do_flush, mask, 0); - /* Done. */ - for_each_vcpu ( d, v ) - if ( v != current && flush_vcpu(ctxt, v) ) - vcpu_unpause(v); - - return true; + while ( !cpumask_empty(mask) ) + cpu_relax(); } static bool always_flush(void *ctxt, struct vcpu *v) @@ -4037,7 +4027,9 @@ static int hvmop_flush_tlb_all(void) if ( !is_hvm_domain(current->domain) ) return -EINVAL; - return hvm_flush_vcpu_tlb(always_flush, NULL) ? 0 : -ERESTART; + hvm_flush_vcpu_tlb(always_flush, NULL); + + return 0; } static int hvmop_set_evtchn_upcall_vector( diff --git a/xen/arch/x86/hvm/viridian/viridian.c b/xen/arch/x86/hvm/viridian/viridian.c index 44c8e6cac6..ec73361597 100644 --- a/xen/arch/x86/hvm/viridian/viridian.c +++ b/xen/arch/x86/hvm/viridian/viridian.c @@ -604,12 +604,7 @@ int viridian_hypercall(struct cpu_user_regs *regs) if ( input_params.flags & HV_FLUSH_ALL_PROCESSORS ) input_params.vcpu_mask = ~0ul; - /* - * A false return means that another vcpu is currently trying - * a similar operation, so back off. - */ - if ( !hvm_flush_vcpu_tlb(need_flush, &input_params.vcpu_mask) ) - return HVM_HCALL_preempted; + hvm_flush_vcpu_tlb(need_flush, &input_params.vcpu_mask); output.rep_complete = input.rep_count; diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h index 09793c12e9..1f70ee0823 100644 --- a/xen/include/asm-x86/hvm/hvm.h +++ b/xen/include/asm-x86/hvm/hvm.h @@ -333,7 +333,7 @@ const char *hvm_efer_valid(const struct vcpu *v, uint64_t value, signed int cr0_pg); unsigned long hvm_cr4_guest_valid_bits(const struct domain *d, bool restore); -bool hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v), +void hvm_flush_vcpu_tlb(bool (*flush_vcpu)(void *ctxt, struct vcpu *v), void *ctxt); #ifdef CONFIG_HVM From patchwork Fri Jan 10 16:04:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 11327803 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1144192A for ; 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x-conformance=sidf_compatible IronPort-SDR: w7RoXuVrBZXc2YFnqn8ZI0/rjEGB/aWaX6YqivnJRgVoHFNiwhLaeOBYcQyLJjRKAaIQhaIcWo /vrUlbIHG+sde9QXHXoh7AuTHqEzZdosE4WmFaMQbx0YNPaavhHxddbs1zX6LJd+0yb3aVC1yH vsSnUrHGE0X8qWdqxikHNGgvOnQScVO111YR9Vfepm5mZkKNk+O//aL/DKa6gyefY3x9KfO5uA mtpmNgbKy3PyyWMlCFlbnUKjDhLc2Et4Am8brncTEQ5Mj29n6IKWS490PIbqbxSzxVU0Nv8PZv tvM= X-SBRS: 2.7 X-MesageID: 10736127 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.69,417,1571716800"; d="scan'208";a="10736127" From: Roger Pau Monne To: Date: Fri, 10 Jan 2020 17:04:04 +0100 Message-ID: <20200110160404.15573-4-roger.pau@citrix.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200110160404.15573-1-roger.pau@citrix.com> References: <20200110160404.15573-1-roger.pau@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v2 3/3] x86/tlb: use Xen L0 assisted TLB flush when available X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , Roger Pau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Use Xen's L0 HVMOP_flush_tlbs hypercall in order to perform flushes. This greatly increases the performance of TLB flushes when running with a high amount of vCPUs as a Xen guest, and is specially important when running in shim mode. The following figures are from a PV guest running `make -j32 xen` in shim mode with 32 vCPUs. Using x2APIC and ALLBUT shorthand: real 4m35.973s user 4m35.110s sys 36m24.117s Using L0 assisted flush: real 1m14.206s user 4m31.835s sys 5m45.013s The implementation adds a new hook to hypervisor_ops so other enlightenments can also implement such assisted flush just by filling the hook. Note that the Xen implementation completely ignores the dirty CPU mask and the linear address passed in, and always performs a global TLB flush on all vCPUs. Signed-off-by: Roger Pau Monné --- Changes since v1: - Add a L0 assisted hook to hypervisor ops. --- xen/arch/x86/guest/hypervisor.c | 9 +++++++++ xen/arch/x86/guest/xen/xen.c | 6 ++++++ xen/arch/x86/smp.c | 6 ++++++ xen/include/asm-x86/guest/hypervisor.h | 13 +++++++++++++ 4 files changed, 34 insertions(+) diff --git a/xen/arch/x86/guest/hypervisor.c b/xen/arch/x86/guest/hypervisor.c index 4f27b98740..c793ba51c2 100644 --- a/xen/arch/x86/guest/hypervisor.c +++ b/xen/arch/x86/guest/hypervisor.c @@ -18,6 +18,7 @@ * * Copyright (c) 2019 Microsoft. */ +#include #include #include @@ -64,6 +65,14 @@ void hypervisor_resume(void) ops->resume(); } +int hypervisor_flush_tlb(const cpumask_t *mask, const void *va) +{ + if ( ops && ops->flush_tlb ) + return ops->flush_tlb(mask, va); + + return -ENOSYS; +} + /* * Local variables: * mode: C diff --git a/xen/arch/x86/guest/xen/xen.c b/xen/arch/x86/guest/xen/xen.c index 6dbc5f953f..47af773aca 100644 --- a/xen/arch/x86/guest/xen/xen.c +++ b/xen/arch/x86/guest/xen/xen.c @@ -310,11 +310,17 @@ static void resume(void) pv_console_init(); } +static int flush_tlb(const cpumask_t *mask, const void *va) +{ + return xen_hypercall_hvm_op(HVMOP_flush_tlbs, NULL); +} + static const struct hypervisor_ops ops = { .name = "Xen", .setup = setup, .ap_setup = ap_setup, .resume = resume, + .flush_tlb = flush_tlb, }; const struct hypervisor_ops *__init xg_probe(void) diff --git a/xen/arch/x86/smp.c b/xen/arch/x86/smp.c index 6510dd84ab..b3cb1ba90f 100644 --- a/xen/arch/x86/smp.c +++ b/xen/arch/x86/smp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -262,6 +263,11 @@ void flush_area_mask(const cpumask_t *mask, const void *va, unsigned int flags) if ( (flags & ~FLUSH_ORDER_MASK) && !cpumask_subset(mask, cpumask_of(cpu)) ) { + if ( cpu_has_hypervisor && + !(flags & ~(FLUSH_TLB | FLUSH_TLB_GLOBAL | FLUSH_VA_VALID)) && + !hypervisor_flush_tlb(mask, va) ) + return; + spin_lock(&flush_lock); cpumask_and(&flush_cpumask, mask, &cpu_online_map); cpumask_clear_cpu(cpu, &flush_cpumask); diff --git a/xen/include/asm-x86/guest/hypervisor.h b/xen/include/asm-x86/guest/hypervisor.h index 392f4b90ae..b7f1969796 100644 --- a/xen/include/asm-x86/guest/hypervisor.h +++ b/xen/include/asm-x86/guest/hypervisor.h @@ -28,6 +28,8 @@ struct hypervisor_ops { void (*ap_setup)(void); /* Resume from suspension */ void (*resume)(void); + /* L0 assisted TLB flush */ + int (*flush_tlb)(const cpumask_t *mask, const void *va); }; #ifdef CONFIG_GUEST @@ -36,9 +38,16 @@ const char *hypervisor_probe(void); void hypervisor_setup(void); void hypervisor_ap_setup(void); void hypervisor_resume(void); +/* + * L0 assisted TLB flush. + * mask: cpumask of the dirty vCPUs that should be flushed. + * va: linear address to flush, or NULL for global flushes. + */ +int hypervisor_flush_tlb(const cpumask_t *mask, const void *va); #else +#include #include #include @@ -46,6 +55,10 @@ static inline const char *hypervisor_probe(void) { return NULL; } static inline void hypervisor_setup(void) { ASSERT_UNREACHABLE(); } static inline void hypervisor_ap_setup(void) { ASSERT_UNREACHABLE(); } static inline void hypervisor_resume(void) { ASSERT_UNREACHABLE(); } +static inline int hypervisor_flush_tlb(const cpumask_t *mask, const void *va) +{ + return -ENOSYS; +} #endif /* CONFIG_GUEST */