From patchwork Sun Jan 12 08:14:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329069 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A9506930 for ; Sun, 12 Jan 2020 08:20:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8759D214D8 for ; Sun, 12 Jan 2020 08:20:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="m07jpV3w" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732425AbgALIUr (ORCPT ); Sun, 12 Jan 2020 03:20:47 -0500 Received: from forward100j.mail.yandex.net ([5.45.198.240]:58038 "EHLO forward100j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732369AbgALIUq (ORCPT ); Sun, 12 Jan 2020 03:20:46 -0500 Received: from forward103q.mail.yandex.net (forward103q.mail.yandex.net [IPv6:2a02:6b8:c0e:50:0:640:b21c:d009]) by forward100j.mail.yandex.net (Yandex) with ESMTP id C778150E0222; Sun, 12 Jan 2020 11:14:39 +0300 (MSK) Received: from mxback5q.mail.yandex.net (mxback5q.mail.yandex.net [IPv6:2a02:6b8:c0e:1ba:0:640:b716:ad89]) by forward103q.mail.yandex.net (Yandex) with ESMTP id BE52261E0005; Sun, 12 Jan 2020 11:14:39 +0300 (MSK) Received: from vla1-ee05250d997a.qloud-c.yandex.net (vla1-ee05250d997a.qloud-c.yandex.net [2a02:6b8:c0d:3495:0:640:ee05:250d]) by mxback5q.mail.yandex.net (mxback/Yandex) with ESMTP id tR0KhGblhy-EdcCaSf8; Sun, 12 Jan 2020 11:14:39 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816879; bh=pebq8GHSI7IfOohalTm91NbPof6IcZx9lXx9DQZnkKc=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=m07jpV3wts2wecQalw6r5Ip2J7np1IuKGiaBK1ZcjWyWeTvo3N/DbIKEmF5tsVKJK qCz6p8iinWuqHlPWc81UgUYB58UeTRNgg8be+Dz9M2Cji6iAJet46ImkwfLRW/Ld20 yam8DCuMa1g6DHBOljBteanDPS/EuQlgXJ9EkMhA= Authentication-Results: mxback5q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-EWV4Iv0P; Sun, 12 Jan 2020 11:14:38 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang , Rob Herring Subject: [PATCH v3 01/10] dt-bindings: Document loongson vendor-prefix Date: Sun, 12 Jan 2020 16:14:07 +0800 Message-Id: <20200112081416.722218-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Loongson is a MIPS-compatible processor vendor. Signed-off-by: Jiaxun Yang Acked-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 50c2b635ecfd..31b364107e60 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -545,6 +545,8 @@ patternProperties: description: Logic PD, Inc. "^longcheer,.*": description: Longcheer Technology (Shanghai) Co., Ltd. + "^loongson,.*": + description: Loongson Technology Corporation Limited "^lsi,.*": description: LSI Corp. (LSI Logic) "^lwn,.*": From patchwork Sun Jan 12 08:14:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329063 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0311F930 for ; Sun, 12 Jan 2020 08:20:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B76AE214D8 for ; Sun, 12 Jan 2020 08:20:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="eWxJSI36" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732370AbgALIUM (ORCPT ); Sun, 12 Jan 2020 03:20:12 -0500 Received: from forward100o.mail.yandex.net ([37.140.190.180]:60404 "EHLO forward100o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732369AbgALIUM (ORCPT ); Sun, 12 Jan 2020 03:20:12 -0500 X-Greylist: delayed 332 seconds by postgrey-1.27 at vger.kernel.org; Sun, 12 Jan 2020 03:20:07 EST Received: from forward103q.mail.yandex.net (forward103q.mail.yandex.net [IPv6:2a02:6b8:c0e:50:0:640:b21c:d009]) by forward100o.mail.yandex.net (Yandex) with ESMTP id B438B4AC0146; Sun, 12 Jan 2020 11:14:49 +0300 (MSK) Received: from mxback11q.mail.yandex.net (mxback11q.mail.yandex.net [IPv6:2a02:6b8:c0e:1b4:0:640:1f0c:10f2]) by forward103q.mail.yandex.net (Yandex) with ESMTP id AEAFC61E0011; Sun, 12 Jan 2020 11:14:49 +0300 (MSK) Received: from vla1-ee05250d997a.qloud-c.yandex.net (vla1-ee05250d997a.qloud-c.yandex.net [2a02:6b8:c0d:3495:0:640:ee05:250d]) by mxback11q.mail.yandex.net (mxback/Yandex) with ESMTP id GPYyGPLaLe-EnouUtZJ; Sun, 12 Jan 2020 11:14:49 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816889; bh=0NuSIKtmETtBEl6vPK8FE06E3r9xPn7fhFLhkmzxzqg=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=eWxJSI36KkcBDIQVZ8lHVQVr+P+PSI93GbCsK665Vkg+VaWOYkoM0DNUQxImzI3cz XVOLnpNE0emR23KpUL2IleQS4p1tHLz3WDpahQBF3KGj49bD2kWTYZ3/Idh5fDMq9J RKsBktg3WsVPRPFLXwQStbRDIlvwB+ai8rlVjJAQ= Authentication-Results: mxback11q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-EeV4Btrp; Sun, 12 Jan 2020 11:14:45 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v3 02/10] irqchip: Add driver for Loongson I/O interrupt controller Date: Sun, 12 Jan 2020 16:14:08 +0800 Message-Id: <20200112081416.722218-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This controller appeared on Loongson family of chips as the primary package interrupt source. Signed-off-by: Jiaxun Yang --- drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-loongson-iointc.c | 338 ++++++++++++++++++++++++++ 3 files changed, 348 insertions(+) create mode 100644 drivers/irqchip/irq-loongson-iointc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 697e6a8ccaae..3f220648151b 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -499,4 +499,13 @@ config SIFIVE_PLIC If you don't know what to do here, say Y. +config LOONGSON_IOINTC + bool "Loongson I/O Interrupt Controller" + depends on MACH_LOONGSON64 + default y + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + help + Support for the Loongson I/O Interrupt Controller. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e806dda690ea..3e98241401b3 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -104,3 +104,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_LOONGSON_IOINTC) += irq-loongson-iointc.o diff --git a/drivers/irqchip/irq-loongson-iointc.c b/drivers/irqchip/irq-loongson-iointc.c new file mode 100644 index 000000000000..b8deead97bc3 --- /dev/null +++ b/drivers/irqchip/irq-loongson-iointc.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020, Jiaxun Yang + * Loongson IOINTC IRQ support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define IOINTC_CHIP_IRQ 32 +#define IOINTC_NUM_PARENT 4 + +#define IOINTC_REG_INTx_MAP(x) (x * 0x1) +#define IOINTC_INTC_CHIP_START 0x20 + +#define IOINTC_REG_INTC_STATUS (IOINTC_INTC_CHIP_START + 0x20) +#define IOINTC_REG_INTC_EN_STATUS (IOINTC_INTC_CHIP_START + 0x04) +#define IOINTC_REG_INTC_ENABLE (IOINTC_INTC_CHIP_START + 0x08) +#define IOINTC_REG_INTC_DISABLE (IOINTC_INTC_CHIP_START + 0x0c) +#define IOINTC_REG_INTC_POL (IOINTC_INTC_CHIP_START + 0x10) +#define IOINTC_REG_INTC_EDGE (IOINTC_INTC_CHIP_START + 0x14) + +#define BUGGY_LPC_IRQ 10 + +#define IOINTC_SHIFT_INTx 4 + +struct iointc_handler_data { + struct iointc_priv *priv; + u32 parent_int_map; +}; + +struct iointc_priv { + void __iomem *base; + struct irq_chip_generic *gc; + u8 map_cache[IOINTC_CHIP_IRQ]; + struct iointc_handler_data handler[IOINTC_NUM_PARENT]; + u8 possible_parent_mask; + bool have_lpc_irq_bug; +}; + +static void iointc_chained_handle_irq(struct irq_desc *desc) +{ + struct iointc_handler_data *handler = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_chip_generic *gc = handler->priv->gc; + u32 pending; + + chained_irq_enter(chip, desc); + + pending = readl(gc->reg_base + IOINTC_REG_INTC_STATUS); + + if (!pending) { + /* Always blame LPC IRQ if we have that Bug and LPC interrupt enabled */ + if (handler->priv->have_lpc_irq_bug && + (handler->parent_int_map & ~gc->mask_cache & BIT(BUGGY_LPC_IRQ))) + generic_handle_irq(irq_find_mapping(gc->domain, BUGGY_LPC_IRQ)); + else + spurious_interrupt(); + } + + while (pending) { + int bit = __ffs(pending); + + generic_handle_irq(irq_find_mapping(gc->domain, bit)); + pending &= ~BIT(bit); + } + + chained_irq_exit(chip, desc); +} + +static void map_cache_set_core(struct iointc_priv *priv, int irq, int core) +{ + priv->map_cache[irq] &= ~GENMASK(3, 0); + priv->map_cache[irq] |= BIT(core); +} + +static void write_map_cache(struct iointc_priv *priv, int irq) +{ + writeb(priv->map_cache[irq], + priv->base + IOINTC_REG_INTx_MAP(irq)); +} + +static void iointc_set_bit(struct irq_chip_generic *gc, + unsigned int offset, + u32 mask, bool set) +{ + if (set) + writel(readl(gc->reg_base + offset) | mask, + gc->reg_base + offset); + else + writel(readl(gc->reg_base + offset) & ~mask, + gc->reg_base + offset); +} + +static int iointc_set_type(struct irq_data *data, unsigned int type) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + u32 mask = data->mask; + unsigned long flags; + + irq_gc_lock_irqsave(gc, flags); + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + iointc_set_bit(gc, IOINTC_REG_INTC_EDGE, mask, false); + iointc_set_bit(gc, IOINTC_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_LEVEL_LOW: + iointc_set_bit(gc, IOINTC_REG_INTC_EDGE, mask, false); + iointc_set_bit(gc, IOINTC_REG_INTC_POL, mask, false); + break; + case IRQ_TYPE_EDGE_RISING: + iointc_set_bit(gc, IOINTC_REG_INTC_EDGE, mask, true); + iointc_set_bit(gc, IOINTC_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_EDGE_FALLING: + iointc_set_bit(gc, IOINTC_REG_INTC_EDGE, mask, true); + iointc_set_bit(gc, IOINTC_REG_INTC_POL, mask, false); + break; + default: + return -EINVAL; + } + irq_gc_unlock_irqrestore(gc, flags); + + irqd_set_trigger_type(data, type); + return 0; +} + +static int iointc_set_affinity(struct irq_data *idata, + const cpumask_t *cpu_mask, bool force) +{ + return -ENAVAIL; +} + +static void iointc_resume(struct irq_chip_generic *gc) +{ + struct iointc_priv *priv = gc->private; + unsigned long flags; + int i; + + irq_gc_lock_irqsave(gc, flags); + /* Revert map cache */ + for (i = 0; i < IOINTC_CHIP_IRQ; i++) + write_map_cache(priv, i); + + /* Revert mask cache again */ + writel(gc->mask_cache, gc->reg_base + IOINTC_REG_INTC_DISABLE); + writel(~gc->mask_cache, gc->reg_base + IOINTC_REG_INTC_ENABLE); + irq_gc_unlock_irqrestore(gc, flags); +} + +static void validate_parent_mask(struct iointc_priv *priv, u32 of_parent_int_map[]) +{ + u32 proceed_mask = 0x0, duplicated_mask = 0x0; + int i; + int fallback_parent = __ffs(priv->possible_parent_mask); + + for (i = 0; i < IOINTC_NUM_PARENT; i++) { + /* Try if the parent is avilable */ + if (!(priv->possible_parent_mask & BIT(i))) + continue; + + priv->handler[i].parent_int_map = of_parent_int_map[i]; + + /* Detect if the IRQ have previously proceed */ + duplicated_mask |= (priv->handler[i].parent_int_map & proceed_mask); + proceed_mask |= priv->handler[i].parent_int_map; + } + + /* Fallback IRQs with no map bit set */ + while (~proceed_mask) { + int bit = __ffs(~proceed_mask); + + pr_warn("loongson-iointc: Found homeless IRQ %d, map to INT%d\n", + bit, fallback_parent); + priv->handler[fallback_parent].parent_int_map |= BIT(bit); + proceed_mask |= BIT(bit); + } + + /* Fallback IRQs with mutiple map bit set */ + while (duplicated_mask) { + int bit = __ffs(duplicated_mask); + + pr_warn("loongson-iointc: IRQ %d have mutiple parents, map to INT%d\n", + bit, fallback_parent); + /* Clear the bit in all parent bits */ + for (i = 0; i < IOINTC_NUM_PARENT; i++) + priv->handler[i].parent_int_map &= ~BIT(bit); + + priv->handler[fallback_parent].parent_int_map |= BIT(bit); + duplicated_mask &= ~BIT(bit); + } + + /* Generate parent INT part of map Cache */ + for (i = 0; i < IOINTC_NUM_PARENT; i++) { + u32 pending = priv->handler[i].parent_int_map; + + while (pending) { + int bit = __ffs(pending); + + priv->map_cache[bit] = BIT(i) << IOINTC_SHIFT_INTx; + pending &= ~BIT(bit); + } + } +} + +static const char *parent_names[] = {"int0", "int1", "int2", "int3"}; + +int __init iointc_of_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_chip_generic *gc; + struct irq_domain *domain; + struct irq_chip_type *ct; + struct iointc_priv *priv; + u32 of_parent_int_map[IOINTC_NUM_PARENT]; + int parent_irq[IOINTC_NUM_PARENT]; + int core = loongson_sysconf.boot_cpu_id; + int i, err = 0; + int sz; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = of_iomap(node, 0); + if (!priv->base) { + err = -ENODEV; + goto out_free_priv; + } + + if (of_device_is_compatible(node, "loongson,iointc-1.0")) + priv->have_lpc_irq_bug = true; + + for (i = 0; i < IOINTC_NUM_PARENT; i++) { + parent_irq[i] = of_irq_get_byname(node, parent_names[i]); + if (parent_irq[i] >= 0) + priv->possible_parent_mask |= BIT(i); + } + + + if (!priv->possible_parent_mask) { + pr_err("loongson-iointc: No parent\n"); + err = -ENOMEM; + goto out_iounmap; + } + + sz = of_property_read_variable_u32_array(node, "loongson,parent_int_map", + &of_parent_int_map[0], IOINTC_NUM_PARENT, + IOINTC_NUM_PARENT); + if (sz < 4) { + pr_err("loongson-iointc: No parent_int_map\n"); + err = -ENODEV; + goto out_iounmap; + } + + /* Setup IRQ domain */ + domain = irq_domain_add_linear(node, 32, + &irq_generic_chip_ops, priv); + if (!domain) { + pr_err("loongson-iointc: cannot add IRQ domain\n"); + err = -ENOMEM; + goto out_iounmap; + } + + err = irq_alloc_domain_generic_chips(domain, 32, 1, + node->full_name, handle_level_irq, + IRQ_NOPROBE, 0, 0); + if (err) { + pr_err("loongson-iointc: unable to register IRQ domain\n"); + err = -ENOMEM; + goto out_free_domain; + } + + + /* Disable all IRQs */ + writel(0xffffffff, priv->base + IOINTC_REG_INTC_DISABLE); + /* Set to level triggered */ + writel(0x0, priv->base + IOINTC_REG_INTC_EDGE); + + validate_parent_mask(priv, &of_parent_int_map[0]); + + for (i = 0; i < IOINTC_CHIP_IRQ; i++) { + map_cache_set_core(priv, i, core); + write_map_cache(priv, i); + } + + gc = irq_get_domain_generic_chip(domain, 0); + gc->private = priv; + gc->reg_base = priv->base; + gc->domain = domain; + gc->resume = iointc_resume; + + ct = gc->chip_types; + ct->regs.enable = IOINTC_REG_INTC_ENABLE; + ct->regs.disable = IOINTC_REG_INTC_DISABLE; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; + ct->chip.irq_set_type = iointc_set_type; + ct->chip.irq_set_affinity = iointc_set_affinity; + + gc->mask_cache = 0xffffffff; + priv->gc = gc; + + for (i = 0; i < IOINTC_NUM_PARENT; i++) { + if (parent_irq[i] < 0) + continue; + + priv->handler[i].priv = priv; + irq_set_chained_handler_and_data(parent_irq[i], + iointc_chained_handle_irq, &priv->handler[i]); + } + + return 0; + +out_free_domain: + irq_domain_remove(domain); +out_iounmap: + iounmap(priv->base); +out_free_priv: + kfree(priv); + + return err; +} + +IRQCHIP_DECLARE(loongson_iointc_1_0, "loongson,iointc-1.0", iointc_of_init); +IRQCHIP_DECLARE(loongson_iointc_1_0a, "loongson,iointc-1.0a", iointc_of_init); From patchwork Sun Jan 12 08:14:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329071 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D2DFE1580 for ; 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Sun, 12 Jan 2020 11:15:01 +0300 (MSK) Received: from vla1-ee05250d997a.qloud-c.yandex.net (vla1-ee05250d997a.qloud-c.yandex.net [2a02:6b8:c0d:3495:0:640:ee05:250d]) by mxback8q.mail.yandex.net (mxback/Yandex) with ESMTP id OyCHLVWPLH-F0pqfcDT; Sun, 12 Jan 2020 11:15:01 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816901; bh=CVEeCj5Nw0JRy5UhMzMQL9w0iN5X3gPEi0kdS+ta39E=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=KoioIhgSID9TutebLu6M1GtXSorWdSkHXB6BYIB7bqe7fFBfXcQOeVzsQWWGWuc8z d6pV/9eCRAYUiZPrPD7XWa93SaEPHV/Gjgkmh0UGwpbGNnuy22dD4sP/IO3w7Jkfbn Wv/tyAmFc3eiBwoEnqdxu46IqkI7G0kmp0z+9wRk= Authentication-Results: mxback8q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-EoV4gOt4; Sun, 12 Jan 2020 11:14:55 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang , Rob Herring Subject: [PATCH v3 03/10] dt-bindings: interrupt-controller: Add Loongson IOINTC Date: Sun, 12 Jan 2020 16:14:09 +0800 Message-Id: <20200112081416.722218-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Document Loongson I/O Interrupt controller. Signed-off-by: Jiaxun Yang Reviewed-by: Rob Herring --- .../interrupt-controller/loongson,iointc.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml new file mode 100644 index 000000000000..b0fe6c551362 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,iointc.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,iointc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson I/O Interrupt Controller + +maintainers: + - Jiaxun Yang + +description: | + This interrupt controller is found in the Loongson-3 family of chips as the primary + package interrupt source which can route interrupt to interrupt line of cores. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - const: loongson,iointc-1.0 + - const: loongson,iointc-1.0a + + reg: + maxItems: 1 + + interrupt-controller: true + + interrupts: + description: + Interrupt source of the CPU interrupts. + minItems: 1 + maxItems: 4 + + interrupt-names: + description: List of names for the parent interrupts. + oneOf: + - items: + - const: int0 + - const: int1 + - const: int2 + - const: int3 + minItems: 1 + maxItems: 4 + + '#interrupt-cells': + const: 2 + + 'loongson,parent_int_map': + description: | + This property points the accept range of children interrupts + that parents will recieve. Each cell refers to a parent interrupt line + and each bit in the cell refers to a children interrupt. If a parent + did not connected, than keep it's cell with zero. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 4 + maxItems: 4 + + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - 'loongson,parent_int_map' + + +examples: + - | + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,iointc-1.0"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>; + interrupt-names = "int0", "int1"; + + loongson,parent_int_map = <0xf0ffffff>, /* int0 */ + <0x0f000000>, /* int1 */ + <0x00000000>, /* int2 */ + <0x00000000>; /* int3 */ + + }; + +... From patchwork Sun Jan 12 08:14:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329075 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B2BF139A for ; Sun, 12 Jan 2020 08:21:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3F61821569 for ; Sun, 12 Jan 2020 08:21:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="ih7aFdi3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732385AbgALIVQ (ORCPT ); Sun, 12 Jan 2020 03:21:16 -0500 Received: from forward101j.mail.yandex.net ([5.45.198.241]:46935 "EHLO forward101j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732369AbgALIVP (ORCPT ); Sun, 12 Jan 2020 03:21:15 -0500 Received: from forward103q.mail.yandex.net (forward103q.mail.yandex.net [IPv6:2a02:6b8:c0e:50:0:640:b21c:d009]) by forward101j.mail.yandex.net (Yandex) with ESMTP id CC09F1BE0FD6; Sun, 12 Jan 2020 11:15:12 +0300 (MSK) Received: from mxback5q.mail.yandex.net (mxback5q.mail.yandex.net [IPv6:2a02:6b8:c0e:1ba:0:640:b716:ad89]) by forward103q.mail.yandex.net (Yandex) with ESMTP id C4DD661E0004; Sun, 12 Jan 2020 11:15:12 +0300 (MSK) Received: from vla1-ee05250d997a.qloud-c.yandex.net (vla1-ee05250d997a.qloud-c.yandex.net [2a02:6b8:c0d:3495:0:640:ee05:250d]) by mxback5q.mail.yandex.net (mxback/Yandex) with ESMTP id RzsfWlDwcB-FCcCWsp6; Sun, 12 Jan 2020 11:15:12 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816912; bh=cQb47U+3vGM7o7PpBCUiXtwksEyD9C8rtuU6Jf0f18c=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=ih7aFdi3uOQVS/LHF5ZEDVK0GFR25LKrxqK4zPsaVM3Okh9AbNRuMLs63YqOuNSWa MzsMEI8fW3rzhb6ZviZ6vSOhajYyYurUcd2uj4EDPWvXsxyldrZqGT79fo3U9QFBpe CFZpUpIu506WIb8n7YJs4aP8W/hRnjdYjPqBKtyc= Authentication-Results: mxback5q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-F1V4Kccv; Sun, 12 Jan 2020 11:15:07 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v3 04/10] irqchip: Add driver for Loongson-3 HyperTransport PIC controller Date: Sun, 12 Jan 2020 16:14:10 +0800 Message-Id: <20200112081416.722218-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This controller appeared on Loongson-3 family of chips to receive interrupts from PCH PIC. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/i8259.h | 1 + drivers/irqchip/Kconfig | 9 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-i8259.c | 6 +- drivers/irqchip/irq-loongson-htpic.c | 147 +++++++++++++++++++++++++++ 5 files changed, 161 insertions(+), 3 deletions(-) create mode 100644 drivers/irqchip/irq-loongson-htpic.c diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h index 97a5e41ed1ab..1ec3dbb1588f 100644 --- a/arch/mips/include/asm/i8259.h +++ b/arch/mips/include/asm/i8259.h @@ -36,6 +36,7 @@ extern raw_spinlock_t i8259A_lock; extern void make_8259A_irq(unsigned int irq); extern void init_i8259_irqs(void); +extern struct irq_domain *of_init_i8259_irqs(struct device_node *node); /** * i8159_set_poll() - Override the i8259 polling function diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 3f220648151b..2d9fadb1b5d5 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -508,4 +508,13 @@ config LOONGSON_IOINTC help Support for the Loongson I/O Interrupt Controller. +config LOONGSON_HTPIC + bool "Loongson3 HyperTransport PIC Controller" + depends on MACH_LOONGSON64 + default y + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + select I8259 + help + Support for the Loongson-3 HyperTransport PIC Controller. endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 3e98241401b3..96ed00da097d 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -105,3 +105,4 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o obj-$(CONFIG_LOONGSON_IOINTC) += irq-loongson-iointc.o +obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c index d000870d9b6b..9d79acce6c0c 100644 --- a/drivers/irqchip/irq-i8259.c +++ b/drivers/irqchip/irq-i8259.c @@ -309,7 +309,7 @@ static const struct irq_domain_ops i8259A_ops = { * driver compatibility reasons interrupts 0 - 15 to be the i8259 * interrupts even if the hardware uses a different interrupt numbering. */ -struct irq_domain * __init __init_i8259_irqs(struct device_node *node) +struct irq_domain * __init of_init_i8259_irqs(struct device_node *node) { struct irq_domain *domain; @@ -330,7 +330,7 @@ struct irq_domain * __init __init_i8259_irqs(struct device_node *node) void __init init_i8259_irqs(void) { - __init_i8259_irqs(NULL); + of_init_i8259_irqs(NULL); } static void i8259_irq_dispatch(struct irq_desc *desc) @@ -351,7 +351,7 @@ int __init i8259_of_init(struct device_node *node, struct device_node *parent) struct irq_domain *domain; unsigned int parent_irq; - domain = __init_i8259_irqs(node); + domain = of_init_i8259_irqs(node); parent_irq = irq_of_parse_and_map(node, 0); if (!parent_irq) { diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c new file mode 100644 index 000000000000..fa33176157d6 --- /dev/null +++ b/drivers/irqchip/irq-loongson-htpic.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020, Jiaxun Yang + * Loongson HTPIC IRQ support + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define HTPIC_MAX_PARENT_IRQ 4 +#define HTINT_NUM_VECTORS 8 +#define HTINT_EN_OFF 0x20 + +struct loongson_htpic { + void __iomem *base; + struct irq_domain *domain; +}; + +struct loongson_htpic *htpic; + +static void htpic_irq_dispatch(struct irq_desc *desc) +{ + struct loongson_htpic *priv = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + uint32_t pending; + + chained_irq_enter(chip, desc); + pending = readl(priv->base); + /* Ack all irqs */ + writel(pending, priv->base); + + if (!pending) + spurious_interrupt(); + + while (pending) { + int bit = __ffs(pending); + + if (unlikely(bit > 15)) + spurious_interrupt(); + + generic_handle_irq(irq_linear_revmap(priv->domain, bit)); + pending &= ~BIT(bit); + } + chained_irq_exit(chip, desc); +} + +static void htpic_reg_init(void) +{ + int i; + + for (i = 0; i < HTINT_NUM_VECTORS; i++) { + uint32_t val; + + /* Disable all HT Vectors */ + writel(0x0, htpic->base + HTINT_EN_OFF + i * 0x4); + val = readl(htpic->base + i * 0x4); + /* Ack all possible pending IRQs */ + writel(GENMASK(31, 0), htpic->base + i * 0x4); + } + + /* Enable 16 vectors for PIC */ + writel(0xffff, htpic->base + HTINT_EN_OFF); +} + +static void htpic_resume(void) +{ + htpic_reg_init(); +} + +struct syscore_ops htpic_syscore_ops = { + .resume = htpic_resume, +}; + +int __init htpic_of_init(struct device_node *node, struct device_node *parent) +{ + unsigned int parent_irq[4]; + int i, err; + int num_parents = 0; + + if (htpic) { + pr_err("loongson-htpic: Only one htpic is allowed in the system\n"); + return -ENODEV; + } + + htpic = kzalloc(sizeof(*htpic), GFP_KERNEL); + if (!htpic) { + err = -ENOMEM; + goto out_free; + } + + htpic->base = of_iomap(node, 0); + if (!htpic->base) { + pr_err("loongson-htpic: Failed to map io\n"); + err = -ENODEV; + goto out_free; + } + + htpic->domain = of_init_i8259_irqs(node); + if (!htpic->domain) { + pr_err("loongson-htpic: Failed to initialize i8259 irqs\n"); + err = -ENOMEM; + goto out_iounmap; + } + + for (i = 0; i < HTPIC_MAX_PARENT_IRQ; i++) { + parent_irq[i] = irq_of_parse_and_map(node, 0); + if (parent_irq[i] < 0) + break; + + num_parents++; + } + + if (!num_parents) { + pr_err("loongson-htpic: Failed to get parent irqs\n"); + err = -ENODEV; + goto out_remove_domain; + } + + htpic_reg_init(); + + for (i = 0; i < num_parents; i++) { + irq_set_chained_handler_and_data(parent_irq[i], + htpic_irq_dispatch, htpic); + } + + register_syscore_ops(&htpic_syscore_ops); + + return 0; + +out_remove_domain: + irq_domain_remove(htpic->domain); +out_iounmap: + iounmap(htpic->base); +out_free: + kfree(htpic); + return err; +} + +IRQCHIP_DECLARE(loongson_htpic, "loongson,htpic-1.0", htpic_of_init); From patchwork Sun Jan 12 08:14:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E5E15139A for ; Sun, 12 Jan 2020 08:20:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C01092064C for ; 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Sun, 12 Jan 2020 11:15:21 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816921; bh=kFUYrcnxgHhYt9NZF/PFTRJ9jW7qOpJ8qLdxtiiXBEo=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=vtVOJ5uuuwcqZt3Wp7mDGcWm2RTU0ac3q6QqObK27nejqJ+QKpZyybI9vTpYCpsMh JxWONnunGnLvc21+FaEOMuWidfSRcIzrdpdhKy+x6o/Z/uKkZ3ZsbgVcGDIX7bKuhb VTRw3D1A/eOEQP6JVMH4Y98E3MU+c+5vvL6DodNU= Authentication-Results: mxback10q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-FDV4R9L7; Sun, 12 Jan 2020 11:15:18 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang , Rob Herring Subject: [PATCH v3 05/10] dt-bindings: interrupt-controller: Add Loongson-3 HTPIC Date: Sun, 12 Jan 2020 16:14:11 +0800 Message-Id: <20200112081416.722218-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Document Loongson-3 HyperTransport PIC controller. Signed-off-by: Jiaxun Yang Reviewed-by: Rob Herring --- .../interrupt-controller/loongson,htpic.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml new file mode 100644 index 000000000000..efcc3f43e45b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson-3 HyperTransport Interrupt Controller + +maintainers: + - Jiaxun Yang + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: | + This interrupt controller is found in the Loongson-3 family of chips to transfer + interrupts from PCH PIC connected on HyperTransport bus. + +properties: + compatible: + const: loongson,htpic-1.0 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 4 + description: | + Four parent interrupts that recieve chained interrupts. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include + htintc: interrupt-controller@1fb000080 { + compatible = "loongson,htintc-1.0"; + reg = <0x1fb000080 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +... From patchwork Sun Jan 12 08:14:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329079 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 281CE139A for ; Sun, 12 Jan 2020 08:22:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F361721569 for ; Sun, 12 Jan 2020 08:22:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="R3VW93Az" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732380AbgALIWu (ORCPT ); Sun, 12 Jan 2020 03:22:50 -0500 Received: from forward106p.mail.yandex.net ([77.88.28.109]:36450 "EHLO forward106p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732371AbgALIWu (ORCPT ); Sun, 12 Jan 2020 03:22:50 -0500 Received: from forward102q.mail.yandex.net (forward102q.mail.yandex.net [IPv6:2a02:6b8:c0e:1ba:0:640:516:4e7d]) by forward106p.mail.yandex.net (Yandex) with ESMTP id 430F51C808D4; Sun, 12 Jan 2020 11:15:28 +0300 (MSK) Received: from mxback12q.mail.yandex.net (mxback12q.mail.yandex.net [IPv6:2a02:6b8:c0e:1b3:0:640:3818:d096]) by forward102q.mail.yandex.net (Yandex) with ESMTP id 3DF337F20010; Sun, 12 Jan 2020 11:15:28 +0300 (MSK) Received: from vla1-ee05250d997a.qloud-c.yandex.net (vla1-ee05250d997a.qloud-c.yandex.net [2a02:6b8:c0d:3495:0:640:ee05:250d]) by mxback12q.mail.yandex.net (mxback/Yandex) with ESMTP id b9DzCgWqde-FSh42AqG; Sun, 12 Jan 2020 11:15:28 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816928; bh=A5zaPJqEAMlFziZ2sTS5vB1EZSkHWnI9Py/AyzLK/MY=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=R3VW93AzT3g7Yp9wuEHfhj0q58Zg+LPbTkd8BMYzS/ZE6GqgWlncbpA1DjW9x032f cbGBlNgfKWO+pJds6/AdUq4XslN88OlwVoOikKBFuOnCBvYG1NpwZSS7VBlG1LSBoX /x4u9aY4nbAFA28wX08Ek+Fmxbe4TK8DBaA7NQfA= Authentication-Results: mxback12q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-FLV4hR7o; Sun, 12 Jan 2020 11:15:26 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v3 06/10] irqchip: mips-cpu: Convert to simple domain Date: Sun, 12 Jan 2020 16:14:12 +0800 Message-Id: <20200112081416.722218-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The old code is using legacy domain to setup irq_domain for CPU interrupts which requires irq_desc being preallocated. However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up unallocated and lead to incorrect behavior. Thus we convert the legacy domain to simple domain which can allocate irq_desc during initialization. Signed-off-by: Jiaxun Yang --- drivers/irqchip/irq-mips-cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 95d4fd8f7a96..c3cf7fa76424 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node) clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); - irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, + irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE, &mips_cpu_intc_irq_domain_ops, NULL); if (!irq_domain) From patchwork Sun Jan 12 08:14:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329073 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BF4211580 for ; Sun, 12 Jan 2020 08:21:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 89CC121569 for ; Sun, 12 Jan 2020 08:21:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="BqPbUKBn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732371AbgALIVM (ORCPT ); Sun, 12 Jan 2020 03:21:12 -0500 Received: from forward102p.mail.yandex.net ([77.88.28.102]:55370 "EHLO forward102p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732369AbgALIVL (ORCPT ); Sun, 12 Jan 2020 03:21:11 -0500 X-Greylist: delayed 341 seconds by postgrey-1.27 at vger.kernel.org; Sun, 12 Jan 2020 03:21:10 EST Received: from forward103q.mail.yandex.net (forward103q.mail.yandex.net [IPv6:2a02:6b8:c0e:50:0:640:b21c:d009]) by forward102p.mail.yandex.net (Yandex) with ESMTP id DF1AA1D40A7B; Sun, 12 Jan 2020 11:15:41 +0300 (MSK) Received: from mxback12q.mail.yandex.net (mxback12q.mail.yandex.net [IPv6:2a02:6b8:c0e:1b3:0:640:3818:d096]) by forward103q.mail.yandex.net (Yandex) with ESMTP id D981961E0004; Sun, 12 Jan 2020 11:15:41 +0300 (MSK) Received: from vla1-ee05250d997a.qloud-c.yandex.net (vla1-ee05250d997a.qloud-c.yandex.net [2a02:6b8:c0d:3495:0:640:ee05:250d]) by mxback12q.mail.yandex.net (mxback/Yandex) with ESMTP id FtiXaFgyPz-Ffh0cOpa; Sun, 12 Jan 2020 11:15:41 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816941; bh=QiD7FdoBSDhrTqxbbKQb//gLnNRoKM1HasAgElmWEfk=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=BqPbUKBn1pAUFJ13PDleOfECkIKQtiiTOF0TG3s3AtDm3oBlDqhAdtGO9cUt0aEuO VomSQsf0/c2Na6QS30147EkevRamJAaAY5H1xsHcizVRcG8VDhCHUDG+4xnAaSPxjz AB2W3chKQRBFjtJrPQisCktowhqyGD0QwXLL9l/M= Authentication-Results: mxback12q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-FSV4molR; Sun, 12 Jan 2020 11:15:33 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v3 07/10] MIPS: Loongson64: Drop legacy IRQ code Date: Sun, 12 Jan 2020 16:14:13 +0800 Message-Id: <20200112081416.722218-8-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org We've made generic irqchip drivers for Loongson-3 platform, it's time to say goodbye to these legacy code. Signed-off-by: Jiaxun Yang --- .../include/asm/mach-loongson64/boot_param.h | 2 + arch/mips/include/asm/mach-loongson64/irq.h | 29 ---- arch/mips/loongson64/Makefile | 2 +- arch/mips/loongson64/init.c | 6 + arch/mips/loongson64/irq.c | 162 ------------------ arch/mips/loongson64/smp.c | 28 ++- 6 files changed, 20 insertions(+), 209 deletions(-) delete mode 100644 arch/mips/loongson64/irq.c diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h index 8c286bedff3e..2ed483e32d8c 100644 --- a/arch/mips/include/asm/mach-loongson64/boot_param.h +++ b/arch/mips/include/asm/mach-loongson64/boot_param.h @@ -2,6 +2,8 @@ #ifndef __ASM_MACH_LOONGSON64_BOOT_PARAM_H_ #define __ASM_MACH_LOONGSON64_BOOT_PARAM_H_ +#include + #define SYSTEM_RAM_LOW 1 #define SYSTEM_RAM_HIGH 2 #define SYSTEM_RAM_RESERVED 3 diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index 73a89913dc38..12208119aac0 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,34 +7,5 @@ /* cpu core interrupt numbers */ #define MIPS_CPU_IRQ_BASE 56 -#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */ -#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */ -#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */ - -#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base -#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80) -#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0) -#define LOONGSON_HT1_INT_VECTOR(n) \ - LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n)) -#define LOONGSON_HT1_INTN_EN(n) \ - LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n)) - -#define LOONGSON_INT_ROUTER_OFFSET 0x1400 -#define LOONGSON_INT_ROUTER_INTEN \ - LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24) -#define LOONGSON_INT_ROUTER_INTENSET \ - LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28) -#define LOONGSON_INT_ROUTER_INTENCLR \ - LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c) -#define LOONGSON_INT_ROUTER_ENTRY(n) \ - LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n) -#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a) -#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18) - -#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */ - -extern void fixup_irqs(void); -extern void loongson3_ipi_interrupt(struct pt_regs *regs); - #include_next #endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */ diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile index 7821891bc5d0..b7f40b179c71 100644 --- a/arch/mips/loongson64/Makefile +++ b/arch/mips/loongson64/Makefile @@ -2,7 +2,7 @@ # # Makefile for Loongson-3 family machines # -obj-$(CONFIG_MACH_LOONGSON64) += irq.o cop2-ex.o platform.o acpi_init.o dma.o \ +obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o acpi_init.o dma.o \ setup.o init.o env.o time.o reset.o \ obj-$(CONFIG_SMP) += smp.o diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c index 5ac1a0f35ca4..da38944471f4 100644 --- a/arch/mips/loongson64/init.c +++ b/arch/mips/loongson64/init.c @@ -4,6 +4,7 @@ * Author: Wu Zhangjin, wuzhangjin@gmail.com */ +#include #include #include #include @@ -44,3 +45,8 @@ void __init prom_init(void) void __init prom_free_prom_memory(void) { } + +void __init arch_init_irq(void) +{ + irqchip_init(); +} diff --git a/arch/mips/loongson64/irq.c b/arch/mips/loongson64/irq.c deleted file mode 100644 index 79ad797497e4..000000000000 --- a/arch/mips/loongson64/irq.c +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include - -#include -#include -#include - -#include "smp.h" - -extern void loongson3_send_irq_by_ipi(int cpu, int irqs); - -unsigned int irq_cpu[16] = {[0 ... 15] = -1}; -unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15}; -unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12; - -int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, - bool force) -{ - unsigned int cpu; - struct cpumask new_affinity; - - /* I/O devices are connected on package-0 */ - cpumask_copy(&new_affinity, affinity); - for_each_cpu(cpu, affinity) - if (cpu_data[cpu].package > 0) - cpumask_clear_cpu(cpu, &new_affinity); - - if (cpumask_empty(&new_affinity)) - return -EINVAL; - - cpumask_copy(d->common->affinity, &new_affinity); - - return IRQ_SET_MASK_OK_NOCOPY; -} - -static void ht_irqdispatch(void) -{ - unsigned int i, irq; - struct irq_data *irqd; - struct cpumask affinity; - - irq = LOONGSON_HT1_INT_VECTOR(0); - LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */ - - for (i = 0; i < ARRAY_SIZE(ht_irq); i++) { - if (!(irq & (0x1 << ht_irq[i]))) - continue; - - /* handled by local core */ - if (local_irq & (0x1 << ht_irq[i])) { - do_IRQ(ht_irq[i]); - continue; - } - - irqd = irq_get_irq_data(ht_irq[i]); - cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask); - if (cpumask_empty(&affinity)) { - do_IRQ(ht_irq[i]); - continue; - } - - irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity); - if (irq_cpu[ht_irq[i]] >= nr_cpu_ids) - irq_cpu[ht_irq[i]] = cpumask_first(&affinity); - - if (irq_cpu[ht_irq[i]] == 0) { - do_IRQ(ht_irq[i]); - continue; - } - - /* balanced by other cores */ - loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i])); - } -} - -#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0) - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending; - - pending = read_c0_cause() & read_c0_status() & ST0_IM; - - if (pending & CAUSEF_IP7) - do_IRQ(LOONGSON_TIMER_IRQ); -#if defined(CONFIG_SMP) - if (pending & CAUSEF_IP6) - loongson3_ipi_interrupt(NULL); -#endif - if (pending & CAUSEF_IP3) - ht_irqdispatch(); - if (pending & CAUSEF_IP2) - do_IRQ(LOONGSON_UART_IRQ); - if (pending & UNUSED_IPS) { - pr_err("%s : spurious interrupt\n", __func__); - spurious_interrupt(); - } -} - -static inline void mask_loongson_irq(struct irq_data *d) { } -static inline void unmask_loongson_irq(struct irq_data *d) { } - - /* For MIPS IRQs which shared by all cores */ -static struct irq_chip loongson_irq_chip = { - .name = "Loongson", - .irq_ack = mask_loongson_irq, - .irq_mask = mask_loongson_irq, - .irq_mask_ack = mask_loongson_irq, - .irq_unmask = unmask_loongson_irq, - .irq_eoi = unmask_loongson_irq, -}; - -void irq_router_init(void) -{ - int i; - - /* route LPC int to cpu core0 int 0 */ - LOONGSON_INT_ROUTER_LPC = - LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0); - /* route HT1 int0 ~ int7 to cpu core0 INT1*/ - for (i = 0; i < 8; i++) - LOONGSON_INT_ROUTER_HT1(i) = - LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1); - /* enable HT1 interrupt */ - LOONGSON_HT1_INTN_EN(0) = 0xffffffff; - /* enable router interrupt intenset */ - LOONGSON_INT_ROUTER_INTENSET = - LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10; -} - -void __init arch_init_irq(void) -{ - struct irq_chip *chip; - - clear_c0_status(ST0_IM | ST0_BEV); - - irq_router_init(); - mips_cpu_irq_init(); - init_i8259_irqs(); - chip = irq_get_chip(I8259A_IRQ_BASE); - chip->irq_set_affinity = plat_set_irq_affinity; - - irq_set_chip_and_handler(LOONGSON_UART_IRQ, - &loongson_irq_chip, handle_percpu_irq); - irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ, - &loongson_irq_chip, handle_percpu_irq); - - set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6); -} - -#ifdef CONFIG_HOTPLUG_CPU - -void fixup_irqs(void) -{ - irq_cpu_offline(); - clear_c0_status(ST0_IM); -} - -#endif diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index de8e0741ce2d..e1fe8bbb377d 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -4,6 +4,7 @@ * Author: Chen Huacai, chenhc@lemote.com */ +#include #include #include #include @@ -25,6 +26,8 @@ DEFINE_PER_CPU(int, cpu_state); +#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) + static void *ipi_set0_regs[16]; static void *ipi_clear0_regs[16]; static void *ipi_status0_regs[16]; @@ -302,20 +305,13 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) ipi_write_action(cpu_logical_map(i), (u32)action); } -#define IPI_IRQ_OFFSET 6 - -void loongson3_send_irq_by_ipi(int cpu, int irqs) -{ - ipi_write_action(cpu_logical_map(cpu), irqs << IPI_IRQ_OFFSET); -} -void loongson3_ipi_interrupt(struct pt_regs *regs) +static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) { int i, cpu = smp_processor_id(); - unsigned int action, c0count, irqs; + unsigned int action, c0count; action = ipi_read_clear(cpu); - irqs = action >> IPI_IRQ_OFFSET; if (action & SMP_RESCHEDULE_YOURSELF) scheduler_ipi(); @@ -335,13 +331,7 @@ void loongson3_ipi_interrupt(struct pt_regs *regs) __wbflush(); /* Let others see the result ASAP */ } - if (irqs) { - int irq; - while ((irq = ffs(irqs))) { - do_IRQ(irq-1); - irqs &= ~(1<<(irq-1)); - } - } + return IRQ_HANDLED; } #define MAX_LOOPS 800 @@ -438,6 +428,9 @@ static void __init loongson3_smp_setup(void) static void __init loongson3_prepare_cpus(unsigned int max_cpus) { + if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt, + IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL)) + pr_err("Failed to request IPI IRQ\n"); init_cpu_present(cpu_possible_mask); per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; } @@ -484,7 +477,8 @@ static int loongson3_cpu_disable(void) set_cpu_online(cpu, false); calculate_cpu_foreign_map(); local_irq_save(flags); - fixup_irqs(); + irq_cpu_offline(); + clear_c0_status(ST0_IM); local_irq_restore(flags); local_flush_tlb_all(); From patchwork Sun Jan 12 08:14:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329061 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5EE57139A for ; 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Sun, 12 Jan 2020 11:15:49 +0300 (MSK) Received: from vla1-ee05250d997a.qloud-c.yandex.net (vla1-ee05250d997a.qloud-c.yandex.net [2a02:6b8:c0d:3495:0:640:ee05:250d]) by mxback7q.mail.yandex.net (mxback/Yandex) with ESMTP id l0SQQ7Tt4H-FnSSPSmi; Sun, 12 Jan 2020 11:15:49 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816949; bh=QIhdMgkkaehQmJ687iqyXti//3kLmXOE11eL6TIK7AQ=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=IxgJmRr+QopwRG702kawUvX1jf9hWuq4wEEpXZzJ55cq1WaVPwhjv/HKcxriCqJrP YXB5zHGEMhjnFGJ6tyAQldJCdBy7aQGE8PPNJtwM36ep7msn/FBjL21riRig+edWc+ IenDLdqlONv0aUqDH64rBTC658julr1zS0xyr6eU= Authentication-Results: mxback7q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-FgV4VGmv; Sun, 12 Jan 2020 11:15:47 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v3 08/10] dt-bindings: mips: Add loongson boards Date: Sun, 12 Jan 2020 16:14:14 +0800 Message-Id: <20200112081416.722218-9-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Prepare for later dts. Signed-off-by: Jiaxun Yang --- .../bindings/mips/loongson/devices.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml new file mode 100644 index 000000000000..3c7c59a29c1b --- /dev/null +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson based Platforms Device Tree Bindings + +maintainers: + - Jiaxun Yang +description: | + Devices with a Loongson CPU shall have the following properties. + Note that generic device is used for built-in dtbs and will be + patched during boot on firmware without OF support. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Generic Loongson3 4Core + RS780E + items: + - const: loongson,loongson3-4core-780e + + - description: Generic Loongson3 8Core + RS780E + items: + - const: loongson,loongson3-8core-780e +... From patchwork Sun Jan 12 08:14:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329077 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B9FBC1580 for ; Sun, 12 Jan 2020 08:22:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8F7D5214D8 for ; Sun, 12 Jan 2020 08:22:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="iS/Wa9Mu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732406AbgALIWP (ORCPT ); Sun, 12 Jan 2020 03:22:15 -0500 Received: from forward106j.mail.yandex.net ([5.45.198.249]:38382 "EHLO forward106j.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732380AbgALIWP (ORCPT ); Sun, 12 Jan 2020 03:22:15 -0500 Received: from forward103q.mail.yandex.net (forward103q.mail.yandex.net [IPv6:2a02:6b8:c0e:50:0:640:b21c:d009]) by forward106j.mail.yandex.net (Yandex) with ESMTP id 7AB3B11A0A31; Sun, 12 Jan 2020 11:16:25 +0300 (MSK) Received: from mxback8q.mail.yandex.net (mxback8q.mail.yandex.net [IPv6:2a02:6b8:c0e:42:0:640:b38f:32ec]) by forward103q.mail.yandex.net (Yandex) with ESMTP id 7395861E000A; Sun, 12 Jan 2020 11:16:25 +0300 (MSK) Received: from vla1-ee05250d997a.qloud-c.yandex.net (vla1-ee05250d997a.qloud-c.yandex.net [2a02:6b8:c0d:3495:0:640:ee05:250d]) by mxback8q.mail.yandex.net (mxback/Yandex) with ESMTP id x630NXtli7-GPpeQjPA; Sun, 12 Jan 2020 11:16:25 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816985; bh=+I+2B6DVh3pvC30SC/PFZ8sM04FtO0EJQ8OdPf7+0Hg=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=iS/Wa9MuAAbRyZ6I81eOjQIeLCHX0EdkTnBHC11/J2/IAkN6okfSyJbnT6cM9lZad lGyB6p37cRyZTXGCKGAcYW9wGoJEBYLAdFkFbkdzM7HdVHRSE+L9L/+uQ+Kxl2lYnT QL0UnSO6uZjVLceZfqAc3+DHcES9lwmDm5iQTGyM= Authentication-Results: mxback8q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-FnV41IQM; Sun, 12 Jan 2020 11:15:54 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v3 09/10] MIPS: Loongson64: Add generic dts Date: Sun, 12 Jan 2020 16:14:15 +0800 Message-Id: <20200112081416.722218-10-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add generic device dts for Loongson-3 devices. They seems identical but will be different later. Some PCH devices like PCI Host Bridge is still enabled by platform code for now. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 6 +- arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/loongson/Makefile | 5 ++ .../boot/dts/loongson/loongson3-package.dtsi | 62 +++++++++++++++++++ .../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++ .../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++ arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++ arch/mips/include/asm/mach-loongson64/irq.h | 3 +- 8 files changed, 150 insertions(+), 3 deletions(-) create mode 100644 arch/mips/boot/dts/loongson/Makefile create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4b83507499f4..47909e733c2d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -489,9 +489,11 @@ config MACH_LOONGSON64 select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_ZBOOT - select LOONGSON_MC146818 select ZONE_DMA32 select NUMA + select COMMON_CLK + select USE_OF + select BUILTIN_DTB help This enables the support of Loongson-2/3 family of machines. @@ -3085,7 +3087,7 @@ endchoice choice prompt "Kernel command line type" if !CMDLINE_OVERRIDE default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \ - !MIPS_MALTA && \ + !MACH_LOONGSON64 && !MIPS_MALTA && \ !CAVIUM_OCTEON_SOC default MIPS_CMDLINE_FROM_BOOTLOADER diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 1e79cab8e269..d429a69bfe30 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y += cavium-octeon subdir-y += img subdir-y += ingenic subdir-y += lantiq +subdir-y += loongson subdir-y += mscc subdir-y += mti subdir-y += netlogic diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile new file mode 100644 index 000000000000..c0cedbaa9a78 --- /dev/null +++ b/arch/mips/boot/dts/loongson/Makefile @@ -0,0 +1,5 @@ +# SPDX_License_Identifier: GPL_2.0 +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb\ + + +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi new file mode 100644 index 000000000000..8a8d8c442dfe --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + package0: bus@1fe00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 + 0 0x3ff00000 0 0x3ff00000 0x100000 + 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 /* 3A HT Config Space */ + 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000 /* 3B HT Config Space */>; + + iointc: interrupt-controller@3ff01400 { + compatible = "loongson,iointc-1.0"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>; + interrupt-names = "int0", "int1"; + + loongson,parent_int_map = <0xf0ffffff>, /* int0 */ + <0x0f000000>, /* int1 */ + <0x00000000>, /* int2 */ + <0x00000000>; /* int3 */ + + }; + + cpu_uart0: serial@1fe001e0 { + compatible = "ns16550a"; + reg = <0 0x1fe001e0 0x8>; + clock-frequency = <33000000>; + interrupt-parent = <&iointc>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + no-loopback-test; + }; + + cpu_uart1: serial@1fe001e8 { + status = "disabled"; + compatible = "ns16550a"; + reg = <0 0x1fe001e8 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&iointc>; + no-loopback-test; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts new file mode 100644 index 000000000000..ef50ed9a4d59 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson3-package.dtsi" +#include "rs780e-pch.dtsi" + +/ { + compatible = "loongson,loongson3-4core-780e"; +}; + +&package0 { + htpic: interrupt-controller@efdfb000080 { + compatible = "loongson,htpic-1.0"; + reg = <0xefd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts new file mode 100644 index 000000000000..409473f1751b --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson3-package.dtsi" +#include "rs780e-pch.dtsi" + +/ { + compatible = "loongson,loongson3-8core-780e"; +}; + +&package0 { + htpic: interrupt-controller@1efdfb000080 { + compatible = "loongson,htpic-1.0"; + reg = <0x1efd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi new file mode 100644 index 000000000000..45c54d555fa4 --- /dev/null +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + bus@10000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x10000000 0 0x10000000 0 0x10000000 + 0 0x40000000 0 0x40000000 0 0x40000000 + 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>; + + isa { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0 0x1000>; + + rtc0: rtc@70 { + compatible = "motorola,mc146818"; + reg = <1 0x70 0x8>; + interrupts = <8>; + interrupt-parent = <&htpic>; + }; + }; + }; +}; diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index 12208119aac0..20e3d4e67788 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -4,8 +4,9 @@ #include +#define NR_IRQS 512 /* cpu core interrupt numbers */ -#define MIPS_CPU_IRQ_BASE 56 +#define MIPS_CPU_IRQ_BASE 16 #include_next #endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */ From patchwork Sun Jan 12 08:14:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329081 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 836D2930 for ; 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Sun, 12 Jan 2020 11:16:37 +0300 (MSK) Received: from vla1-ee05250d997a.qloud-c.yandex.net (vla1-ee05250d997a.qloud-c.yandex.net [2a02:6b8:c0d:3495:0:640:ee05:250d]) by mxback1q.mail.yandex.net (mxback/Yandex) with ESMTP id Q7ZMkSEcVy-Gb8Gorow; Sun, 12 Jan 2020 11:16:37 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578816997; bh=ZF4UnfCbDyKUT35YCijKiYicTuas0pwMkPes6YsV4VA=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=rGO//L39Zj4/svE77D63WP2DeNDcMUQVQbRvIeL4hYCZtYiRD1yH6liD4+RE6Uvt3 U71+gxf/Ob8xe4zbGBrphlZHNVDmCBJr7Dll8MPqpvATeB3NDWtohrz8+JTOEl4eTz jNoMDCDTXIxiFEHwj7/2gjmxXkSyhq3fB7j8+iDQ= Authentication-Results: mxback1q.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by vla1-ee05250d997a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 3jM5RHRYtF-GPV4YZPD; Sun, 12 Jan 2020 11:16:30 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.co, devicetree@vger.kernel.org, Jiaxun Yang Subject: [PATCH v3 10/10] MIPS: Loongson64: Load built-in dtbs Date: Sun, 12 Jan 2020 16:14:16 +0800 Message-Id: <20200112081416.722218-11-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200112081416.722218-1-jiaxun.yang@flygoat.com> References: <20200112081416.722218-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Load proper dtb according to firmware passed parameters and CPU PRID. Signed-off-by: Jiaxun Yang --- .../asm/mach-loongson64/builtin_dtbs.h | 13 +++++++++++ .../include/asm/mach-loongson64/loongson.h | 1 + arch/mips/loongson64/env.c | 23 +++++++++++++++++++ arch/mips/loongson64/setup.c | 16 +++++++++++++ 4 files changed, 53 insertions(+) create mode 100644 arch/mips/include/asm/mach-loongson64/builtin_dtbs.h diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h new file mode 100644 index 000000000000..853c6d80887b --- /dev/null +++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019 Jiaxun Yang + * + * Built-in Generic dtbs for MACH_LOONGSON64 + */ + +#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ +#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ + +extern u32 __dtb_loongson3_4core_rs780e_begin[]; +extern u32 __dtb_loongson3_8core_rs780e_begin[]; +#endif diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h index a8fce112a9b0..fde1b75c45ea 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson.h +++ b/arch/mips/include/asm/mach-loongson64/loongson.h @@ -25,6 +25,7 @@ extern const struct plat_smp_ops loongson3_smp_ops; /* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); extern void __init prom_init_env(void); +extern void *loongson_fdt_blob; /* irq operation functions */ extern void mach_irq_dispatch(unsigned int pending); diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c index 0daeb7bcf023..2554ef11170d 100644 --- a/arch/mips/loongson64/env.c +++ b/arch/mips/loongson64/env.c @@ -17,6 +17,7 @@ #include #include #include +#include #include u32 cpu_clock_freq; @@ -120,6 +121,28 @@ void __init prom_init_env(void) loongson_sysconf.cores_per_node - 1) / loongson_sysconf.cores_per_node; + if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) { + switch (read_c0_prid() & PRID_REV_MASK) { + case PRID_REV_LOONGSON3A_R1: + case PRID_REV_LOONGSON3A_R2_0: + case PRID_REV_LOONGSON3A_R2_1: + case PRID_REV_LOONGSON3A_R3_0: + case PRID_REV_LOONGSON3A_R3_1: + loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin; + break; + case PRID_REV_LOONGSON3B_R1: + case PRID_REV_LOONGSON3B_R2: + loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin; + break; + default: + break; + } + } + + + if (!loongson_fdt_blob) + pr_err("Failed to determine built-in Loongson64 dtb\n"); + loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr; loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr; loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr; diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c index 4fd27f4f90ed..6fe3ffffcaa6 100644 --- a/arch/mips/loongson64/setup.c +++ b/arch/mips/loongson64/setup.c @@ -8,9 +8,15 @@ #include #include +#include +#include + +#include #include +void *loongson_fdt_blob; + static void wbflush_loongson(void) { asm(".set\tpush\n\t" @@ -27,4 +33,14 @@ EXPORT_SYMBOL(__wbflush); void __init plat_mem_setup(void) { + if (loongson_fdt_blob) + __dt_setup_arch(loongson_fdt_blob); +} + +void __init device_tree_init(void) +{ + if (!initial_boot_params) + return; + + unflatten_and_copy_device_tree(); }