From patchwork Mon Jan 13 16:43:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11330565 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E017B1398 for ; Mon, 13 Jan 2020 16:44:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4E0F2187F for ; Mon, 13 Jan 2020 16:44:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728939AbgAMQoZ (ORCPT ); Mon, 13 Jan 2020 11:44:25 -0500 Received: from out28-220.mail.aliyun.com ([115.124.28.220]:49709 "EHLO out28-220.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728753AbgAMQoY (ORCPT ); Mon, 13 Jan 2020 11:44:24 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436282|-1;CH=green;DM=CONTINUE|CONTINUE|true|0.421166-0.0238202-0.555013;DS=CONTINUE|ham_alarm|0.0276717-0.027558-0.94477;FP=0|0|0|0|0|-1|-1|-1;HT=e02c03301;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=25;RT=25;SR=0;TI=SMTPD_---.GbRhA7M_1578933839; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.GbRhA7M_1578933839) by smtp.aliyun-inc.com(10.147.40.233); Tue, 14 Jan 2020 00:44:10 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, miquel.raynal@bootlin.com, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, daniel.lezcano@linaro.org, ebiederm@xmission.com, keescook@chromium.org, ak@linux.intel.com, krzk@kernel.org, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 1/6] MIPS: JZ4780: Introduce SMP support. Date: Tue, 14 Jan 2020 00:43:28 +0800 Message-Id: <1578933813-80122-3-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Forward port smp support from kernel 3.18.3 of CI20_linux to upstream kernel 5.5. Signed-off-by: 周琰杰 (Zhou Yanjie) --- arch/mips/include/asm/mach-jz4740/jz4780-smp.h | 91 ++++++++ arch/mips/jz4740/Kconfig | 3 + arch/mips/jz4740/Makefile | 5 + arch/mips/jz4740/prom.c | 4 + arch/mips/jz4740/smp-entry.S | 57 +++++ arch/mips/jz4740/smp.c | 300 +++++++++++++++++++++++++ arch/mips/kernel/idle.c | 14 +- drivers/irqchip/irq-ingenic.c | 21 ++ 8 files changed, 494 insertions(+), 1 deletion(-) create mode 100644 arch/mips/include/asm/mach-jz4740/jz4780-smp.h create mode 100644 arch/mips/jz4740/smp-entry.S create mode 100644 arch/mips/jz4740/smp.c diff --git a/arch/mips/include/asm/mach-jz4740/jz4780-smp.h b/arch/mips/include/asm/mach-jz4740/jz4780-smp.h new file mode 100644 index 00000000..3f592ce --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/jz4780-smp.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2013, Paul Burton + * JZ4780 SMP definitions + */ + +#ifndef __MIPS_ASM_MACH_JZ4740_JZ4780_SMP_H__ +#define __MIPS_ASM_MACH_JZ4740_JZ4780_SMP_H__ + +#define read_c0_corectrl() __read_32bit_c0_register($12, 2) +#define write_c0_corectrl(val) __write_32bit_c0_register($12, 2, val) + +#define read_c0_corestatus() __read_32bit_c0_register($12, 3) +#define write_c0_corestatus(val) __write_32bit_c0_register($12, 3, val) + +#define read_c0_reim() __read_32bit_c0_register($12, 4) +#define write_c0_reim(val) __write_32bit_c0_register($12, 4, val) + +#define read_c0_mailbox0() __read_32bit_c0_register($20, 0) +#define write_c0_mailbox0(val) __write_32bit_c0_register($20, 0, val) + +#define read_c0_mailbox1() __read_32bit_c0_register($20, 1) +#define write_c0_mailbox1(val) __write_32bit_c0_register($20, 1, val) + +#define smp_clr_pending(mask) do { \ + unsigned int stat; \ + stat = read_c0_corestatus(); \ + stat &= ~((mask) & 0xff); \ + write_c0_corestatus(stat); \ + } while (0) + +/* + * Core Control register + */ +#define CORECTRL_SLEEP1M_SHIFT 17 +#define CORECTRL_SLEEP1M (_ULCAST_(0x1) << CORECTRL_SLEEP1M_SHIFT) +#define CORECTRL_SLEEP0M_SHIFT 16 +#define CORECTRL_SLEEP0M (_ULCAST_(0x1) << CORECTRL_SLEEP0M_SHIFT) +#define CORECTRL_RPC1_SHIFT 9 +#define CORECTRL_RPC1 (_ULCAST_(0x1) << CORECTRL_RPC1_SHIFT) +#define CORECTRL_RPC0_SHIFT 8 +#define CORECTRL_RPC0 (_ULCAST_(0x1) << CORECTRL_RPC0_SHIFT) +#define CORECTRL_SWRST1_SHIFT 1 +#define CORECTRL_SWRST1 (_ULCAST_(0x1) << CORECTRL_SWRST1_SHIFT) +#define CORECTRL_SWRST0_SHIFT 0 +#define CORECTRL_SWRST0 (_ULCAST_(0x1) << CORECTRL_SWRST0_SHIFT) + +/* + * Core Status register + */ +#define CORESTATUS_SLEEP1_SHIFT 17 +#define CORESTATUS_SLEEP1 (_ULCAST_(0x1) << CORESTATUS_SLEEP1_SHIFT) +#define CORESTATUS_SLEEP0_SHIFT 16 +#define CORESTATUS_SLEEP0 (_ULCAST_(0x1) << CORESTATUS_SLEEP0_SHIFT) +#define CORESTATUS_IRQ1P_SHIFT 9 +#define CORESTATUS_IRQ1P (_ULCAST_(0x1) << CORESTATUS_IRQ1P_SHIFT) +#define CORESTATUS_IRQ0P_SHIFT 8 +#define CORESTATUS_IRQ0P (_ULCAST_(0x1) << CORESTATUS_IRQ8P_SHIFT) +#define CORESTATUS_MIRQ1P_SHIFT 1 +#define CORESTATUS_MIRQ1P (_ULCAST_(0x1) << CORESTATUS_MIRQ1P_SHIFT) +#define CORESTATUS_MIRQ0P_SHIFT 0 +#define CORESTATUS_MIRQ0P (_ULCAST_(0x1) << CORESTATUS_MIRQ0P_SHIFT) + +/* + * Reset Entry & IRQ Mask register + */ +#define REIM_ENTRY_SHIFT 16 +#define REIM_ENTRY (_ULCAST_(0xffff) << REIM_ENTRY_SHIFT) +#define REIM_IRQ1M_SHIFT 9 +#define REIM_IRQ1M (_ULCAST_(0x1) << REIM_IRQ1M_SHIFT) +#define REIM_IRQ0M_SHIFT 8 +#define REIM_IRQ0M (_ULCAST_(0x1) << REIM_IRQ0M_SHIFT) +#define REIM_MBOXIRQ1M_SHIFT 1 +#define REIM_MBOXIRQ1M (_ULCAST_(0x1) << REIM_MBOXIRQ1M_SHIFT) +#define REIM_MBOXIRQ0M_SHIFT 0 +#define REIM_MBOXIRQ0M (_ULCAST_(0x1) << REIM_MBOXIRQ0M_SHIFT) + +#ifdef CONFIG_SMP + +extern void jz4780_smp_wait_irqoff(void); + +extern void jz4780_smp_init(void); +extern void jz4780_secondary_cpu_entry(void); + +#else /* !CONFIG_SMP */ + +static inline void jz4780_smp_init(void) { } + +#endif /* !CONFIG_SMP */ + +#endif /* __MIPS_ASM_MACH_JZ4740_JZ4780_SMP_H__ */ diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig index 412d2fa..0239597 100644 --- a/arch/mips/jz4740/Kconfig +++ b/arch/mips/jz4740/Kconfig @@ -34,9 +34,12 @@ config MACH_JZ4770 config MACH_JZ4780 bool + select GENERIC_CLOCKEVENTS_BROADCAST if SMP select MIPS_CPU_SCACHE + select NR_CPUS_DEFAULT_2 select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_SMP config MACH_X1000 bool diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile index 6de14c0..0a0f024 100644 --- a/arch/mips/jz4740/Makefile +++ b/arch/mips/jz4740/Makefile @@ -12,3 +12,8 @@ CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt # PM support obj-$(CONFIG_PM) += pm.o + +# SMP support + +obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SMP) += smp-entry.o diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c index ff4555c..a79159e 100644 --- a/arch/mips/jz4740/prom.c +++ b/arch/mips/jz4740/prom.c @@ -8,10 +8,14 @@ #include #include +#include void __init prom_init(void) { fw_init_cmdline(); +#if defined(CONFIG_MACH_JZ4780) && defined(CONFIG_SMP) + jz4780_smp_init(); +#endif } void __init prom_free_prom_memory(void) diff --git a/arch/mips/jz4740/smp-entry.S b/arch/mips/jz4740/smp-entry.S new file mode 100644 index 00000000..20049a3 --- /dev/null +++ b/arch/mips/jz4740/smp-entry.S @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2013, Paul Burton + * JZ4780 SMP entry point + */ + +#include +#include +#include +#include +#include + +#define CACHE_SIZE (32 * 1024) +#define CACHE_LINESIZE 32 + +.extern jz4780_cpu_entry_sp +.extern jz4780_cpu_entry_gp + +.section .text.smp-entry +.balign 0x10000 +.set noreorder +LEAF(jz4780_secondary_cpu_entry) + mtc0 zero, CP0_CAUSE + + li t0, ST0_CU0 + mtc0 t0, CP0_STATUS + + /* cache setup */ + li t0, KSEG0 + ori t1, t0, CACHE_SIZE + mtc0 zero, CP0_TAGLO, 0 +1: cache Index_Store_Tag_I, 0(t0) + cache Index_Store_Tag_D, 0(t0) + bne t0, t1, 1b + addiu t0, t0, CACHE_LINESIZE + + /* kseg0 cache attribute */ + mfc0 t0, CP0_CONFIG, 0 + ori t0, t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG, 0 + + /* pagemask */ + mtc0 zero, CP0_PAGEMASK, 0 + + /* retrieve sp */ + la t0, jz4780_cpu_entry_sp + lw sp, 0(t0) + + /* retrieve gp */ + la t0, jz4780_cpu_entry_gp + lw gp, 0(t0) + + /* jump to the kernel in kseg0 */ + la t0, smp_bootstrap + jr t0 + nop + END(jz4780_secondary_cpu_entry) diff --git a/arch/mips/jz4740/smp.c b/arch/mips/jz4740/smp.c new file mode 100644 index 00000000..d36e0b2 --- /dev/null +++ b/arch/mips/jz4740/smp.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2013, Paul Burton + * JZ4780 SMP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct clk *cpu_clock_gates[CONFIG_NR_CPUS] = { NULL }; + +u32 jz4780_cpu_entry_sp; +u32 jz4780_cpu_entry_gp; + +static struct cpumask cpu_running; + +static DEFINE_SPINLOCK(smp_lock); + +extern void (*r4k_blast_dcache)(void); + +/* + * The Ingenic jz4780 SMP variant has to write back dirty cache lines before + * executing wait. The CPU & cache clock will be gated until we return from + * the wait, and if another core attempts to access data from our data cache + * during this time then it will lock up. + */ +void jz4780_smp_wait_irqoff(void) +{ + unsigned long pending = read_c0_cause() & read_c0_status() & CAUSEF_IP; + + /* + * Going to idle has a significant overhead due to the cache flush so + * try to avoid it if we'll immediately be woken again due to an IRQ. + */ + if (!need_resched() && !pending) { + r4k_blast_dcache(); + + __asm__( + " .set push \n" + " .set mips3 \n" + " sync \n" + " wait \n" + " .set pop \n"); + } + + local_irq_enable(); +} + +static irqreturn_t mbox_handler(int irq, void *dev_id) +{ + int cpu = smp_processor_id(); + u32 action, status; + + spin_lock(&smp_lock); + + switch (cpu) { + case 0: + action = read_c0_mailbox0(); + write_c0_mailbox0(0); + break; + case 1: + action = read_c0_mailbox1(); + write_c0_mailbox1(0); + break; + default: + panic("unhandled cpu %d!", cpu); + } + + /* clear pending mailbox interrupt */ + status = read_c0_corestatus(); + status &= ~(CORESTATUS_MIRQ0P << cpu); + write_c0_corestatus(status); + + spin_unlock(&smp_lock); + + if (action & SMP_RESCHEDULE_YOURSELF) + scheduler_ipi(); + if (action & SMP_CALL_FUNCTION) + generic_smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +static struct irqaction mbox_action = { + .handler = mbox_handler, + .name = "core mailbox", + .flags = IRQF_PERCPU | IRQF_NO_THREAD, +}; + +static void jz4780_smp_setup(void) +{ + u32 addr, reim; + int cpu; + + reim = read_c0_reim(); + + for (cpu = 0; cpu < NR_CPUS; cpu++) { + __cpu_number_map[cpu] = cpu; + __cpu_logical_map[cpu] = cpu; + set_cpu_possible(cpu, true); + } + + /* mask mailbox interrupts for this core */ + reim &= ~REIM_MBOXIRQ0M; + write_c0_reim(reim); + + /* clear mailboxes & pending mailbox IRQs */ + write_c0_mailbox0(0); + write_c0_mailbox1(0); + write_c0_corestatus(0); + + /* set reset entry point */ + addr = KSEG1ADDR((u32)&jz4780_secondary_cpu_entry); + WARN_ON(addr & ~REIM_ENTRY); + reim &= ~REIM_ENTRY; + reim |= addr & REIM_ENTRY; + + /* unmask mailbox interrupts for this core */ + reim |= REIM_MBOXIRQ0M; + write_c0_reim(reim); + set_c0_status(STATUSF_IP3); + irq_enable_hazard(); + + cpumask_set_cpu(cpu, &cpu_running); +} + +static void jz4780_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *cpu_node; + unsigned cpu, ctrl; + int err; + + /* setup the mailbox IRQ */ + setup_irq(MIPS_CPU_IRQ_BASE + 3, &mbox_action); + + init_cpu_present(cpu_possible_mask); + + ctrl = read_c0_corectrl(); + + for (cpu = 0; cpu < max_cpus; cpu++) { + /* use reset entry point from REIM register */ + ctrl |= CORECTRL_RPC0 << cpu; + } + + for_each_compatible_node(cpu_node, NULL, "ingenic,xburst") { + err = of_property_read_u32_index(cpu_node, "reg", 0, &cpu); + if (err) { + pr_err("Failed to read index of %s\n", + cpu_node->full_name); + continue; + } + + cpu_clock_gates[cpu] = of_clk_get(cpu_node, 0); + if (IS_ERR(cpu_clock_gates[cpu])) { + cpu_clock_gates[cpu] = NULL; + continue; + } + + err = clk_prepare(cpu_clock_gates[cpu]); + if (err) + pr_err("Failed to prepare CPU clock gate\n"); + } + + write_c0_corectrl(ctrl); +} + +static int jz4780_boot_secondary(int cpu, struct task_struct *idle) +{ + unsigned long flags; + u32 ctrl; + + spin_lock_irqsave(&smp_lock, flags); + + /* ensure the core is in reset */ + ctrl = read_c0_corectrl(); + ctrl |= CORECTRL_SWRST0 << cpu; + write_c0_corectrl(ctrl); + + /* ungate core clock */ + if (cpu_clock_gates[cpu]) + clk_enable(cpu_clock_gates[cpu]); + + /* power up the core */ + { + void __iomem *lpcr = (void __iomem *)0xb0000004; + void __iomem *clkgr1 = (void __iomem *)0xb0000028; + + writel(readl(lpcr) & ~BIT(31), lpcr); + writel(readl(clkgr1) & ~BIT(15), clkgr1); + + /* wait for the CPU to be powered up */ + while (readl(lpcr) & BIT(27)) + ; + } + + /* set entry sp/gp register values */ + jz4780_cpu_entry_sp = __KSTK_TOS(idle); + jz4780_cpu_entry_gp = (u32)task_thread_info(idle); + smp_wmb(); + + /* take the core out of reset */ + ctrl &= ~(CORECTRL_SWRST0 << cpu); + write_c0_corectrl(ctrl); + + cpumask_set_cpu(cpu, &cpu_running); + + spin_unlock_irqrestore(&smp_lock, flags); + + return 0; +} + +static void jz4780_init_secondary(void) +{ +} + +static void jz4780_smp_finish(void) +{ + u32 reim; + + spin_lock(&smp_lock); + + /* unmask mailbox interrupts for this core */ + reim = read_c0_reim(); + reim |= REIM_MBOXIRQ0M << smp_processor_id(); + write_c0_reim(reim); + + spin_unlock(&smp_lock); + + /* unmask interrupts for this core */ + change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP2 | + STATUSF_IP1 | STATUSF_IP0); + irq_enable_hazard(); + + /* force broadcast timer */ + tick_broadcast_force(); +} + +static void jz4780_send_ipi_single_locked(int cpu, unsigned int action) +{ + u32 mbox; + + switch (cpu) { + case 0: + mbox = read_c0_mailbox0(); + write_c0_mailbox0(mbox | action); + break; + case 1: + mbox = read_c0_mailbox1(); + write_c0_mailbox1(mbox | action); + break; + default: + panic("unhandled cpu %d!", cpu); + } +} + +static void jz4780_send_ipi_single(int cpu, unsigned int action) +{ + unsigned long flags; + + spin_lock_irqsave(&smp_lock, flags); + jz4780_send_ipi_single_locked(cpu, action); + spin_unlock_irqrestore(&smp_lock, flags); +} + +static void jz4780_send_ipi_mask(const struct cpumask *mask, + unsigned int action) +{ + unsigned long flags; + int cpu; + + spin_lock_irqsave(&smp_lock, flags); + + for_each_cpu(cpu, mask) + jz4780_send_ipi_single_locked(cpu, action); + + spin_unlock_irqrestore(&smp_lock, flags); +} + +static struct plat_smp_ops jz4780_smp_ops = { + .send_ipi_single = jz4780_send_ipi_single, + .send_ipi_mask = jz4780_send_ipi_mask, + .init_secondary = jz4780_init_secondary, + .smp_finish = jz4780_smp_finish, + .boot_secondary = jz4780_boot_secondary, + .smp_setup = jz4780_smp_setup, + .prepare_cpus = jz4780_smp_prepare_cpus, +}; + +void jz4780_smp_init(void) +{ + register_smp_ops(&jz4780_smp_ops); +} diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 37f8e78..a406de3 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -19,6 +19,10 @@ #include #include +#ifdef CONFIG_MACH_JZ4780 +# include +#endif + /* * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, * the implementation of the "wait" feature differs between CPU families. This @@ -172,7 +176,6 @@ void __init check_wait(void) case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: case CPU_CAVIUM_OCTEON3: - case CPU_XBURST: case CPU_LOONGSON32: case CPU_XLR: case CPU_XLP: @@ -246,6 +249,15 @@ void __init check_wait(void) cpu_wait = r4k_wait; */ break; + case CPU_XBURST: +#if defined(CONFIG_MACH_JZ4780) && defined(CONFIG_SMP) + if (NR_CPUS > 1) + cpu_wait = jz4780_smp_wait_irqoff; + else + cpu_wait = r4k_wait; +#else + cpu_wait = r4k_wait; +#endif default: break; } diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c index 01d18b3..56a9648 100644 --- a/drivers/irqchip/irq-ingenic.c +++ b/drivers/irqchip/irq-ingenic.c @@ -17,6 +17,7 @@ #include #include +#include #include struct ingenic_intc_data { @@ -32,6 +33,26 @@ struct ingenic_intc_data { #define JZ_REG_INTC_PENDING 0x10 #define CHIP_SIZE 0x20 +asmlinkage void plat_irq_dispatch(void) +{ + uint32_t pending = read_c0_cause() & read_c0_status() & CAUSEF_IP; + + if (pending & CAUSEF_IP4) { + /* from OS timer */ + do_IRQ(4); +#ifdef CONFIG_SMP + } else if (pending & CAUSEF_IP3) { + /* from a mailbox write */ + do_IRQ(3); +#endif + } else if (pending & CAUSEF_IP2) { + /* from interrupt controller */ + do_IRQ(2); + } else { + spurious_interrupt(); + } +} + static irqreturn_t intc_cascade(int irq, void *data) { struct ingenic_intc_data *intc = irq_get_handler_data(irq); From patchwork Mon Jan 13 16:43:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11330567 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D574C92A for ; Mon, 13 Jan 2020 16:44:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B34C021739 for ; Mon, 13 Jan 2020 16:44:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728775AbgAMQoY (ORCPT ); Mon, 13 Jan 2020 11:44:24 -0500 Received: from out28-149.mail.aliyun.com ([115.124.28.149]:41157 "EHLO out28-149.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726567AbgAMQoY (ORCPT ); Mon, 13 Jan 2020 11:44:24 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07436282|-1;CH=green;DM=CONTINUE|CONTINUE|true|0.104935-0.00692224-0.888143;DS=CONTINUE|ham_alarm|0.00659935-0.00134675-0.992054;FP=0|0|0|0|0|-1|-1|-1;HT=e02c03303;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=25;RT=25;SR=0;TI=SMTPD_---.GbRhA7M_1578933839; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.GbRhA7M_1578933839) by smtp.aliyun-inc.com(10.147.40.233); Tue, 14 Jan 2020 00:44:12 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, miquel.raynal@bootlin.com, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, daniel.lezcano@linaro.org, ebiederm@xmission.com, keescook@chromium.org, ak@linux.intel.com, krzk@kernel.org, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 2/6] clocksource: Ingenic: Add high resolution timer support for SMP. Date: Tue, 14 Jan 2020 00:43:29 +0800 Message-Id: <1578933813-80122-4-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Enable clock event handling on per CPU core basis. Make sure that interrupts raised on the first core execute event handlers on the correct CPU core. Signed-off-by: 周琰杰 (Zhou Yanjie) --- drivers/clocksource/ingenic-timer.c | 114 +++++++++++++++++++++++++++++------- 1 file changed, 93 insertions(+), 21 deletions(-) diff --git a/drivers/clocksource/ingenic-timer.c b/drivers/clocksource/ingenic-timer.c index 4bbdb3d..1d32652 100644 --- a/drivers/clocksource/ingenic-timer.c +++ b/drivers/clocksource/ingenic-timer.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * JZ47xx SoCs TCU IRQ driver + * XBurst SoCs TCU IRQ driver * Copyright (C) 2019 Paul Cercueil + * Copyright (C) 2020 周琰杰 (Zhou Yanjie) */ #include @@ -27,12 +28,15 @@ struct ingenic_soc_info { struct ingenic_tcu { struct regmap *map; + struct device_node *np; struct clk *timer_clk, *cs_clk; + unsigned int timer_local[NR_CPUS]; unsigned int timer_channel, cs_channel; struct clock_event_device cevt; struct clocksource cs; - char name[4]; + char name[16]; unsigned long pwm_channels_mask; + int cpu; }; static struct ingenic_tcu *ingenic_tcu; @@ -81,6 +85,30 @@ static int ingenic_tcu_cevt_set_next(unsigned long next, return 0; } +static void ingenic_per_cpu_event_handle(void *info) +{ + struct clock_event_device *cevt = (struct clock_event_device *) info; + + if (cevt->event_handler) + cevt->event_handler(cevt); +} + +static void ingenic_tcu_per_cpu_cb(struct clock_event_device *evt) +{ + struct clock_event_device *cevt = evt; + struct ingenic_tcu *tcu = to_ingenic_tcu(evt); + + if (smp_processor_id() == tcu->cpu) { + if (cevt->event_handler) + cevt->event_handler(cevt); + } else { + arch_local_irq_enable(); + smp_call_function_single(tcu->cpu, + ingenic_per_cpu_event_handle, (void *) cevt, 0); + arch_local_irq_disable(); + } +} + static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; @@ -88,8 +116,7 @@ static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id) regmap_write(tcu->map, TCU_REG_TECR, BIT(tcu->timer_channel)); - if (evt->event_handler) - evt->event_handler(evt); + ingenic_tcu_per_cpu_cb(evt); return IRQ_HANDLED; } @@ -105,15 +132,23 @@ static struct clk * __init ingenic_tcu_get_clock(struct device_node *np, int id) return of_clk_get_from_provider(&args); } -static int __init ingenic_tcu_timer_init(struct device_node *np, - struct ingenic_tcu *tcu) +static int ingenic_tcu_setup_cevt(struct device_node *np, + unsigned int channel) { - unsigned int timer_virq, channel = tcu->timer_channel; + unsigned int timer_virq; struct irq_domain *domain; + struct ingenic_tcu *tcu; unsigned long rate; int err; + tcu = kzalloc(sizeof(*tcu), GFP_KERNEL); + if (!tcu) + return -ENOMEM; + + tcu->map = ingenic_tcu->map; + tcu->timer_clk = ingenic_tcu_get_clock(np, channel); + if (IS_ERR(tcu->timer_clk)) return PTR_ERR(tcu->timer_clk); @@ -139,13 +174,15 @@ static int __init ingenic_tcu_timer_init(struct device_node *np, goto err_clk_disable; } - snprintf(tcu->name, sizeof(tcu->name), "TCU"); + snprintf(tcu->name, sizeof(tcu->name), "TCU channel.%u", channel); err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER, tcu->name, &tcu->cevt); if (err) goto err_irq_dispose_mapping; + tcu->cpu = smp_processor_id(); + tcu->timer_channel = channel; tcu->cevt.cpumask = cpumask_of(smp_processor_id()); tcu->cevt.features = CLOCK_EVT_FEAT_ONESHOT; tcu->cevt.name = tcu->name; @@ -233,12 +270,32 @@ static const struct of_device_id ingenic_tcu_of_match[] = { { /* sentinel */ } }; +static int register_cpu_online(unsigned int cpu) +{ + int ret; + + ret = ingenic_tcu_setup_cevt(ingenic_tcu->np, + ingenic_tcu->timer_local[cpu]); + if (ret) + goto err_tcu_clocksource_cleanup; + + return 0; + +err_tcu_clocksource_cleanup: + clocksource_unregister(&ingenic_tcu->cs); + clk_disable_unprepare(ingenic_tcu->cs_clk); + clk_put(ingenic_tcu->cs_clk); + kfree(ingenic_tcu); + return ret; +} + static int __init ingenic_tcu_init(struct device_node *np) { const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np); const struct ingenic_soc_info *soc_info = id->data; struct ingenic_tcu *tcu; struct regmap *map; + unsigned cpu = 0; long rate; int ret; @@ -253,12 +310,14 @@ static int __init ingenic_tcu_init(struct device_node *np) return -ENOMEM; /* Enable all TCU channels for PWM use by default except channels 0/1 */ - tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, 2); + tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, + NR_CPUS + 1); of_property_read_u32(np, "ingenic,pwm-channels-mask", (u32 *)&tcu->pwm_channels_mask); /* Verify that we have at least two free channels */ - if (hweight8(tcu->pwm_channels_mask) > soc_info->num_channels - 2) { + if (hweight8(tcu->pwm_channels_mask) > + soc_info->num_channels - NR_CPUS + 1) { pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__, tcu->pwm_channels_mask); ret = -EINVAL; @@ -266,13 +325,29 @@ static int __init ingenic_tcu_init(struct device_node *np) } tcu->map = map; + tcu->np = np; ingenic_tcu = tcu; - tcu->timer_channel = find_first_zero_bit(&tcu->pwm_channels_mask, + tcu->timer_local[cpu] = find_first_zero_bit(&tcu->pwm_channels_mask, soc_info->num_channels); - tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask, - soc_info->num_channels, - tcu->timer_channel + 1); + + if (NR_CPUS > 1) { + for (cpu = 1; cpu < NR_CPUS; cpu++) + tcu->timer_local[cpu] = find_next_zero_bit( + &tcu->pwm_channels_mask, + soc_info->num_channels, + tcu->timer_local[cpu - 1] + 1); + + tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask, + soc_info->num_channels, + tcu->timer_local[cpu-1] + 1); + } else { + tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask, + soc_info->num_channels, + tcu->timer_local[cpu] + 1); + } + + ret = ingenic_tcu_clocksource_init(np, tcu); if (ret) { @@ -280,9 +355,10 @@ static int __init ingenic_tcu_init(struct device_node *np) goto err_free_ingenic_tcu; } - ret = ingenic_tcu_timer_init(np, tcu); - if (ret) - goto err_tcu_clocksource_cleanup; + /* Setup clock events on each CPU core */ + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "Ingenic XBurst: online", + register_cpu_online, NULL); + WARN_ON(ret < 0); /* Register the sched_clock at the end as there's no way to undo it */ rate = clk_get_rate(tcu->cs_clk); @@ -290,10 +366,6 @@ static int __init ingenic_tcu_init(struct device_node *np) return 0; -err_tcu_clocksource_cleanup: - clocksource_unregister(&tcu->cs); - clk_disable_unprepare(tcu->cs_clk); - clk_put(tcu->cs_clk); err_free_ingenic_tcu: kfree(tcu); return ret; From patchwork Mon Jan 13 16:43:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11330569 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4ED811398 for ; Mon, 13 Jan 2020 16:44:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 36A5621739 for ; Mon, 13 Jan 2020 16:44:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728868AbgAMQoX (ORCPT ); Mon, 13 Jan 2020 11:44:23 -0500 Received: from out28-49.mail.aliyun.com ([115.124.28.49]:56635 "EHLO out28-49.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728775AbgAMQoX (ORCPT ); Mon, 13 Jan 2020 11:44:23 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.4632446|-1;CH=green;DM=CONTINUE|CONTINUE|true|0.571545-0.0205303-0.407925;DS=CONTINUE|ham_enroll_verification|0.0125564-0.000309334-0.987134;FP=0|0|0|0|0|-1|-1|-1;HT=e01l07389;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=25;RT=25;SR=0;TI=SMTPD_---.GbRhA7M_1578933839; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.GbRhA7M_1578933839) by smtp.aliyun-inc.com(10.147.40.233); Tue, 14 Jan 2020 00:44:13 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, miquel.raynal@bootlin.com, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, daniel.lezcano@linaro.org, ebiederm@xmission.com, keescook@chromium.org, ak@linux.intel.com, krzk@kernel.org, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding. Date: Tue, 14 Jan 2020 00:43:30 +0800 Message-Id: <1578933813-80122-5-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Document the available properties for the SoC root node and the CPU nodes of the devicetree for the Ingenic XBurst SoCs. Signed-off-by: 周琰杰 (Zhou Yanjie) --- .../bindings/mips/ingenic/ingenic,cpu.txt | 32 ++++++++++++++++++++++ .../bindings/mips/ingenic/ingenic,soc,txt | 18 ++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt new file mode 100644 index 00000000..f23e9be --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt @@ -0,0 +1,32 @@ +Bindings for Ingenic XBurst family CPUs. + +Required properties: +- device_type: Must be "cpu". +- compatible: One of: + - "ingenic,xburst". + - "ingenic,xburst2". +- reg: The number of the CPU. + +Example: +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <0>; + + clocks = <&cgu JZ4780_CLK_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <1>; + + clocks = <&cgu JZ4780_CLK_CORE1>; + clock-names = "cpu"; + }; +}; diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt new file mode 100644 index 00000000..c731fa3 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt @@ -0,0 +1,18 @@ +Bindings for Ingenic SoCs with XBurst CPU inside. + +Required properties: +- compatible: One of: + - "ingenic,jz4740". + - "ingenic,jz4725b". + - "ingenic,jz4760". + - "ingenic,jz4760b". + - "ingenic,jz4770". + - "ingenic,jz4780". + - "ingenic,x1000". + - "ingenic,x1000e". + - "ingenic,x1500". + +Example: +#address-cells = <1>; +#size-cells = <1>; +compatible = "ingenic,jz4780"; From patchwork Mon Jan 13 16:43:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11330575 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B1C996C1 for ; Mon, 13 Jan 2020 16:45:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 98B9420678 for ; Mon, 13 Jan 2020 16:45:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728733AbgAMQpT (ORCPT ); Mon, 13 Jan 2020 11:45:19 -0500 Received: from out28-49.mail.aliyun.com ([115.124.28.49]:46544 "EHLO out28-49.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728753AbgAMQpS (ORCPT ); Mon, 13 Jan 2020 11:45:18 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07450532|-1;CH=green;DM=CONTINUE|CONTINUE|true|0.19843-0.0103649-0.791205;DS=CONTINUE|ham_system_inform|0.028472-0.000402336-0.971126;FP=0|0|0|0|0|-1|-1|-1;HT=e02c03302;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=25;RT=25;SR=0;TI=SMTPD_---.GbRhA7M_1578933839; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.GbRhA7M_1578933839) by smtp.aliyun-inc.com(10.147.40.233); Tue, 14 Jan 2020 00:44:15 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, miquel.raynal@bootlin.com, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, daniel.lezcano@linaro.org, ebiederm@xmission.com, keescook@chromium.org, ak@linux.intel.com, krzk@kernel.org, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 4/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs. Date: Tue, 14 Jan 2020 00:43:31 +0800 Message-Id: <1578933813-80122-6-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add 'cpus' node to the jz4740.dtsi, jz4770.dtsi, jz4780.dtsi and x1000.dtsi files. Signed-off-by: 周琰杰 (Zhou Yanjie) --- arch/mips/boot/dts/ingenic/jz4740.dtsi | 14 ++++++++++++++ arch/mips/boot/dts/ingenic/jz4770.dtsi | 15 ++++++++++++++- arch/mips/boot/dts/ingenic/jz4780.dtsi | 23 +++++++++++++++++++++++ arch/mips/boot/dts/ingenic/x1000.dtsi | 14 ++++++++++++++ 4 files changed, 65 insertions(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi index 5accda2..9627d95 100644 --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi @@ -6,6 +6,20 @@ #size-cells = <1>; compatible = "ingenic,jz4740"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <0>; + + clocks = <&cgu JZ4740_CLK_CCLK>; + clock-names = "cpu"; + }; + }; + cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi index 0bfb9ed..1b8114d 100644 --- a/arch/mips/boot/dts/ingenic/jz4770.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0 - #include / { @@ -7,6 +6,20 @@ #size-cells = <1>; compatible = "ingenic,jz4770"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <0>; + + clocks = <&cgu JZ4770_CLK_CCLK>; + clock-names = "cpu"; + }; + }; + cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index f928329..93a0604 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -7,6 +7,29 @@ #size-cells = <1>; compatible = "ingenic,jz4780"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <0>; + + clocks = <&cgu JZ4780_CLK_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <1>; + + clocks = <&cgu JZ4780_CLK_CORE1>; + clock-names = "cpu"; + }; + }; + cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi index 61061a4..ea54263 100644 --- a/arch/mips/boot/dts/ingenic/x1000.dtsi +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi @@ -7,6 +7,20 @@ #size-cells = <1>; compatible = "ingenic,x1000", "ingenic,x1000e"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <0>; + + clocks = <&cgu X1000_CLK_CPU>; + clock-names = "cpu"; + }; + }; + cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; From patchwork Mon Jan 13 16:43:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11330571 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C445C13BD for ; Mon, 13 Jan 2020 16:44:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A298121739 for ; Mon, 13 Jan 2020 16:44:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728787AbgAMQog (ORCPT ); Mon, 13 Jan 2020 11:44:36 -0500 Received: from out28-51.mail.aliyun.com ([115.124.28.51]:51671 "EHLO out28-51.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728774AbgAMQof (ORCPT ); Mon, 13 Jan 2020 11:44:35 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.08580225|-1;CH=green;DM=CONTINUE|CONTINUE|true|0.258727-0.0162396-0.725034;DS=CONTINUE|ham_system_inform|0.080439-0.00417079-0.91539;FP=0|0|0|0|0|-1|-1|-1;HT=e02c03279;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=25;RT=25;SR=0;TI=SMTPD_---.GbRhA7M_1578933839; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.GbRhA7M_1578933839) by smtp.aliyun-inc.com(10.147.40.233); Tue, 14 Jan 2020 00:44:17 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, miquel.raynal@bootlin.com, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, daniel.lezcano@linaro.org, ebiederm@xmission.com, keescook@chromium.org, ak@linux.intel.com, krzk@kernel.org, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 5/6] MIPS: CI20: Modify DTS to support high resolution timer for SMP. Date: Tue, 14 Jan 2020 00:43:32 +0800 Message-Id: <1578933813-80122-7-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Modify DTS, change tcu channel from 2 to 3, channel #0 and #1 for per core local timer, #2 for clocksource. Signed-off-by: 周琰杰 (Zhou Yanjie) --- arch/mips/boot/dts/ingenic/ci20.dts | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 37b9316..98c4c42 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -456,6 +456,13 @@ &tcu { /* 3 MHz for the system timer and clocksource */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; - assigned-clock-rates = <3000000>, <3000000>; + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>; + assigned-clock-rates = <3000000>, <3000000>, <750000>; + + /* + * Use channel #0 and #1 for the per core system timer, + * and use channel #2 for the clocksource. + */ + ingenic,pwm-channels-mask = <0xF8>; }; From patchwork Mon Jan 13 16:43:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11330573 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D2AD692A for ; Mon, 13 Jan 2020 16:44:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B244421739 for ; Mon, 13 Jan 2020 16:44:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728984AbgAMQog (ORCPT ); Mon, 13 Jan 2020 11:44:36 -0500 Received: from out28-51.mail.aliyun.com ([115.124.28.51]:46768 "EHLO out28-51.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728777AbgAMQog (ORCPT ); Mon, 13 Jan 2020 11:44:36 -0500 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.2512184|-1;CH=green;DM=CONTINUE|CONTINUE|true|0.0266138-0.00157687-0.971809;DS=CONTINUE|ham_system_inform|0.0297817-0.00180406-0.968414;FP=0|0|0|0|0|-1|-1|-1;HT=e01a16378;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=25;RT=25;SR=0;TI=SMTPD_---.GbRhA7M_1578933839; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.GbRhA7M_1578933839) by smtp.aliyun-inc.com(10.147.40.233); Tue, 14 Jan 2020 00:44:19 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, miquel.raynal@bootlin.com, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, daniel.lezcano@linaro.org, ebiederm@xmission.com, keescook@chromium.org, ak@linux.intel.com, krzk@kernel.org, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 6/6] MIPS: CI20: Update defconfig to support SMP. Date: Tue, 14 Jan 2020 00:43:33 +0800 Message-Id: <1578933813-80122-8-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add "CONFIG_SMP=y" and "CONFIG_NR_CPUS=2" to support SMP. Signed-off-by: 周琰杰 (Zhou Yanjie) --- arch/mips/configs/ci20_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index be41df2..3aadb2e 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -1,3 +1,5 @@ +CONFIG_SMP=y +CONFIG_NR_CPUS=2 # CONFIG_LOCALVERSION_AUTO is not set CONFIG_KERNEL_XZ=y CONFIG_SYSVIPC=y