From patchwork Mon Jan 13 21:07:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Cooper X-Patchwork-Id: 11330881 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F1F481398 for ; Mon, 13 Jan 2020 21:07:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D00A324658 for ; Mon, 13 Jan 2020 21:07:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="utfA3alr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728680AbgAMVHv (ORCPT ); Mon, 13 Jan 2020 16:07:51 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:45411 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726086AbgAMVHu (ORCPT ); Mon, 13 Jan 2020 16:07:50 -0500 Received: by mail-pl1-f196.google.com with SMTP id b22so4292305pls.12; Mon, 13 Jan 2020 13:07:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LyQkYDM/KZKONjplFnyoxpxnLT5IGwQv8MiMr7YPN3I=; b=utfA3alrv7tHpghnKdkmJ3E0IqLvR/zXbdnViKLkrLfW8ko7gw7GTfXLrgEkbIqSJe OmHci07hmtJ8jlSGaF8s1zDVjPIzQbipUsLUzcvg4+SmZNpGatNqyPmtr4yXj5HXue9w v+le4kOlRgwDbA7LBe4l6BQhXCP+r7kjMT7xUiEmxzx6IYN+SGFsaTbYx6zfeKDTOSE3 QtJB3IIApfjxmV/26ONJgL9AMVrAS5+lJNBUc25L8k0i0m0dkVyHBKAeM9wZkok2+SRZ bp1R7RwtXcAXMCWfGMM4Ej4kts9WxU5aHmRNFNAidPjM9ZZjSZVaBdYTKjYI9xzrHzX4 LKGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LyQkYDM/KZKONjplFnyoxpxnLT5IGwQv8MiMr7YPN3I=; b=bmQelJIxYO49s4259czJBJ5LNRvwRe0S2x6fR5C4IpKWiBtfY8UM7lHZT1FdxCgXCz 5+yqG1+FK8mfUpDgh4EqCr7IdfJqhzeVtnzTv3S72JWbCfdsn0vb19N88z+/K/0Vp5py GPM+0u6bhv7jhWvF5EueUG1srb74WBL0VB4aBs41Pjh4i/SoNNRbOdjMJbrr7kj8ocpo K8KyJHlQRDqV52sJl0PDGRn3OM/mW60/mRj9+00RKqxhlZgJbb/LNaNbxR7+5v1p2oOu SdrFpPE7F69p7+jTZemYpT7U4ZVks9wlcs3ei8MLjdFFxEPS5PGCoYnfGBV6U2dWHbFd JNiQ== X-Gm-Message-State: APjAAAXDdQFvTBPSgFMFi4fXVq+E2nfNU+ELGfXBSdy/ZPTAp/t46vVF ct/RXtssMjmbRQeT1qwzHXjDeqml8il7og== X-Google-Smtp-Source: APXvYqzliCyBk9qFpUk4+wdWthbVhifyZvXlrNnXV9vrs6fPOu67hIWB75V3MJEl+WkyzYcNilvw3g== X-Received: by 2002:a17:90a:9b88:: with SMTP id g8mr24522340pjp.72.1578949669444; Mon, 13 Jan 2020 13:07:49 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id s1sm14195827pgv.87.2020.01.13.13.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2020 13:07:49 -0800 (PST) From: Al Cooper To: linux-kernel@vger.kernel.org Cc: Al Cooper , Adrian Hunter , Andrew Jeffery , bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, "Enrico Weigelt, metux IT consult" , Faiz Abbas , Florian Fainelli , linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, Manivannan Sadhasivam , Mark Rutland , Rob Herring , Sowjanya Komatineni , Takao Orito , Ulf Hansson , YueHaibing Subject: [PATCH 1/6] dt-bindings: mmc: brcm,sdhci-brcmstb: Add support for 7216b0 Date: Mon, 13 Jan 2020 16:07:01 -0500 Message-Id: <20200113210706.11972-2-alcooperx@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200113210706.11972-1-alcooperx@gmail.com> References: <20200113210706.11972-1-alcooperx@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add 7216b0 with supports CQE, HS400, HS400-ES and SDR104. Signed-off-by: Al Cooper --- .../bindings/mmc/brcm,sdhci-brcmstb.txt | 41 +++++++++++++------ 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt index 733b64a4d8eb..ae2074184528 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt @@ -11,28 +11,43 @@ Required properties: - compatible: should be one of the following - "brcm,bcm7425-sdhci" - "brcm,bcm7445-sdhci" + - "brcm,bcm7216-sdhci" Refer to clocks/clock-bindings.txt for generic clock consumer properties. Example: - sdhci@f03e0100 { - compatible = "brcm,bcm7425-sdhci"; - reg = <0xf03e0000 0x100>; - interrupts = <0x0 0x26 0x0>; - sdhci,auto-cmd12; - clocks = <&sw_sdio>; + sdhci@84b0000 { sd-uhs-sdr50; sd-uhs-ddr50; + sd-uhs-sdr104; + sdhci,auto-cmd12; + compatible = "brcm,bcm7216-sdhci", + "brcm,bcm7445-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x84b0000 0x260 0x84b0300 0x200>; + reg-names = "host", "cfg"; + interrupts = <0x0 0x26 0x4>; + interrupt-names = "sdio0_0"; + clocks = <&scmi_clk 245>; + clock-names = "sw_sdio"; }; - sdhci@f03e0300 { + sdhci@84b1000 { + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + supports-cqe; non-removable; bus-width = <0x8>; - compatible = "brcm,bcm7425-sdhci"; - reg = <0xf03e0200 0x100>; - interrupts = <0x0 0x27 0x0>; - sdhci,auto-cmd12; - clocks = ; - mmc-hs200-1_8v; + compatible = "brcm,bcm7216-sdhci", + "brcm,bcm7445-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x84b1000 0x260 0x84b1300 0x200>; + reg-names = "host", "cfg"; + interrupts = <0x0 0x27 0x4>; + interrupt-names = "sdio1_0"; + clocks = <&scmi_clk 245>; + clock-names = "sw_sdio"; }; From patchwork Mon Jan 13 21:07:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Cooper X-Patchwork-Id: 11330883 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CAA3B1398 for ; Mon, 13 Jan 2020 21:07:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9E15724658 for ; Mon, 13 Jan 2020 21:07:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="imf2N9GC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726086AbgAMVHz (ORCPT ); Mon, 13 Jan 2020 16:07:55 -0500 Received: from mail-pj1-f66.google.com ([209.85.216.66]:39443 "EHLO mail-pj1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728769AbgAMVHx (ORCPT ); Mon, 13 Jan 2020 16:07:53 -0500 Received: by mail-pj1-f66.google.com with SMTP id e11so3275175pjt.4; Mon, 13 Jan 2020 13:07:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZCAEUSlUeHjJbOzhybZNdXvqq8RaBrp2R/gTbl2SsA4=; b=imf2N9GC3kHPqBbRGoBeoJtgVzok4YeYS3x1fRz8ck7RDWL0pktxyfg99w0VH067cP CuA2T30U80nscFo4jgx2jWiI/QlhO0N5HJT7ZMMQb0YlILKo6DefBL+DtkTB7cAybz5H scXKuPGm9p+ULT6R1oiWMTPz8YFxw531D4gNlI1L5MZpdlWBx6CweB+22+w5BEyO1YBs k6DN0vyNhFKzvzkEHcw+aXvF7FFB++6iDxB4GqfEOKNn8MxkQrsIEaEe/eKCw+lNDBmQ 3RNOhrmOVYsoAsuDwf4Hw2as4TLZaeKD3WSGcxtHsEFHaBFAQPgnm5A8NnzS66UeTjwn cU6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZCAEUSlUeHjJbOzhybZNdXvqq8RaBrp2R/gTbl2SsA4=; b=sNNK/WJPsZTPrgbxJ7I/YNrR/BFae+eQiNpfilcyXIjVrapq8OBRf2b4tALmKmY579 mZRKSEDP5/FVIKLJxlpSR9B2+hoXZf8ItRIC3c7yec6btmG+GXVjzQhH52/oRqXjBL98 Uev8tJgnza9q5oTh6BJe1C1C4CpFNM0KLrkZtZO9SpCg1hjRPt1D8Y/5bgx0MaSN1c0m V7DUEPZAwV1jBAFgJKFkqWSAeU1V3F7LqsJXfU0cZ3eCYMwoY8RFnfzS+7cjliWrMEub 92XCr86iAzpKIp9euJyT/U6rAMDfZCulYbw8xVtgvlbn7OylppsceCLq3eBqAb4U7HdR n/RQ== X-Gm-Message-State: APjAAAUv9XIcXDXwKkIUwt5JQyMVVjYx7pzW4qm4XsoZLpDzYrIpaNNi FceynvwIACcKNimjQxXCT+pcoppjXL/mpA== X-Google-Smtp-Source: APXvYqyErGp9uGm8FttvDm8IHO5klXLdH9nJDmcvZ44xGfQ3O2sLApMIAp/CiMUrsi0IV/v10P7o5g== X-Received: by 2002:a17:902:5ac9:: with SMTP id g9mr15616765plm.69.1578949672068; Mon, 13 Jan 2020 13:07:52 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id s1sm14195827pgv.87.2020.01.13.13.07.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2020 13:07:51 -0800 (PST) From: Al Cooper To: linux-kernel@vger.kernel.org Cc: Al Cooper , Adrian Hunter , Andrew Jeffery , bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, "Enrico Weigelt, metux IT consult" , Faiz Abbas , Florian Fainelli , linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, Manivannan Sadhasivam , Mark Rutland , Rob Herring , Sowjanya Komatineni , Takao Orito , Ulf Hansson , YueHaibing Subject: [PATCH 2/6] mmc: sdhci-brcmstb: Add ability to use HS400ES transfer mode Date: Mon, 13 Jan 2020 16:07:02 -0500 Message-Id: <20200113210706.11972-3-alcooperx@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200113210706.11972-1-alcooperx@gmail.com> References: <20200113210706.11972-1-alcooperx@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The latest eMMC JEDEC specification version 5.1 added a new transfer mode, HS400 with enhanced strobe (HS400ES). This mode will be selected if both the host controller and eMMC device support it. The latest Arasan 5.1 controller in the 7216a0 supports this mode. The "Host Controller Specification" has not been updated so the controller register bit used to enable this mode is not specified and varies the with controller vendor. The Linux SDHCI driver supplies a callback for enabling HS400ES mode and that callback will be used to supply a routine that will set the proper bit in the Arasan Vendor register. Signed-off-by: Al Cooper --- drivers/mmc/host/sdhci-brcmstb.c | 97 ++++++++++++++++++++++++++++---- 1 file changed, 86 insertions(+), 11 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 73bb440aaf93..daa89ca232a2 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -9,9 +9,41 @@ #include #include #include +#include #include "sdhci-pltfm.h" +#define SDHCI_VENDOR 0x78 +#define SDHCI_VENDOR_ENHANCED_STRB 0x1 + +#define BRCMSTB_PRIV_FLAGS_NO_64BIT BIT(0) +#define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT BIT(1) + +struct sdhci_brcmstb_priv { + void __iomem *cfg_regs; +}; + +struct brcmstb_match_priv { + void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); + unsigned int flags; +}; + +static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + + u32 reg; + + dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", + __func__); + reg = readl(host->ioaddr + SDHCI_VENDOR); + if (ios->enhanced_strobe) + reg |= SDHCI_VENDOR_ENHANCED_STRB; + else + reg &= ~SDHCI_VENDOR_ENHANCED_STRB; + writel(reg, host->ioaddr + SDHCI_VENDOR); +} + static const struct sdhci_ops sdhci_brcmstb_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -23,13 +55,40 @@ static const struct sdhci_pltfm_data sdhci_brcmstb_pdata = { .ops = &sdhci_brcmstb_ops, }; +static const struct brcmstb_match_priv match_priv_7425 = { + .flags = BRCMSTB_PRIV_FLAGS_NO_64BIT | + BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, +}; + +static const struct brcmstb_match_priv match_priv_7445 = { + .flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, +}; + +static const struct brcmstb_match_priv match_priv_7216 = { + .hs400es = sdhci_brcmstb_hs400es, +}; + +static const struct of_device_id sdhci_brcm_of_match[] = { + { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, + { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, + { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, + {}, +}; + static int sdhci_brcmstb_probe(struct platform_device *pdev) { - struct sdhci_host *host; + const struct brcmstb_match_priv *match_priv; struct sdhci_pltfm_host *pltfm_host; + const struct of_device_id *match; + struct sdhci_brcmstb_priv *priv; + struct sdhci_host *host; + struct resource *iomem; struct clk *clk; int res; + match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); + match_priv = match->data; + clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(clk)) { dev_err(&pdev->dev, "Clock not found in Device Tree\n"); @@ -39,36 +98,57 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) if (res) return res; - host = sdhci_pltfm_init(pdev, &sdhci_brcmstb_pdata, 0); + host = sdhci_pltfm_init(pdev, &sdhci_brcmstb_pdata, + sizeof(struct sdhci_brcmstb_priv)); if (IS_ERR(host)) { res = PTR_ERR(host); goto err_clk; } + pltfm_host = sdhci_priv(host); + priv = sdhci_pltfm_priv(pltfm_host); + + /* Map in the non-standard CFG registers */ + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem); + if (IS_ERR(priv->cfg_regs)) { + res = PTR_ERR(priv->cfg_regs); + goto err; + } + sdhci_get_of_property(pdev); res = mmc_of_parse(host->mmc); if (res) goto err; + /* + * If the chip has enhanced strobe and it's enabled, add + * callback + */ + if (match_priv->hs400es && + (host->mmc->caps2 & MMC_CAP2_HS400_ES)) + host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; + /* * Supply the existing CAPS, but clear the UHS modes. This * will allow these modes to be specified by device tree * properties through mmc_of_parse(). */ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); - if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm7425-sdhci")) + if (match_priv->flags & BRCMSTB_PRIV_FLAGS_NO_64BIT) host->caps &= ~SDHCI_CAN_64BIT; host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_DDR50); - host->quirks |= SDHCI_QUIRK_MISSING_CAPS | - SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; + host->quirks |= SDHCI_QUIRK_MISSING_CAPS; + + if (match_priv->flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT) + host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; res = sdhci_add_host(host); if (res) goto err; - pltfm_host = sdhci_priv(host); pltfm_host->clk = clk; return res; @@ -79,11 +159,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) return res; } -static const struct of_device_id sdhci_brcm_of_match[] = { - { .compatible = "brcm,bcm7425-sdhci" }, - { .compatible = "brcm,bcm7445-sdhci" }, - {}, -}; MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match); static struct platform_driver sdhci_brcmstb_driver = { From patchwork Mon Jan 13 21:07:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Cooper X-Patchwork-Id: 11330891 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 70F336C1 for ; Mon, 13 Jan 2020 21:08:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4F33224670 for ; Mon, 13 Jan 2020 21:08:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TvNq4fxI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728799AbgAMVH4 (ORCPT ); Mon, 13 Jan 2020 16:07:56 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:38033 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728792AbgAMVH4 (ORCPT ); Mon, 13 Jan 2020 16:07:56 -0500 Received: by mail-pg1-f193.google.com with SMTP id a33so5298817pgm.5; Mon, 13 Jan 2020 13:07:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c4EwOwGyRZn732m62F/bmkLNPBHupsvQnM8EZTJTEOU=; b=TvNq4fxIGcMuRSTocpaToEWweIJ2INFcSGkfkTb2PGFYP4PexLnpNWn0jgZYGYkBrv VcgNEUh9ux0x752QjnvpckLrBNTTBhvRbXKtk3vwZq8JrI/K3L+8JDPweSfGXHyj/NDp SvdW6n05jJp7R3pUNZSHm0PkJ2hw1hb2HhRkTO/XwdTOK6H3f1xhiznskz7KsLuroa/l 9xL/gQ8ciwMwcwuf7vlBvbai/qoolqJVhLzDwQXYFaAQUJloAe5eBq1QOfzWp/0ZmigB FnOcocIKY7rYAWBeSySjqqTjLIRtFhGBdyrIyskrV6zXFmRPVx0TZeQbIzuOaZttRLWi WKRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c4EwOwGyRZn732m62F/bmkLNPBHupsvQnM8EZTJTEOU=; b=pIjvVw/BQQtIPS+rCdIFUvnWsUwm8G+rYCX/FNSWxUBMEGpktTM1STI+CgfhLYBKmR 1mG2y3/jr6VDeOfuX8di0KjhnBeypO7iCvB/ypgOjIp7v1+yZ27p8Qw0nNP22y3a6s6x PYlpGA+wgq13qfEkzhllQBGymkI0C89pJwBigO4huK5Tl/Nt1C0vteX+JLSFg3HHP6wi XM6yoR05r6wuEcAYGSQ23VDlZhcV+0dr5h4CwCeKkks+qwvwNV3lv+1XC+u12DG6rZ2a /FnHIBkY0qzCQuQtrWjYb73kwTqor6/EwTztsNX+LlQCnfnduaObp3C8NB+QtvIsD8Uz 2FBQ== X-Gm-Message-State: APjAAAV7eTCKku5Z2arcRamOkL3L9C/hp0DAslj1hvecO5nDKQW8rSqR tHRWxIWDRtpN60sakRKcUEJo422yILBKiA== X-Google-Smtp-Source: APXvYqx1R7S8pIV0K8TV9qoZ4dBSE0XGBn6qp4kgOM11WVqKY4FU4nvS/xhY19oqkjyQfl1iY2QsUg== X-Received: by 2002:a63:a43:: with SMTP id z3mr22981828pgk.232.1578949674958; Mon, 13 Jan 2020 13:07:54 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id s1sm14195827pgv.87.2020.01.13.13.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2020 13:07:54 -0800 (PST) From: Al Cooper To: linux-kernel@vger.kernel.org Cc: Al Cooper , Adrian Hunter , Andrew Jeffery , bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, "Enrico Weigelt, metux IT consult" , Faiz Abbas , Florian Fainelli , linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, Manivannan Sadhasivam , Mark Rutland , Rob Herring , Sowjanya Komatineni , Takao Orito , Ulf Hansson , YueHaibing Subject: [PATCH 3/6] mmc: sdhci-brcmstb: Fix driver to defer on clk_get defer Date: Mon, 13 Jan 2020 16:07:03 -0500 Message-Id: <20200113210706.11972-4-alcooperx@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200113210706.11972-1-alcooperx@gmail.com> References: <20200113210706.11972-1-alcooperx@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The new SCMI clock protocol driver does not get probed that early in boot. Brcmstb drivers typically have the following code when getting a clock: priv->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, "Clock not found in Device Tree\n"); priv->clk = NULL; } This commit changes the driver to do what is below. priv->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(priv->clk)) { if (PTR_ERR(priv->clk) == -EPROBE_DEFER) return -EPROBE_DEFER; dev_err(&pdev->dev, "Clock not found in Device Tree\n"); priv->clk = NULL; } Signed-off-by: Al Cooper --- drivers/mmc/host/sdhci-brcmstb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index daa89ca232a2..218176b79b6a 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -91,6 +91,8 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(clk)) { + if (PTR_ERR(clk) == -EPROBE_DEFER) + return -EPROBE_DEFER; dev_err(&pdev->dev, "Clock not found in Device Tree\n"); clk = NULL; } From patchwork Mon Jan 13 21:07:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Cooper X-Patchwork-Id: 11330885 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B6B86C1 for ; Mon, 13 Jan 2020 21:08:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 597252465A for ; Mon, 13 Jan 2020 21:08:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JZ5FNozJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728831AbgAMVIA (ORCPT ); Mon, 13 Jan 2020 16:08:00 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:40747 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728820AbgAMVH7 (ORCPT ); Mon, 13 Jan 2020 16:07:59 -0500 Received: by mail-pg1-f194.google.com with SMTP id k25so5297266pgt.7; Mon, 13 Jan 2020 13:07:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5CAP7vT78sJ7ShUW4RVOxpE+JfJTOO+iEZfiA9Ic9Ok=; b=JZ5FNozJHtqB38WQ7SVPzNJy5Il5TQRFnfhZR7yzCDo5bdXPLtP0RUlP6yV7bIzd78 z1UXKwnP7GfNiP7jt5dAmvY0ZUFg9e4TqhPVx1hO0R2JZE6ZrMtveQCiFJ+7yI/M+gF2 AM7G9aWjAXLmZIsj4JAxN7LBdrqDyibZW1737i20WPIoQEIfkAUPTlvyMaj1iCkXzxeJ 8rysh4DomHv8VgdDBWiYQ0dIJhAY9NCwcnd5MxP0aeBeBrT2dHxjTN/n4DrquS/kkj7g BxGoxZHBf8JYSH7rAONXfPkZVSK3JebIL7GqtnAtND1EfunK8+4J/Sc5qku+PXA9SLRE QU0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5CAP7vT78sJ7ShUW4RVOxpE+JfJTOO+iEZfiA9Ic9Ok=; b=PceosCUJxPpo4uBW0bN32O2DKA8XvsKiuQIUpurljwX5a43eh/6adr78TdMfWkn7Mn RnFx3CpzEHIQjf6PKCA+xCuprqSSdg8Ll5H9ufxfmfDKJyesETX/isfAAFOtjvO1+/dQ 2UhUsC+Z8horrUNRuI8MFmg5+rkCzD0UF40rwW43mEWlXJwXqBV84SdPvoQuePCBupLy iCHS6XzP7lryqU9eDgF8WgCn2SuP6cfuGrFou4Vu0VgY8QKZ1TqMq73I3Km5srVZebEs j9xu/qMtuBIgajLfI3Dyxd1FunqmaIzZcPOzdO2pb8fCZ8GsTABVt+7c2IE70ZjntUDN sNhA== X-Gm-Message-State: APjAAAVGW7McbyjIEtGSdfk3UscuVZd0SP9HGZZl43N4/BOjrthpvZl3 xwzRczplj06LJDHEXHQbiqWW+JgvIMJaag== X-Google-Smtp-Source: APXvYqwk0d1fEyYVDxkLaN2UU1oTmel6YbkzKPFuVHpnNlXMqHO4ed/D6FyMrUyjKuAJus6QcKitpw== X-Received: by 2002:a63:6704:: with SMTP id b4mr23575633pgc.424.1578949677899; Mon, 13 Jan 2020 13:07:57 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id s1sm14195827pgv.87.2020.01.13.13.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2020 13:07:57 -0800 (PST) From: Al Cooper To: linux-kernel@vger.kernel.org Cc: Al Cooper , Adrian Hunter , Andrew Jeffery , bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, "Enrico Weigelt, metux IT consult" , Faiz Abbas , Florian Fainelli , linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, Manivannan Sadhasivam , Mark Rutland , Rob Herring , Sowjanya Komatineni , Takao Orito , Ulf Hansson , YueHaibing Subject: [PATCH 4/6] mmc: sdhci-brcmstb: Add shutdown callback Date: Mon, 13 Jan 2020 16:07:04 -0500 Message-Id: <20200113210706.11972-5-alcooperx@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200113210706.11972-1-alcooperx@gmail.com> References: <20200113210706.11972-1-alcooperx@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Shutdown controller and disable it's clocks to insure max power savings in S5 on systems that leave power on. Signed-off-by: Al Cooper --- drivers/mmc/host/sdhci-brcmstb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 218176b79b6a..7ea426ba5cbc 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -161,6 +161,15 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) return res; } +static void sdhci_brcmstb_shutdown(struct platform_device *pdev) +{ + int ret; + + ret = sdhci_pltfm_unregister(pdev); + if (ret) + dev_err(&pdev->dev, "failed to shutdown\n"); +} + MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match); static struct platform_driver sdhci_brcmstb_driver = { @@ -171,6 +180,7 @@ static struct platform_driver sdhci_brcmstb_driver = { }, .probe = sdhci_brcmstb_probe, .remove = sdhci_pltfm_unregister, + .shutdown = sdhci_brcmstb_shutdown, }; module_platform_driver(sdhci_brcmstb_driver); From patchwork Mon Jan 13 21:07:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Cooper X-Patchwork-Id: 11330889 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B454A1398 for ; Mon, 13 Jan 2020 21:08:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 884A124670 for ; Mon, 13 Jan 2020 21:08:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sdN9eNr0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728855AbgAMVID (ORCPT ); Mon, 13 Jan 2020 16:08:03 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:46229 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728842AbgAMVIC (ORCPT ); Mon, 13 Jan 2020 16:08:02 -0500 Received: by mail-pg1-f196.google.com with SMTP id z124so5280014pgb.13; Mon, 13 Jan 2020 13:08:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bZHyA1pnyUOSaH6sIl5fA7IIKshVElY/2p2ut+5kOaQ=; b=sdN9eNr07g2kJ1ITVDp0TNjWSLys9RQy1ZdVzcG/3SfKuPwDWgV8Nur8qCGDAVRfE/ fcTpnrOMRkqfkPmRR8DD4YNCnM+XwpMwvTMp+dUYrAxINFzxj2Xo7cut3iU70gTLRGFa ByKJ1sLpMjcsk2JKEPNb28ScvP6tl6urgMRaKncQe0HITx/XtuUM+UKzMj8o6LG5jZ5g N8/M4RfvhEWGaLspv4geZbVCycj+Z+m674voNokRIunu6DVzliC0+KdCqTs1ReOBxAnx inOoPL0OHVO/slPdMquWDYoLDqzcZ/oDt5kwrAok2LtBhOr+t19+5MZJ/v5cQ36PxREk wQQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bZHyA1pnyUOSaH6sIl5fA7IIKshVElY/2p2ut+5kOaQ=; b=Kq2/Vw1m9SenYDe5KNGVTG54K+mu1DuChjIcuwpTeef2YYmppOaZ0I7JG3NKWUvpEa EYvRv1eIWj1lAcaGrQ6fckyIol6U6mlC3kdSngQybI63r2LoNm0Bc0zsErDpfy2OqHKo vCiXf6xRGU66Qc6L0kSt352GHVTM5Uk3337Mia+WJvdX/27sYmxVhi7JMpEMA2PMHaPU QLIlvjzNQ24dXkwy55R0x4v9I5ZOqoogCpByk4K5c+ifC8nfPoa8cqXkxYGMwmRpuhcW IR4hYeklgsXPTVkcw4QfV1DJ7hMJoW/MjjEjpgrsUc+b+/y/HHFwMqxR6dSDm1qlT9hJ 8Mqw== X-Gm-Message-State: APjAAAUHP8gBaMTX074mDpAuWO6DwbgFWBy0Xgt0X/fQ8WwIYod2O8Yp rMCLu9Wx2Hh2lziOwlsY7Y5RyrY1hRMjeQ== X-Google-Smtp-Source: APXvYqxU8UBmtvYuVuX3/nVbKboe1z24KIGFrgYkD4UDVAQnisLGoaslVQUYy2VnpHAYyKYJyMAhjQ== X-Received: by 2002:a63:6507:: with SMTP id z7mr23578729pgb.322.1578949680591; Mon, 13 Jan 2020 13:08:00 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id s1sm14195827pgv.87.2020.01.13.13.07.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2020 13:08:00 -0800 (PST) From: Al Cooper To: linux-kernel@vger.kernel.org Cc: Al Cooper , Adrian Hunter , Andrew Jeffery , bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, "Enrico Weigelt, metux IT consult" , Faiz Abbas , Florian Fainelli , linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, Manivannan Sadhasivam , Mark Rutland , Rob Herring , Sowjanya Komatineni , Takao Orito , Ulf Hansson , YueHaibing Subject: [PATCH 5/6] mmc: sdhci-brcmstb: Add support for Command Queuing (CQE) Date: Mon, 13 Jan 2020 16:07:05 -0500 Message-Id: <20200113210706.11972-6-alcooperx@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200113210706.11972-1-alcooperx@gmail.com> References: <20200113210706.11972-1-alcooperx@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The latest Arasan controller first used in the 7216 now supports CQE so enable this feature. Signed-off-by: Al Cooper --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-brcmstb.c | 140 +++++++++++++++++++++++++++++-- 2 files changed, 133 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index d06b2dfe3c95..8897de30959a 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -990,6 +990,7 @@ config MMC_SDHCI_BRCMSTB tristate "Broadcom SDIO/SD/MMC support" depends on ARCH_BRCMSTB || BMIPS_GENERIC depends on MMC_SDHCI_PLTFM + select MMC_CQHCI default y help This selects support for the SDIO/SD/MMC Host Controller on diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 7ea426ba5cbc..2c4b6e7e3d9a 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -10,8 +10,10 @@ #include #include #include +#include #include "sdhci-pltfm.h" +#include "cqhci.h" #define SDHCI_VENDOR 0x78 #define SDHCI_VENDOR_ENHANCED_STRB 0x1 @@ -19,12 +21,16 @@ #define BRCMSTB_PRIV_FLAGS_NO_64BIT BIT(0) #define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT BIT(1) +#define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; + bool has_cqe; }; struct brcmstb_match_priv { void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); + struct sdhci_ops *ops; unsigned int flags; }; @@ -44,28 +50,74 @@ static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) writel(reg, host->ioaddr + SDHCI_VENDOR); } -static const struct sdhci_ops sdhci_brcmstb_ops = { +static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) +{ + u16 clk; + + host->mmc->actual_clock = 0; + + clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + return; + + sdhci_enable_clk(host, clk); +} + +static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) +{ + sdhci_dumpregs(mmc_priv(mmc)); +} + +static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u32 reg; + + reg = sdhci_readl(host, SDHCI_PRESENT_STATE); + while (reg & SDHCI_DATA_AVAILABLE) { + sdhci_readl(host, SDHCI_BUFFER); + reg = sdhci_readl(host, SDHCI_PRESENT_STATE); + } + + sdhci_cqe_enable(mmc); +} + +static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = { + .enable = sdhci_brcmstb_cqe_enable, + .disable = sdhci_cqe_disable, + .dumpregs = sdhci_brcmstb_dumpregs, +}; + +static struct sdhci_ops sdhci_brcmstb_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, }; -static const struct sdhci_pltfm_data sdhci_brcmstb_pdata = { - .ops = &sdhci_brcmstb_ops, +static struct sdhci_ops sdhci_brcmstb_ops_7216 = { + .set_clock = sdhci_brcmstb_set_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, }; -static const struct brcmstb_match_priv match_priv_7425 = { +static struct brcmstb_match_priv match_priv_7425 = { .flags = BRCMSTB_PRIV_FLAGS_NO_64BIT | BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, + .ops = &sdhci_brcmstb_ops, }; -static const struct brcmstb_match_priv match_priv_7445 = { +static struct brcmstb_match_priv match_priv_7445 = { .flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT, + .ops = &sdhci_brcmstb_ops, }; static const struct brcmstb_match_priv match_priv_7216 = { .hs400es = sdhci_brcmstb_hs400es, + .ops = &sdhci_brcmstb_ops_7216, }; static const struct of_device_id sdhci_brcm_of_match[] = { @@ -75,20 +127,85 @@ static const struct of_device_id sdhci_brcm_of_match[] = { {}, }; +static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask) +{ + int cmd_error = 0; + int data_error = 0; + + if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) + return intmask; + + cqhci_irq(host->mmc, intmask, cmd_error, data_error); + + return 0; +} + +static int sdhci_brcmstb_add_host(struct sdhci_host *host, + struct sdhci_brcmstb_priv *priv) +{ + struct cqhci_host *cq_host; + bool dma64; + int ret; + + if (!priv->has_cqe) + return sdhci_add_host(host); + + dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); + host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; + ret = sdhci_setup_host(host); + if (ret) + return ret; + + cq_host = devm_kzalloc(mmc_dev(host->mmc), + sizeof(*cq_host), GFP_KERNEL); + if (!cq_host) { + ret = -ENOMEM; + goto cleanup; + } + + cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; + cq_host->ops = &sdhci_brcmstb_cqhci_ops; + + dma64 = host->flags & SDHCI_USE_64_BIT_DMA; + if (dma64) { + dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n"); + cq_host->caps |= CQHCI_TASK_DESC_SZ_128; + cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; + } + + ret = cqhci_init(cq_host, host->mmc, dma64); + if (ret) + goto cleanup; + + ret = __sdhci_add_host(host); + if (ret) + goto cleanup; + + return 0; + +cleanup: + sdhci_cleanup_host(host); + return ret; +} + static int sdhci_brcmstb_probe(struct platform_device *pdev) { const struct brcmstb_match_priv *match_priv; + struct sdhci_pltfm_data brcmstb_pdata; struct sdhci_pltfm_host *pltfm_host; const struct of_device_id *match; struct sdhci_brcmstb_priv *priv; struct sdhci_host *host; struct resource *iomem; + bool has_cqe = false; struct clk *clk; int res; match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); match_priv = match->data; + dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); + clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(clk)) { if (PTR_ERR(clk) == -EPROBE_DEFER) @@ -100,7 +217,13 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) if (res) return res; - host = sdhci_pltfm_init(pdev, &sdhci_brcmstb_pdata, + memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); + if (device_property_read_bool(&pdev->dev, "supports-cqe")) { + has_cqe = true; + match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; + } + brcmstb_pdata.ops = match_priv->ops; + host = sdhci_pltfm_init(pdev, &brcmstb_pdata, sizeof(struct sdhci_brcmstb_priv)); if (IS_ERR(host)) { res = PTR_ERR(host); @@ -109,6 +232,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); priv = sdhci_pltfm_priv(pltfm_host); + priv->has_cqe = has_cqe; /* Map in the non-standard CFG registers */ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); @@ -141,13 +265,13 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) host->caps &= ~SDHCI_CAN_64BIT; host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | - SDHCI_SUPPORT_DDR50); + SDHCI_SUPPORT_DDR50); host->quirks |= SDHCI_QUIRK_MISSING_CAPS; if (match_priv->flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT) host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; - res = sdhci_add_host(host); + res = sdhci_brcmstb_add_host(host, priv); if (res) goto err; From patchwork Mon Jan 13 21:07:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Cooper X-Patchwork-Id: 11330887 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F2A71398 for ; Mon, 13 Jan 2020 21:08:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 63AFE24658 for ; Mon, 13 Jan 2020 21:08:10 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 13 Jan 2020 13:08:02 -0800 (PST) From: Al Cooper To: linux-kernel@vger.kernel.org Cc: Al Cooper , Adrian Hunter , Andrew Jeffery , bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, "Enrico Weigelt, metux IT consult" , Faiz Abbas , Florian Fainelli , linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, Manivannan Sadhasivam , Mark Rutland , Rob Herring , Sowjanya Komatineni , Takao Orito , Ulf Hansson , YueHaibing Subject: [PATCH 6/6] mmc: sdhci-brcmstb: Fix incorrect switch to HS mode Date: Mon, 13 Jan 2020 16:07:06 -0500 Message-Id: <20200113210706.11972-7-alcooperx@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200113210706.11972-1-alcooperx@gmail.com> References: <20200113210706.11972-1-alcooperx@gmail.com> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org When switching from any MMC speed mode that requires 1.8v (HS200, HS400 and HS400ES) to High Speed (HS) mode, the system ends up configured for SDR12 with a 50MHz clock which is an illegal mode. This happens because the SDHCI_CTRL_VDD_180 bit in the SDHCI_HOST_CONTROL2 register is left set and when this bit is set, the speed mode is controlled by the SDHCI_CTRL_UHS field in the SDHCI_HOST_CONTROL2 register. The SDHCI_CTRL_UHS field will end up being set to 0 (SDR12) by sdhci_set_uhs_signaling() because there is no UHS mode being set. The fix is to change sdhci_set_uhs_signaling() to set the SDHCI_CTRL_UHS field to SDR25 (which is the same as HS) for any switch to HS mode. This was found on a new eMMC controller that does strict checking of the speed mode and the corresponding clock rate. It caused the switch to HS400 mode to fail because part of the sequence to switch to HS400 requires a switch from HS200 to HS before going to HS400. This issue was previously fixed by commit c894e33ddc191 ("mmc: sdhci: Fix incorrect switch to HS mode") and later removed by commit 07bcc411567c ("Revert \"mmc: sdhci: Fix incorrect switch to HS mode\"") because it caused failures with some SD cards on AM65X systems. The fix will now be done in a platform specific callback instead of common sdhci code. Signed-off-by: Al Cooper Suggested-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 2c4b6e7e3d9a..ad01f6451a95 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -65,6 +65,35 @@ static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_enable_clk(host, clk); } +static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n", + __func__, timing); + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + if ((timing == MMC_TIMING_MMC_HS200) || + (timing == MMC_TIMING_UHS_SDR104)) + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + else if (timing == MMC_TIMING_UHS_SDR12) + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + else if (timing == MMC_TIMING_SD_HS || + timing == MMC_TIMING_MMC_HS || + timing == MMC_TIMING_UHS_SDR25) + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + else if (timing == MMC_TIMING_UHS_SDR50) + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + else if ((timing == MMC_TIMING_UHS_DDR50) || + (timing == MMC_TIMING_MMC_DDR52)) + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + else if (timing == MMC_TIMING_MMC_HS400) + ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -101,7 +130,7 @@ static struct sdhci_ops sdhci_brcmstb_ops_7216 = { .set_clock = sdhci_brcmstb_set_clock, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_reset, - .set_uhs_signaling = sdhci_set_uhs_signaling, + .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, }; static struct brcmstb_match_priv match_priv_7425 = {