From patchwork Wed Jan 15 14:13:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334925 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9440E1398 for ; Wed, 15 Jan 2020 14:15:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 72CDB2467E for ; Wed, 15 Jan 2020 14:15:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="b6Xz4MLj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729099AbgAOOPF (ORCPT ); Wed, 15 Jan 2020 09:15:05 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:44429 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729631AbgAOONJ (ORCPT ); Wed, 15 Jan 2020 09:13:09 -0500 Received: by mail-wr1-f67.google.com with SMTP id q10so15889028wrm.11 for ; Wed, 15 Jan 2020 06:13:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f2EHRYMI/TrUMZiwdhRPG+CtjBM6dg1rcU2ZvEhaaRU=; b=b6Xz4MLjpNeovyf0j/n3jNiTMyMKIbYXWa+8HcRWYqQOMTWOyIEWH4h1uo0njlqPOm 4GEheSsQF2cON7MQC3DutbDhgEX9EOFRtRTrM/j8VnF55rISfOZMvh6MwgvBeMGCrt0x 8hlc832sNeke+deccGiXMylyEhm17cBLEdfzMt0A8ToezBTwKrgBBzyJxhUAapOEZBmr 6AOoYVgngMt2QH+n1pbWzTNNuweb0ZfZp0Y9uAUFzxrnhPJqURjzdR4K/LEzi3TY7hGF THU9dLU8hseyu97IlLTjmmpKxL3YsrTghAqgJqy0GXY6MYFV8TyyrefNFE7ph/oF877v JYYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f2EHRYMI/TrUMZiwdhRPG+CtjBM6dg1rcU2ZvEhaaRU=; b=N0cElcYn3YBJD2sDa+hFMRYmZe+xKK2MzD4taIJ+8vIAMhDauEIlG9YGEBf7W6J1qu q1RYOhaEWNSrc2jB2xKmrlvMO/DjvQ2ppR/klLkj/uVzpGWoFLxja5gTjxkXRtnkbdhW NVq/u2uYeBbFRA1ziABAO/vvNVFNTqrrjbyK7Gtr+C5FAVyr/Tc6eMzwYxkIZTP0XGgo YqQRll4T+I0wlqp1UyLUNTy9i8OJdVD157Q3oDNAilzlYnKOdFbiN59tXfwF5DT8gIVa ge0LaUPt1uO1YkXuXJ/7yGBgS2JICClnJ4s/0Jwtv1I9hSjXfCCjvOEQr4qQV2Irlb31 /urg== X-Gm-Message-State: APjAAAWwJD5x38BxrtEZG31prZu+sDkDsnAHu0lfa8lMhtRvECBnidFH x0Mw7yhwNwnWpsmqNoAqEdfnhsCj/9k= X-Google-Smtp-Source: APXvYqzxzRlw2U5aBlUnoLp9Qf+6/vSSV796tAM/I8yuqlr7588woX0Svjra55WW5pbW9B+PNOsMRw== X-Received: by 2002:adf:d4ca:: with SMTP id w10mr29951658wrk.53.1579097586435; Wed, 15 Jan 2020 06:13:06 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:05 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Jorge Ramirez-Ortiz , Jorge Ramirez-Ortiz , Bryan O'Donoghue Subject: [PATCH 01/19] dt-bindings: phy: remove qcom-dwc3-usb-phy Date: Wed, 15 Jan 2020 14:13:15 +0000 Message-Id: <20200115141333.1222676-2-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz This binding is not used by any driver. Signed-off-by: Jorge Ramirez-Ortiz Cc: Jorge Ramirez-Ortiz Signed-off-by: Bryan O'Donoghue --- .../bindings/phy/qcom-dwc3-usb-phy.txt | 37 ------------------- 1 file changed, 37 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt deleted file mode 100644 index a1697c27aecd..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt +++ /dev/null @@ -1,37 +0,0 @@ -Qualcomm DWC3 HS AND SS PHY CONTROLLER --------------------------------------- - -DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer -controllers. Each DWC3 PHY controller should have its own node. - -Required properties: -- compatible: should contain one of the following: - - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller - - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller -- reg: offset and length of the DWC3 PHY controller register set -- #phy-cells: must be zero -- clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. -- clock-names: Should contain "ref" for the PHY reference clock - -Optional clocks: - "xo" External reference clock - -Example: - phy@100f8800 { - compatible = "qcom,dwc3-hs-usb-phy"; - reg = <0x100f8800 0x30>; - clocks = <&gcc USB30_0_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - }; - - phy@100f8830 { - compatible = "qcom,dwc3-ss-usb-phy"; - reg = <0x100f8830 0x30>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - }; From patchwork Wed Jan 15 14:13:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334927 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B5EC92A for ; Wed, 15 Jan 2020 14:15:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E450924656 for ; Wed, 15 Jan 2020 14:15:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nEY82/y0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729631AbgAOOPG (ORCPT ); Wed, 15 Jan 2020 09:15:06 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:41483 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729657AbgAOONJ (ORCPT ); Wed, 15 Jan 2020 09:13:09 -0500 Received: by mail-wr1-f68.google.com with SMTP id c9so15892849wrw.8 for ; Wed, 15 Jan 2020 06:13:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PCdwe+dsjnxv3bml7N0qDZxbZ4I8SN1UrysTU8U3ets=; b=nEY82/y0BNZg4ZPeORMiuXFe/3DgtX+U5lo1ZtJ3hn5e08nKkdJbBqUlLNvOYjrZc+ 7ioEe0dTNAVDXPeWAR5n4202QgN6RV3Hct0i0HfCu1UGMI7f3VPvXyUbD2s6Z9E6L1U3 kAcoO6GbwWhQ+KhRrBmMiBtX03QSLSiigmXMOEBTfDuGovHeOB0z9sFdkzftXdN7S2k3 o/ESFR8PgVT5RBaDIVu8nFRcP9QafJAO6PUSV3ioLDTBqBX/Tc5qlhYxVXzpxtPTnV4M 8RMZyG7IKrBNEnPJC5vt4TOX7Eq4cNHgfCVbRqJNiLR8ZtV2KSqXAiIkAt+f/VV8kqs7 9oJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PCdwe+dsjnxv3bml7N0qDZxbZ4I8SN1UrysTU8U3ets=; b=hhE69rnwPhzBkUdtKnb2KlDfHY1uJLsTbUt6K7QEWitDlLQav3fRcoRQz7chVc9RX2 lmAno9hFuGVofh6jTXiTLdchqRpQqUgWPQttIUES6lBHbBeI4B6C1zgCPZ5TCKIs3VGi 7bFhTkAEK5E8zYSxNjMENkyTbOwV5dImlZ+8qsC4n1frv/PKxnC+xpQy9UGaBm4ymOK6 8ZQejurDLCRCZKIx/WCADU4ZOwo0VHywrq4aJeSiKjylZDAqeVOl+ixZ8ZDdmn+DRaTn M4Ubybu3qkkPzkbMbPMUGf6kXb5+hR0PYSKvNm5cOVtjdvhF+d7REqWIZhpngxer7GIo WMjQ== X-Gm-Message-State: APjAAAV1UoYdIVWJEOIXh0nyxAGa2Bk7XCI0MVaXfns+FjjOpRzuffvK mt3J8ig8cSN34SOMKC08fufjSjKZBUA= X-Google-Smtp-Source: APXvYqyFCs8W824zav4mO7iW6IJZ2oMXu8EgcO0ACxcSO5xMO78O+j9I88X7j/y/aOwE8yO8BrTnKw== X-Received: by 2002:adf:f484:: with SMTP id l4mr31381219wro.207.1579097587939; Wed, 15 Jan 2020 06:13:07 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:07 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Sriharsha Allenki , Anu Ramanathan , Shawn Guo , Andy Gross , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Jorge Ramirez-Ortiz , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH 02/19] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Date: Wed, 15 Jan 2020 14:13:16 +0000 Message-Id: <20200115141333.1222676-3-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sriharsha Allenki Adds bindings for QCS404 USB PHY supporting Low-Speed, Full-Speed and Hi-Speed USB connectivity on Qualcomm chipsets. [bod: Converted to YAML. Changed name dropping snps component] Signed-off-by: Sriharsha Allenki Signed-off-by: Anu Ramanathan Signed-off-by: Bjorn Andersson Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Rob Herring Cc: Mark Rutland Cc: Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- .../bindings/phy/qcom,qcs404-usb-hs.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml new file mode 100644 index 000000000000..4bc7a3334b54 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qcs404-usb-hs.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys QCS-404 High-Speed PHY + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm QCS-404 Low-Speed, Full-Speed, Hi-Speed USB PHY + +properties: + compatible: + enum: + - qcom,qcs404-usb-hsphy + + reg: + maxItems: 1 + description: USB PHY base address and length of the register map. + + "#phy-cells": + const: 0 + description: Should be 0. See phy/phy-bindings.txt for details. + + clocks: + items: + - description: Rescource Power Management clock + - descirption: PHY AHB clock + - description: Retention clock + + clock-names: + items: + - const: ref + - const: phy + - const: sleep + + resets: + items: + - description: PHY core reset + - description: POR reset + + reset-names: + items: + - description: phy + - description: por + + vdd-supply: + maxItems: 1 + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + maxItems: 1 + description: phandle to the regulator 1.8V supply node. + + vdda3p3-supply: + maxItems: 1 + description: phandle to the regulator 3.3V supply node. + +Example: + + phy@7a000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x7a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + }; From patchwork Wed Jan 15 14:13:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334915 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C8461398 for ; Wed, 15 Jan 2020 14:15:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 10BAB24681 for ; Wed, 15 Jan 2020 14:15:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oW8pvvdH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729747AbgAOONM (ORCPT ); Wed, 15 Jan 2020 09:13:12 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:35357 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729701AbgAOONM (ORCPT ); Wed, 15 Jan 2020 09:13:12 -0500 Received: by mail-wr1-f68.google.com with SMTP id g17so15884642wro.2 for ; Wed, 15 Jan 2020 06:13:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YOaDQqLtOTp7XppyzLnPT/PUdBtVKIt3+gEHpuiyQDM=; b=oW8pvvdHPMVsv5IykdLPiloRJ5enVINiTYMOm56STr1kvqGofzf+4+y/n/43KfbbrK zAY3yDVPl1m36sWafnW5nQSTkrFEHkXsezS8aOsObBhRXWMBgIiTkwQSc0JKf3uxHsDM CXKPe/MSC98aAFMERSkHDsea534GMiTy2nShhn8capNhoL3fXi4Pgru0/MFWLQoJO7wY Enbh9JcOzyqPB8+mm+lLjlhK/ah1VsMLdSEihxmUmsYoJocf4XLgqdpKvWKpQJ6I0obC P82/ItxQXIkys9WME1Xx1gpNZndIoiBwSafNNlabK+OWQNZrTfxLuVj83sLOV1vKZNoX sq9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YOaDQqLtOTp7XppyzLnPT/PUdBtVKIt3+gEHpuiyQDM=; b=P1UtOmOxkoDQ58STItNxglmwt82AaMiZpjtBT6gIYLC+eHAMmKe/U985sgy2qNdHji k3pSQyWBWmuxuIYCYBZX3Vygr17sKS0niLKufEkdCvKQhxMdX5XmGsjQ5RkNainuS+0I qMv2StPK1UzKV3y6od9Nqo+MNm5/52fUfxN7NwIkue0JUS2/fS/cakRC04ca4i2Pgdz4 pLgCZi0Mq6omeGr2eoSECqne/cB4OYz0Jap45WKqWt5dAEJ7UyY6WKrqr8MIMQb9ijmH 8CIxOpmTWTiFxv5zIM3NmzaDj37wIZ4Bk602t/TclXY9njq6818J3g8X9pdfpvnKpQpt 8QJw== X-Gm-Message-State: APjAAAXw2NgrNEsgOz+nYzs3fbqg8/JFZQ5QgxLDVjPrFike83sNsHJG gggv5U0pYxwREJK7DIbtMMxLW5+3BGY= X-Google-Smtp-Source: APXvYqzRjtH6yroOtixYub0jXwr5qSgs/qlqDz8JWVv8GAIfx6i1oA8DozEFHYLGAUhiWBKyxhJ9HA== X-Received: by 2002:adf:ea88:: with SMTP id s8mr31607751wrm.293.1579097589275; Wed, 15 Jan 2020 06:13:09 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:08 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Shawn Guo , Andy Gross , Kishon Vijay Abraham I , Philipp Zabel , Jorge Ramirez-Ortiz , Bryan O'Donoghue Subject: [PATCH 03/19] phy: qualcomm: Add Synopsys Hi-Speed USB PHY driver Date: Wed, 15 Jan 2020 14:13:17 +0000 Message-Id: <20200115141333.1222676-4-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Shawn Guo Adds Qualcomm QCS404 Hi-Speed USB PHY driver support. This PHY is usually is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. [bod: Updated qcom_snps_hsphy_set_mode to match new method signature Added disjunct on mode > 0 Removed regulator_set_voltage() in favour of setting floor in dts Removed 'snps' and '28nm' from driver name] Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Philipp Zabel Cc: Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- drivers/phy/qualcomm/Kconfig | 10 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c | 415 ++++++++++++++++++ 3 files changed, 426 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index e46824da29f6..cc3f2bb01ad1 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -91,3 +91,13 @@ config PHY_QCOM_USB_HSIC select GENERIC_PHY help Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. + +config PHY_QCOM_QCS404_USB_HS + tristate "Qualcomm QCS404 Hi-Speed USB PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Qualcomm QCS404 USB Hi-Speed PHY driver. + This driver supports the Hi-Speed PHY which is usually paired with + either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 283251d6a5d9..a4a3b21240fa 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o +obj-$(CONFIG_PHY_QCOM_QCS404_USB_HS) += phy-qcom-qcs404-usb-hs.o diff --git a/drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c b/drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c new file mode 100644 index 000000000000..c09b786592b1 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qcs404-usb-hs.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2009-2018, Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PHY register and bit definitions */ +#define PHY_CTRL_COMMON0 0x078 +#define SIDDQ BIT(2) +#define PHY_IRQ_CMD 0x0d0 +#define PHY_INTR_MASK0 0x0d4 +#define PHY_INTR_CLEAR0 0x0dc +#define DPDM_MASK 0x1e +#define DP_1_0 BIT(4) +#define DP_0_1 BIT(3) +#define DM_1_0 BIT(2) +#define DM_0_1 BIT(1) + +enum hsphy_voltage { + VOL_NONE, + VOL_MIN, + VOL_MAX, + VOL_NUM, +}; + +enum hsphy_vreg { + VDD, + VDDA_1P8, + VDDA_3P3, + VREG_NUM, +}; + +struct hsphy_init_seq { + int offset; + int val; + int delay; +}; + +struct hsphy_data { + const struct hsphy_init_seq *init_seq; + unsigned int init_seq_num; +}; + +struct hsphy_priv { + void __iomem *base; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *phy_reset; + struct reset_control *por_reset; + struct regulator_bulk_data vregs[VREG_NUM]; + const struct hsphy_data *data; + enum phy_mode mode; +}; + +static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + priv->mode = PHY_MODE_INVALID; + + if (mode > 0) + priv->mode = mode; + + return 0; +} + +static void qcom_snps_hsphy_enable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + /* Clear any existing interrupts before enabling the interrupts */ + val = readb(priv->base + PHY_INTR_CLEAR0); + val |= DPDM_MASK; + writeb(val, priv->base + PHY_INTR_CLEAR0); + + writeb(0x0, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); + writeb(0x1, priv->base + PHY_IRQ_CMD); + + /* Make sure the interrupts are cleared */ + usleep_range(200, 220); + + val = readb(priv->base + PHY_INTR_MASK0); + switch (priv->mode) { + case PHY_MODE_USB_HOST_HS: + case PHY_MODE_USB_HOST_FS: + case PHY_MODE_USB_DEVICE_HS: + case PHY_MODE_USB_DEVICE_FS: + val |= DP_1_0 | DM_0_1; + break; + case PHY_MODE_USB_HOST_LS: + case PHY_MODE_USB_DEVICE_LS: + val |= DP_0_1 | DM_1_0; + break; + default: + /* No device connected */ + val |= DP_0_1 | DM_0_1; + break; + } + writeb(val, priv->base + PHY_INTR_MASK0); +} + +static void qcom_snps_hsphy_disable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_INTR_MASK0); + val &= ~DPDM_MASK; + writeb(val, priv->base + PHY_INTR_MASK0); + + /* Clear any pending interrupts */ + val = readb(priv->base + PHY_INTR_CLEAR0); + val |= DPDM_MASK; + writeb(val, priv->base + PHY_INTR_CLEAR0); + + writeb(0x0, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); + + writeb(0x1, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); +} + +static void qcom_snps_hsphy_enter_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val |= SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); +} + +static void qcom_snps_hsphy_exit_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val &= ~SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); +} + +static int qcom_snps_hsphy_power_on(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = regulator_bulk_enable(VREG_NUM, priv->vregs); + if (ret) + return ret; + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + goto err_disable_regulator; + qcom_snps_hsphy_disable_hv_interrupts(priv); + qcom_snps_hsphy_exit_retention(priv); + + return 0; + +err_disable_regulator: + regulator_bulk_disable(VREG_NUM, priv->vregs); + + return ret; +} + +static int qcom_snps_hsphy_power_off(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + qcom_snps_hsphy_enter_retention(priv); + qcom_snps_hsphy_enable_hv_interrupts(priv); + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + regulator_bulk_disable(VREG_NUM, priv->vregs); + + return 0; +} + +static int qcom_snps_hsphy_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(10, 15); + + ret = reset_control_deassert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(80, 100); + + return 0; +} + +static void qcom_snps_hsphy_init_sequence(struct hsphy_priv *priv) +{ + const struct hsphy_data *data = priv->data; + const struct hsphy_init_seq *seq; + int i; + + /* Device match data is optional. */ + if (!data) + return; + + seq = data->init_seq; + + for (i = 0; i < data->init_seq_num; i++, seq++) { + writeb(seq->val, priv->base + seq->offset); + if (seq->delay) + usleep_range(seq->delay, seq->delay + 10); + } +} + +static int qcom_snps_hsphy_por_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->por_reset); + if (ret) + return ret; + + /* + * The Femto PHY is POR reset in the following scenarios. + * + * 1. After overriding the parameter registers. + * 2. Low power mode exit from PHY retention. + * + * Ensure that SIDDQ is cleared before bringing the PHY + * out of reset. + */ + qcom_snps_hsphy_exit_retention(priv); + + /* + * As per databook, 10 usec delay is required between + * PHY POR assert and de-assert. + */ + usleep_range(10, 20); + ret = reset_control_deassert(priv->por_reset); + if (ret) + return ret; + + /* + * As per databook, it takes 75 usec for PHY to stabilize + * after the reset. + */ + usleep_range(80, 100); + + return 0; +} + +static int qcom_snps_hsphy_init(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = qcom_snps_hsphy_reset(priv); + if (ret) + return ret; + + qcom_snps_hsphy_init_sequence(priv); + + ret = qcom_snps_hsphy_por_reset(priv); + if (ret) + return ret; + + return 0; +} + +static const struct phy_ops qcom_snps_hsphy_ops = { + .init = qcom_snps_hsphy_init, + .power_on = qcom_snps_hsphy_power_on, + .power_off = qcom_snps_hsphy_power_off, + .set_mode = qcom_snps_hsphy_set_mode, + .owner = THIS_MODULE, +}; + +static const char * const qcom_snps_hsphy_clks[] = { + "ref", + "phy", + "sleep", +}; + +static int qcom_snps_hsphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct hsphy_priv *priv; + struct phy *phy; + int ret; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->num_clks = ARRAY_SIZE(qcom_snps_hsphy_clks); + priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks), + GFP_KERNEL); + if (!priv->clks) + return -ENOMEM; + + for (i = 0; i < priv->num_clks; i++) + priv->clks[i].id = qcom_snps_hsphy_clks[i]; + + ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks); + if (ret) + return ret; + + priv->phy_reset = devm_reset_control_get(dev, "phy"); + if (IS_ERR(priv->phy_reset)) + return PTR_ERR(priv->phy_reset); + + priv->por_reset = devm_reset_control_get(dev, "por"); + if (IS_ERR(priv->por_reset)) + return PTR_ERR(priv->por_reset); + + priv->vregs[VDD].supply = "vdd"; + priv->vregs[VDDA_1P8].supply = "vdda1p8"; + priv->vregs[VDDA_3P3].supply = "vdda3p3"; + + ret = devm_regulator_bulk_get(dev, VREG_NUM, priv->vregs); + if (ret) + return ret; + + /* Get device match data */ + priv->data = device_get_match_data(dev); + + phy = devm_phy_create(dev, dev->of_node, &qcom_snps_hsphy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(provider)) + return PTR_ERR(provider); + + ret = regulator_set_load(priv->vregs[VDDA_1P8].consumer, 19000); + if (ret < 0) + return ret; + + ret = regulator_set_load(priv->vregs[VDDA_3P3].consumer, 16000); + if (ret < 0) + goto unset_1p8_load; + + return 0; + +unset_1p8_load: + regulator_set_load(priv->vregs[VDDA_1P8].consumer, 0); + + return ret; +} + +/* + * The macro is used to define an initialization sequence. Each tuple + * is meant to program 'value' into phy register at 'offset' with 'delay' + * in us followed. + */ +#define HSPHY_INIT_CFG(o, v, d) { .offset = o, .val = v, .delay = d, } + +static const struct hsphy_init_seq init_seq_qcs404[] = { + HSPHY_INIT_CFG(0xc0, 0x01, 0), + HSPHY_INIT_CFG(0xe8, 0x0d, 0), + HSPHY_INIT_CFG(0x74, 0x12, 0), + HSPHY_INIT_CFG(0x98, 0x63, 0), + HSPHY_INIT_CFG(0x9c, 0x03, 0), + HSPHY_INIT_CFG(0xa0, 0x1d, 0), + HSPHY_INIT_CFG(0xa4, 0x03, 0), + HSPHY_INIT_CFG(0x8c, 0x23, 0), + HSPHY_INIT_CFG(0x78, 0x08, 0), + HSPHY_INIT_CFG(0x7c, 0xdc, 0), + HSPHY_INIT_CFG(0x90, 0xe0, 20), + HSPHY_INIT_CFG(0x74, 0x10, 0), + HSPHY_INIT_CFG(0x90, 0x60, 0), +}; + +static const struct hsphy_data hsphy_data_qcs404 = { + .init_seq = init_seq_qcs404, + .init_seq_num = ARRAY_SIZE(init_seq_qcs404), +}; + +static const struct of_device_id qcom_snps_hsphy_match[] = { + { .compatible = "qcom,qcs404-usb-hsphy", .data = &hsphy_data_qcs404, }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_match); + +static struct platform_driver qcom_snps_hsphy_driver = { + .probe = qcom_snps_hsphy_probe, + .driver = { + .name = "qcom-qcs404-usb-hsphy", + .of_match_table = qcom_snps_hsphy_match, + }, +}; +module_platform_driver(qcom_snps_hsphy_driver); + +MODULE_DESCRIPTION("Qualcomm QCS404 Hi-Speed USB PHY driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Jan 15 14:13:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334917 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 842F41398 for ; Wed, 15 Jan 2020 14:15:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 62DC724680 for ; Wed, 15 Jan 2020 14:15:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="I31EknCz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730197AbgAOOPC (ORCPT ); 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Wed, 15 Jan 2020 06:13:10 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Jorge Ramirez-Ortiz , Jorge Ramirez-Ortiz , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH 04/19] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Date: Wed, 15 Jan 2020 14:13:18 +0000 Message-Id: <20200115141333.1222676-5-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed phy controller embedded in QCS404. Based on Sriharsha Allenki's original definitions. [bod: converted to yaml format] Signed-off-by: Jorge Ramirez-Ortiz Cc: Jorge Ramirez-Ortiz Cc: Rob Herring Cc: Mark Rutland Cc: Bjorn Andersson Cc: Jorge Ramirez-Ortiz Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- .../devicetree/bindings/qcom,usb-ss.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/qcom,usb-ss.yaml diff --git a/Documentation/devicetree/bindings/qcom,usb-ss.yaml b/Documentation/devicetree/bindings/qcom,usb-ss.yaml new file mode 100644 index 000000000000..fb0e399d64a0 --- /dev/null +++ b/Documentation/devicetree/bindings/qcom,usb-ss.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY. + +properties: + +- compatible: + enum: + - qcom,usb-ssphy + + reg: + maxItems: 1 + description: USB PHY base address and length of the register map. + + "#phy-cells": + const: 0 + description: Should be 0. See phy/phy-bindings.txt for details. + + clocks: + items: + - description: Block reference clock + - description: PHY AHB clock + - description: SuperSpeed pipe clock + + clock-names: + items: + - const: ref + - const: phy + - const: sleep + + vdd-supply: + maxItems: 1 + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + maxItems: 1 + description: phandle to the regulator 1.8V supply node. + + resets: + items: + - description: COM reset + - description: PHY reset line + + reset-names: + items: + - description: com + - description: phy + +Example: + +usb3_phy: usb3-phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; +}; From patchwork Wed Jan 15 14:13:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334907 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40A521398 for ; Wed, 15 Jan 2020 14:14:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0BAAF2467C for ; Wed, 15 Jan 2020 14:14:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BJ0Nmqok" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726553AbgAOOOx (ORCPT ); Wed, 15 Jan 2020 09:14:53 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:34798 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729765AbgAOONP (ORCPT ); Wed, 15 Jan 2020 09:13:15 -0500 Received: by mail-wr1-f67.google.com with SMTP id t2so15912025wrr.1 for ; Wed, 15 Jan 2020 06:13:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hkLW9376kNaAP2cCZzPr5DVWx2pUMEC0uQ4FLFt5LZQ=; b=BJ0Nmqok8hUc8auHcKInFCKanEh5yXgv+oFFu6tG/s9JmAoQ9+EDkziAcBHfixfKRl xoLEswjtvif04RRbIdnukoaItdfGjJHB5Ss8DPFor8lj/oeOmN2i465ouZh9jV1l5Thr wPBPht6X5QamhHCScSys+/0YVYLKdPbmTtrBHiw7I/YWckKQN4lG1+NqmiI6U4q4gGdc CJIWRH8jWWH71Vuv8LKVyTfN0qTjcfL9prJnPscyUt+pJ18HCL8rpq+IdTDdewwYchqa EBQ560+6ctFDUFytN6ChtNHVcT52zYSJjFU0lW1FU+9ccKuNNzZyTrRK2ayjuNiy8BAs tAHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hkLW9376kNaAP2cCZzPr5DVWx2pUMEC0uQ4FLFt5LZQ=; b=Zz7Pfhujm3NsFocjo92u+kmBf/Omi8YtgLRTRC+a1PXJdT+uGldTIf2Q3UqZE3akyx kyjn9t4inbSzAltQo1oaOahGEPSAiAMn+OqLtYTqKLnEjAjp+KMpA+gJiz5bh9E7wvQH NsuX5O4RHsyx7QET5HRzrfBzldI7V/xSkGxUFdeqYkzrBVFypF4BRLYHN/UcPkKlBT8W hViywdFgs8w+YOCS/a6fsx+75B9RVYvNdI042NqC8I6SgK6RAK0B+G019TsuSCXgaWbK 1y1SPynbSCJ28m1lQ9zFnymi3z+Ti1mylxEDnO/bwJ4gCQLzpVCZuiSNMaAZT0md8WCr +QtQ== X-Gm-Message-State: APjAAAUk8nzOLbnKn8s/WVMRoMD2QzJmwMbaFGTIfFFHTOTEf8OVWsyv b4FYTfNHHb0nrMatYRyx/VoAKpW9dsg= X-Google-Smtp-Source: APXvYqwbP21Tcnjjnh60DPljSutLNPdzleh4vLa6R5vpDk4janWSNyPS/+yWOuLYFSDEGvN8rbS/UQ== X-Received: by 2002:a5d:6a8e:: with SMTP id s14mr32359236wru.150.1579097591920; Wed, 15 Jan 2020 06:13:11 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:11 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Jorge Ramirez-Ortiz , Jorge Ramirez-Ortiz , Sriharsha Allenki's , Andy Gross , Kishon Vijay Abraham I , Philipp Zabel , Bryan O'Donoghue Subject: [PATCH 05/19] phy: qualcomm: usb: Add SuperSpeed PHY driver Date: Wed, 15 Jan 2020 14:13:19 +0000 Message-Id: <20200115141333.1222676-6-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Controls Qualcomm's SS phy 1.0.0 implemented in the QCS404 and some other Qualcomm platforms. Based on Sriharsha Allenki's original code. [bod: Removed dependency on extcon. Switched to gpio-usb-conn to handle VBUS On/Off Switched to usb-role-switch to bind gpio-usb-conn to DWC3] Signed-off-by: Jorge Ramirez-Ortiz Cc: Jorge Ramirez-Ortiz Cc: Sriharsha Allenki's Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Philipp Zabel Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- drivers/phy/qualcomm/Kconfig | 11 ++ drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-usb-ss.c | 246 +++++++++++++++++++++++++ 3 files changed, 258 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index cc3f2bb01ad1..d95602ec6515 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -101,3 +101,14 @@ config PHY_QCOM_QCS404_USB_HS Enable this to support the Qualcomm QCS404 USB Hi-Speed PHY driver. This driver supports the Hi-Speed PHY which is usually paired with either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. + +config PHY_QCOM_USB_SS + tristate "Qualcomm USB SS PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Super-Speed USB transceiver on Qualcomm + chips. This driver supports the PHY which uses the QSCRATCH-based + register set for its control sequences, normally paired with newer + DWC3-based Super-Speed controllers on Qualcomm SoCs. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index a4a3b21240fa..e8c7137cdbed 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o obj-$(CONFIG_PHY_QCOM_QCS404_USB_HS) += phy-qcom-qcs404-usb-hs.o +obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c new file mode 100644 index 000000000000..109e455cb509 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_CTRL0 0x6C +#define PHY_CTRL1 0x70 +#define PHY_CTRL2 0x74 +#define PHY_CTRL4 0x7C + +/* PHY_CTRL bits */ +#define REF_PHY_EN BIT(0) +#define LANE0_PWR_ON BIT(2) +#define SWI_PCS_CLK_SEL BIT(4) +#define TST_PWR_DOWN BIT(4) +#define PHY_RESET BIT(7) + +#define NUM_BULK_CLKS 3 +#define NUM_BULK_REGS 2 + +struct ssphy_priv { + void __iomem *base; + struct device *dev; + struct reset_control *reset_com; + struct reset_control *reset_phy; + struct regulator_bulk_data regs[NUM_BULK_REGS]; + struct clk_bulk_data clks[NUM_BULK_CLKS]; + enum phy_mode mode; +}; + +static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val) +{ + writel((readl(addr) & ~mask) | val, addr); +} + +static int qcom_ssphy_do_reset(struct ssphy_priv *priv) +{ + int ret; + + if (!priv->reset_com) { + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, + PHY_RESET); + usleep_range(10, 20); + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0); + } else { + ret = reset_control_assert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to assert reset com\n"); + return ret; + } + + ret = reset_control_assert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to assert reset phy\n"); + return ret; + } + + usleep_range(10, 20); + + ret = reset_control_deassert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset com\n"); + return ret; + } + + ret = reset_control_deassert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset phy\n"); + return ret; + } + } + + return 0; +} + +static int qcom_ssphy_power_on(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks); + if (ret) + goto err_disable_regulator; + + ret = qcom_ssphy_do_reset(priv); + if (ret) + goto err_disable_clock; + + writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); + + return 0; +err_disable_clock: + clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); +err_disable_regulator: + regulator_bulk_disable(NUM_BULK_REGS, priv->regs); + + return ret; +} + +static int qcom_ssphy_power_off(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); + + clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); + regulator_bulk_disable(NUM_BULK_REGS, priv->regs); + + return 0; +} + +static int qcom_ssphy_init_clock(struct ssphy_priv *priv) +{ + priv->clks[0].id = "ref"; + priv->clks[1].id = "phy"; + priv->clks[2].id = "pipe"; + + return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks); +} + +static int qcom_ssphy_init_regulator(struct ssphy_priv *priv) +{ + int ret; + + priv->regs[0].supply = "vdd"; + priv->regs[1].supply = "vdda1p8"; + ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(priv->dev, "Failed to get regulators\n"); + return ret; + } + + return ret; +} + +static int qcom_ssphy_init_reset(struct ssphy_priv *priv) +{ + priv->reset_com = devm_reset_control_get_optional(priv->dev, "com"); + if (IS_ERR(priv->reset_com)) { + dev_err(priv->dev, "Failed to get reset control com\n"); + return PTR_ERR(priv->reset_com); + } + + if (priv->reset_com) { + /* if reset_com is present, reset_phy is no longer optional */ + priv->reset_phy = devm_reset_control_get(priv->dev, "phy"); + if (IS_ERR(priv->reset_phy)) { + dev_err(priv->dev, "Failed to get reset control phy\n"); + return PTR_ERR(priv->reset_phy); + } + } + + return 0; +} + +static const struct phy_ops qcom_ssphy_ops = { + .power_off = qcom_ssphy_power_off, + .power_on = qcom_ssphy_power_on, + .owner = THIS_MODULE, +}; + +static int qcom_ssphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct ssphy_priv *priv; + struct phy *phy; + int ret; + + priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->mode = PHY_MODE_INVALID; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = qcom_ssphy_init_clock(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_reset(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_regulator(priv); + if (ret) + return ret; + + phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "Failed to create the SS phy\n"); + return PTR_ERR(phy); + } + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id qcom_ssphy_match[] = { + { .compatible = "qcom,usb-ssphy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_ssphy_match); + +static struct platform_driver qcom_ssphy_driver = { + .probe = qcom_ssphy_probe, + .driver = { + .name = "qcom-usb-ssphy", + .of_match_table = qcom_ssphy_match, + }, +}; +module_platform_driver(qcom_ssphy_driver); + +MODULE_DESCRIPTION("Qualcomm SuperSpeed USB PHY driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Jan 15 14:13:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334909 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DACEE1398 for ; Wed, 15 Jan 2020 14:14:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B8C1D24680 for ; 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Wed, 15 Jan 2020 06:13:12 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 06/19] dt-bindings: usb: dwc3: Add a gpio-usb-connector description Date: Wed, 15 Jan 2020 14:13:20 +0000 Message-Id: <20200115141333.1222676-7-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A USB connector should be a child node of the USB controller connector/usb-connector.txt. This patch adds a property "gpio_usb_connector" which declares a connector child device. Code in the DWC3 driver will then - Search for "gpio_usb_controller" - Do an of_platform_populate() if found This will have the effect of making the declared node a child of the USB controller and will make sure that USB role-switch events detected with the gpio_usb_controller driver propagate into the DWC3 controller code appropriately. Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/usb/dwc3.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 66780a47ad85..b019bd472f83 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -108,6 +108,9 @@ Optional properties: When just one value, which means INCRX burst mode enabled. When more than one value, which means undefined length INCR burst type enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. + - gpio_usb_connector: Declares a USB connector named 'gpio_usb_connector' as a + child node of the DWC3 block. Use when modelling a USB + connector based on the gpio-usb-b-connector driver. - in addition all properties from usb-xhci.txt from the current directory are supported as well @@ -121,4 +124,12 @@ dwc3@4a030000 { interrupts = <0 92 4> usb-phy = <&usb2_phy>, <&usb3,phy>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + usb_con: gpio_usb_connector { + compatible = "gpio-usb-b-connector"; + id-gpio = <&tlmm 116 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&pms405_gpios 12 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb3_vbus_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_id_pin>, <&usb3_vbus_pin>; + }; }; From patchwork Wed Jan 15 14:13:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334905 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C679E92A for ; Wed, 15 Jan 2020 14:14:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B5DD2467E for ; Wed, 15 Jan 2020 14:14:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="re9rv4mt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729530AbgAOOOv (ORCPT ); Wed, 15 Jan 2020 09:14:51 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:40948 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729863AbgAOONQ (ORCPT ); Wed, 15 Jan 2020 09:13:16 -0500 Received: by mail-wr1-f68.google.com with SMTP id c14so15889977wrn.7 for ; Wed, 15 Jan 2020 06:13:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lsykBhEyvK0tZ7Sd4nSOkkMUKoCrE9pE1rfSWJ5r3+Y=; b=re9rv4mtv2OupFAsIAflrMVaQ5iLA986NVX0PYx7p2ncjN9ucz0YjRo9/FfweSwxe3 QaMplo8e7KcdaMdxmnbpUtQdJPHtFLzz6onkTLQuasZc7XIqYDvkcoRATqBokRukh83J FTB3k+k8o+isRLeD6fDClnpYAqHmBpXYaKU/MvTFFsaTJnhB+X1I7UKDWKLh5BO8ZawB UsqSE2Pi1OhhpvZrRXrrdKmCutwVSDUc7LM8+abT5GP08OWzn1T+xuY5fXTvT+2RtUbC hERzbMLzOZSW5DfiIBSP+iGWr0Fxg9dZdP8MPG2ATSMzL3CcXxcQXvPihTXJxZDdomuv 6isA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lsykBhEyvK0tZ7Sd4nSOkkMUKoCrE9pE1rfSWJ5r3+Y=; b=Ip2g9uLlM+ZSBpfb4wN7zE1nUSWrED0CnzLgTqkzBRdql95VEE/7L4RwqQo0bF8LBM 1gtqps5ZpfrUOB78tz7XdD7trer/27m8WPkXDsBxlT1BhUZhZarpes8DEApdAa/SFSZm Kn6/K/88xACbr3Ia/UHGJs3+RNmz6ON5gFJV2ZqENENHtzidVVbdmW4LpMyDoxTUNBEi /l3MgZX8pwfQRmSQJOFdATQjU/ulyYsoChE2yCyLS9Fg8WkU2QFMVIJaggLwvZ7LBwvX nRCTskytRasuuxRMNdB2OWI52kjJitTSPzSU0RY9l2orprIMNx7cE9SC6VeJsFG7JLT3 fDsQ== X-Gm-Message-State: APjAAAWCuFkzJFzmDhCfdRYqW0+zpFlmOUqhjHm7uSZLOu1WBfZwd1zL sI8O0qRsGqs3BSFIjI9nDY6tOFqj/MY= X-Google-Smtp-Source: APXvYqy6NVkPsyluruYl9FEsemRuTWWOQAMmZ4B/CrP6jyssJX1DCcwUhweAdkXTLc085cWo12vvag== X-Received: by 2002:adf:f3cc:: with SMTP id g12mr31687879wrp.236.1579097594994; Wed, 15 Jan 2020 06:13:14 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:14 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Yu Chen , Rob Herring , Mark Rutland , ShuFan Lee , Heikki Krogerus , Suzuki K Poulose , Chunfeng Yun , Hans de Goede , Andy Shevchenko , Jun Li , Valentin Schneider , devicetree@vger.kernel.org, John Stultz , Bryan O'Donoghue Subject: [PATCH 07/19] usb: dwc3: Registering a role switch in the DRD code. Date: Wed, 15 Jan 2020 14:13:21 +0000 Message-Id: <20200115141333.1222676-8-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Yu Chen The Type-C drivers use USB role switch API to inform the system about the negotiated data role, so registering a role switch in the DRD code in order to support platforms with USB Type-C connectors. Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland CC: ShuFan Lee Cc: Heikki Krogerus Cc: Suzuki K Poulose Cc: Chunfeng Yun Cc: Yu Chen Cc: Felipe Balbi Cc: Hans de Goede Cc: Andy Shevchenko Cc: Jun Li Cc: Valentin Schneider Cc: Jack Pham Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Suggested-by: Heikki Krogerus Signed-off-by: Yu Chen Signed-off-by: John Stultz Signed-off-by: Bryan O'Donoghue --- drivers/usb/dwc3/core.h | 3 ++ drivers/usb/dwc3/drd.c | 77 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 77c4a9abe365..a99e57636172 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -953,6 +954,7 @@ struct dwc3_scratchpad_array { * @hsphy_mode: UTMI phy mode, one of following: * - USBPHY_INTERFACE_MODE_UTMI * - USBPHY_INTERFACE_MODE_UTMIW + * @role_sw: usb_role_switch handle * @usb2_phy: pointer to USB2 PHY * @usb3_phy: pointer to USB3 PHY * @usb2_generic_phy: pointer to USB2 PHY @@ -1086,6 +1088,7 @@ struct dwc3 { struct extcon_dev *edev; struct notifier_block edev_nb; enum usb_phy_interface hsphy_mode; + struct usb_role_switch *role_sw; u32 fladj; u32 irq_gadget; diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index c946d64142ad..3b57d2ddda93 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -476,6 +476,73 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) return edev; } +#ifdef CONFIG_USB_ROLE_SWITCH +#define ROLE_SWITCH 1 +static int dwc3_usb_role_switch_set(struct device *dev, enum usb_role role) +{ + struct dwc3 *dwc = dev_get_drvdata(dev); + u32 mode; + + switch (role) { + case USB_ROLE_HOST: + mode = DWC3_GCTL_PRTCAP_HOST; + break; + case USB_ROLE_DEVICE: + mode = DWC3_GCTL_PRTCAP_DEVICE; + break; + default: + mode = DWC3_GCTL_PRTCAP_DEVICE; + break; + } + + dwc3_set_mode(dwc, mode); + return 0; +} + +static enum usb_role dwc3_usb_role_switch_get(struct device *dev) +{ + struct dwc3 *dwc = dev_get_drvdata(dev); + unsigned long flags; + enum usb_role role; + + spin_lock_irqsave(&dwc->lock, flags); + switch (dwc->current_dr_role) { + case DWC3_GCTL_PRTCAP_HOST: + role = USB_ROLE_HOST; + break; + case DWC3_GCTL_PRTCAP_DEVICE: + role = USB_ROLE_DEVICE; + break; + case DWC3_GCTL_PRTCAP_OTG: + role = dwc->current_otg_role; + break; + default: + role = USB_ROLE_DEVICE; + break; + } + spin_unlock_irqrestore(&dwc->lock, flags); + return role; +} + +static int dwc3_setup_role_switch(struct dwc3 *dwc) +{ + struct usb_role_switch_desc dwc3_role_switch = {NULL}; + + dwc3_role_switch.fwnode = dev_fwnode(dwc->dev); + dwc3_role_switch.set = dwc3_usb_role_switch_set; + dwc3_role_switch.get = dwc3_usb_role_switch_get; + dwc->role_sw = usb_role_switch_register(dwc->dev, &dwc3_role_switch); + if (IS_ERR(dwc->role_sw)) + return PTR_ERR(dwc->role_sw); + + dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); + return 0; +} +#else +#define ROLE_SWITCH 0 +#define dwc3_setup_role_switch(x) 0 +#endif + int dwc3_drd_init(struct dwc3 *dwc) { int ret, irq; @@ -484,7 +551,12 @@ int dwc3_drd_init(struct dwc3 *dwc) if (IS_ERR(dwc->edev)) return PTR_ERR(dwc->edev); - if (dwc->edev) { + if (ROLE_SWITCH && + device_property_read_bool(dwc->dev, "usb-role-switch")) { + ret = dwc3_setup_role_switch(dwc); + if (ret < 0) + return ret; + } else if (dwc->edev) { dwc->edev_nb.notifier_call = dwc3_drd_notifier; ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST, &dwc->edev_nb); @@ -531,6 +603,9 @@ void dwc3_drd_exit(struct dwc3 *dwc) { unsigned long flags; + if (dwc->role_sw) + usb_role_switch_unregister(dwc->role_sw); + if (dwc->edev) extcon_unregister_notifier(dwc->edev, EXTCON_USB_HOST, &dwc->edev_nb); From patchwork Wed Jan 15 14:13:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334897 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5DEF692A for ; Wed, 15 Jan 2020 14:14:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3C3B72467C for ; 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Wed, 15 Jan 2020 06:13:15 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, John Stultz , Rob Herring , Mark Rutland , ShuFan Lee , Heikki Krogerus , Suzuki K Poulose , Chunfeng Yun , Yu Chen , Hans de Goede , Andy Shevchenko , Jun Li , Valentin Schneider , devicetree@vger.kernel.org, Rob Herring , Bryan O'Donoghue Subject: [PATCH 08/19] dt-bindings: usb: generic: Add role-switch-default-mode binding Date: Wed, 15 Jan 2020 14:13:22 +0000 Message-Id: <20200115141333.1222676-9-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: John Stultz Add binding to configure the default role the controller assumes is host mode when the usb role is USB_ROLE_NONE. Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland CC: ShuFan Lee Cc: Heikki Krogerus Cc: Suzuki K Poulose Cc: Chunfeng Yun Cc: Yu Chen Cc: Felipe Balbi Cc: Hans de Goede Cc: Andy Shevchenko Cc: Jun Li Cc: Valentin Schneider Cc: Jack Pham Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: John Stultz Signed-off-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/usb/generic.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic.txt b/Documentation/devicetree/bindings/usb/generic.txt index cf5a1ad456e6..dd733fa81fad 100644 --- a/Documentation/devicetree/bindings/usb/generic.txt +++ b/Documentation/devicetree/bindings/usb/generic.txt @@ -34,6 +34,12 @@ Optional properties: the USB data role (USB host or USB device) for a given USB connector, such as Type-C, Type-B(micro). see connector/usb-connector.txt. + - role-switch-default-mode: indicating if usb-role-switch is enabled, the + device default operation mode of controller while usb + role is USB_ROLE_NONE. Valid arguments are "host" and + "peripheral". Defaults to "peripheral" if not + specified. + This is an attribute to a USB controller such as: From patchwork Wed Jan 15 14:13:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334899 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8E1AA1398 for ; Wed, 15 Jan 2020 14:14:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6C3A22467D for ; Wed, 15 Jan 2020 14:14:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pqow9njW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729923AbgAOOOf (ORCPT ); Wed, 15 Jan 2020 09:14:35 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:37983 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729814AbgAOONT (ORCPT ); Wed, 15 Jan 2020 09:13:19 -0500 Received: by mail-wr1-f66.google.com with SMTP id y17so15907488wrh.5 for ; Wed, 15 Jan 2020 06:13:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ocnZYGpg6yFKKLUpsN1HHuLypXoe9Q32/jf1lCHrlrU=; b=pqow9njW0/Q1XGJtL1i64+9mYUWPAqmZv8Bfr9JREIoHHs3coqfVqdKQMeKZavmGOX xmlIVgQC65vTYDaLhFUHO4TZJl9Tk/1iF144e8YfYD3B71p473kUDlBrCLCtOIyEySqx TXQ2UQ5v33+cj2VnEXQYV2T9Syh0oV9vRaN4o7jOcqeVDWo5ZEWUIzMDOLPWNgxMCC+0 qJA7OyJ+WMq/PmNwAvrDWKkRqM9b6APULRtLFZDNPPURu0i7pPOFYjG+JXzYbEERHymy 2RW6RWIIi+PckKMnoJNaI11vOuhC7LE3WbKY5i4vs5HpBG66zARYlWmpL0PT6lHfLWsA KjWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ocnZYGpg6yFKKLUpsN1HHuLypXoe9Q32/jf1lCHrlrU=; b=qCqTetKRmP1vp56rJoKtAvxXHdfl+zw8wG1vtgfUVoB7th+9OBtTbMIl0l5HFBsu3E Nst/KekyIWZroYblHtOzmFjb5+wt8u0XGW/qbK+ZfBe8LhIusQkhhycbkz7OS3w4mQ3s zKmB+DK3hgFal/N8Ox2TmfjPmVocDyU5dmwNpeZTW92Y1m3bEfEXFYD+2M/jH3okkhYu 3tLeIUc4IPENsjwiTbxpylhfWBwwTiAWsqFcs7jNUy7US7zkgX0wKbARwC681/+6EzNj LmJ4XCMcKF6wCX878zI+GjZb+KW6ujrEK5YQuZXaHCpxoiWnyLtfIbZf0b7AfwJJd2Qm 6W0w== X-Gm-Message-State: APjAAAXdEHRq3IaUjpeR2XY0IaNWNObvyxVvvmuXVb8Pc2oBGovFworp 942npQewidSKtopASawrOh+AKRKw4kU= X-Google-Smtp-Source: APXvYqxiks20p1vcbhgJKtiiAPeYy/e3DCfR0VwT0lt4PoEXw/9zoQIkOTjCzZmAcH7P46O/oIgF7Q== X-Received: by 2002:a5d:6b82:: with SMTP id n2mr31524663wrx.153.1579097597704; Wed, 15 Jan 2020 06:13:17 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:17 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Lee Jones , Philipp Zabel Subject: [PATCH 09/19] usb: dwc3: qcom: Override VBUS when using gpio_usb_connector Date: Wed, 15 Jan 2020 14:13:23 +0000 Message-Id: <20200115141333.1222676-10-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Using the gpio_usb_connector driver also means that we are not supplying VBUS via the SoC but by an external PMIC directly. This patch searches for a gpio_usb_connector as a child node of the core DWC3 block and if found switches on the VBUS over-ride, leaving it up to the role-switching code in gpio-usb-connector to switch off and on VBUS. Cc: Andy Gross Cc: Bjorn Andersson Cc: Lee Jones Cc: Felipe Balbi Cc: Greg Kroah-Hartman Cc: Philipp Zabel Cc: linux-arm-msm@vger.kernel.org Cc: linux-usb@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- drivers/usb/dwc3/dwc3-qcom.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 261af9e38ddd..73f9f3bcec59 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -550,6 +550,16 @@ static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { .ss_phy_irq_index = 2 }; +static bool dwc3_qcom_find_gpio_usb_connector(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + + if (of_get_child_by_name(np, "gpio_usb_connector")) + return true; + + return false; +} + static int dwc3_qcom_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -557,7 +567,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev) struct dwc3_qcom *qcom; struct resource *res, *parent_res = NULL; int ret, i; - bool ignore_pipe_clk; + bool ignore_pipe_clk, gpio_usb_conn; qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); if (!qcom) @@ -649,9 +659,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev) } qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev); + gpio_usb_conn = dwc3_qcom_find_gpio_usb_connector(qcom->dwc3); - /* enable vbus override for device mode */ - if (qcom->mode == USB_DR_MODE_PERIPHERAL) + /* enable vbus override for device mode or GPIO USB connector mode */ + if (qcom->mode == USB_DR_MODE_PERIPHERAL || gpio_usb_conn) dwc3_qcom_vbus_overrride_enable(qcom, true); /* register extcon to override sw_vbus on Vbus change later */ From patchwork Wed Jan 15 14:13:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334889 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B733092A for ; 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Wed, 15 Jan 2020 06:13:19 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:18 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, John Stultz , Rob Herring , Mark Rutland , ShuFan Lee , Heikki Krogerus , Suzuki K Poulose , Chunfeng Yun , Yu Chen , Hans de Goede , Andy Shevchenko , Jun Li , Valentin Schneider , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH 10/19] usb: dwc3: Add support for role-switch-default-mode binding Date: Wed, 15 Jan 2020 14:13:24 +0000 Message-Id: <20200115141333.1222676-11-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: John Stultz Support the new role-switch-default-mode binding for configuring the default role the controller assumes as when the usb role is USB_ROLE_NONE This patch was split out from a larger patch originally by Yu Chen Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland CC: ShuFan Lee Cc: Heikki Krogerus Cc: Suzuki K Poulose Cc: Chunfeng Yun Cc: Yu Chen Cc: Felipe Balbi Cc: Hans de Goede Cc: Andy Shevchenko Cc: Jun Li Cc: Valentin Schneider Cc: Jack Pham Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz Signed-off-by: Bryan O'Donoghue --- drivers/usb/dwc3/core.h | 3 +++ drivers/usb/dwc3/drd.c | 25 ++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index a99e57636172..57d549a1ad0b 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -955,6 +955,8 @@ struct dwc3_scratchpad_array { * - USBPHY_INTERFACE_MODE_UTMI * - USBPHY_INTERFACE_MODE_UTMIW * @role_sw: usb_role_switch handle + * @role_switch_default_mode: default operation mode of controller while + * usb role is USB_ROLE_NONE. * @usb2_phy: pointer to USB2 PHY * @usb3_phy: pointer to USB3 PHY * @usb2_generic_phy: pointer to USB2 PHY @@ -1089,6 +1091,7 @@ struct dwc3 { struct notifier_block edev_nb; enum usb_phy_interface hsphy_mode; struct usb_role_switch *role_sw; + enum usb_dr_mode role_switch_default_mode; u32 fladj; u32 irq_gadget; diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index 3b57d2ddda93..865341facece 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -491,7 +491,10 @@ static int dwc3_usb_role_switch_set(struct device *dev, enum usb_role role) mode = DWC3_GCTL_PRTCAP_DEVICE; break; default: - mode = DWC3_GCTL_PRTCAP_DEVICE; + if (dwc->role_switch_default_mode == USB_DR_MODE_HOST) + mode = DWC3_GCTL_PRTCAP_HOST; + else + mode = DWC3_GCTL_PRTCAP_DEVICE; break; } @@ -517,7 +520,10 @@ static enum usb_role dwc3_usb_role_switch_get(struct device *dev) role = dwc->current_otg_role; break; default: - role = USB_ROLE_DEVICE; + if (dwc->role_switch_default_mode == USB_DR_MODE_HOST) + role = USB_ROLE_HOST; + else + role = USB_ROLE_DEVICE; break; } spin_unlock_irqrestore(&dwc->lock, flags); @@ -527,6 +533,19 @@ static enum usb_role dwc3_usb_role_switch_get(struct device *dev) static int dwc3_setup_role_switch(struct dwc3 *dwc) { struct usb_role_switch_desc dwc3_role_switch = {NULL}; + const char *str; + u32 mode; + int ret; + + ret = device_property_read_string(dwc->dev, "role-switch-default-mode", + &str); + if (ret >= 0 && !strncmp(str, "host", strlen("host"))) { + dwc->role_switch_default_mode = USB_DR_MODE_HOST; + mode = DWC3_GCTL_PRTCAP_HOST; + } else { + dwc->role_switch_default_mode = USB_DR_MODE_PERIPHERAL; + mode = DWC3_GCTL_PRTCAP_DEVICE; + } dwc3_role_switch.fwnode = dev_fwnode(dwc->dev); dwc3_role_switch.set = dwc3_usb_role_switch_set; @@ -535,7 +554,7 @@ static int dwc3_setup_role_switch(struct dwc3 *dwc) if (IS_ERR(dwc->role_sw)) return PTR_ERR(dwc->role_sw); - dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); + dwc3_set_mode(dwc, mode); return 0; } #else From patchwork Wed Jan 15 14:13:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334881 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 34C341398 for ; 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Wed, 15 Jan 2020 06:13:20 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:19 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , John Stultz , Lee Jones , Rob Herring , Mark Rutland , ShuFan Lee , Heikki Krogerus , Suzuki K Poulose , Chunfeng Yun , Yu Chen , Hans de Goede , Andy Shevchenko , Jun Li , Valentin Schneider , devicetree@vger.kernel.org Subject: [PATCH 11/19] usb: dwc3: Add support for usb-conn-gpio connectors Date: Wed, 15 Jan 2020 14:13:25 +0000 Message-Id: <20200115141333.1222676-12-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the ability to probe and enumerate a connector based on usb-conn-gpio. A device node label gpio_usb_connector is used to identify a usb-conn-gpio as a child of the USB interface. You would use usb-conn-gpio when a regulator in your system provides VBUS directly to the connector instead of supplying via the USB PHY. The parent device must have the "usb-role-switch" property, so that when the usb-conn-gpio driver calls usb_role_switch_set_role() the notification in dwc3 will run and the block registers will be updated to match the state detected at the connector. Cc: John Stultz Cc: Bjorn Andersson Cc: Lee Jones Cc: Greg Kroah-Hartman Cc: Rob Herring Cc: Mark Rutland CC: ShuFan Lee Cc: Heikki Krogerus Cc: Suzuki K Poulose Cc: Chunfeng Yun Cc: Yu Chen Cc: Felipe Balbi Cc: Hans de Goede Cc: Andy Shevchenko Cc: Jun Li Cc: Valentin Schneider Cc: Jack Pham Cc: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- drivers/usb/dwc3/drd.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index 865341facece..c6bb7cb809d5 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "debug.h" #include "core.h" @@ -557,9 +558,32 @@ static int dwc3_setup_role_switch(struct dwc3 *dwc) dwc3_set_mode(dwc, mode); return 0; } + +static int dwc3_register_gpio_usb_connector(struct dwc3 *dwc) +{ + struct device *dev = dwc->dev; + struct device_node *np = dev->of_node, *con_np; + int ret; + + con_np = of_get_child_by_name(np, "gpio_usb_connector"); + if (!np) { + dev_dbg(dev, "no usb_connector child node specified\n"); + return 0; + } + + ret = of_platform_populate(np, NULL, NULL, dev); + if (ret) { + dev_err(dev, "failed to register usb_connector - %d\n", ret); + return ret; + } + + return 0; +} + #else #define ROLE_SWITCH 0 #define dwc3_setup_role_switch(x) 0 +#define dwc3_register_gpio_usb_connector(x) 0 #endif int dwc3_drd_init(struct dwc3 *dwc) @@ -575,6 +599,9 @@ int dwc3_drd_init(struct dwc3 *dwc) ret = dwc3_setup_role_switch(dwc); if (ret < 0) return ret; + ret = dwc3_register_gpio_usb_connector(dwc); + if (ret < 0) + return ret; } else if (dwc->edev) { dwc->edev_nb.notifier_call = dwc3_drd_notifier; ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST, From patchwork Wed Jan 15 14:13:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334887 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6F81314B4 for ; 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Wed, 15 Jan 2020 06:13:21 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:21 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Vinod Koul , Shawn Guo , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH 12/19] arm64: dts: qcom: qcs404: Add USB devices and PHYs Date: Wed, 15 Jan 2020 14:13:26 +0000 Message-Id: <20200115141333.1222676-13-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson QCS404 sports HS and SS USB controllers based on dwc3 block with two HS PHYs and one SS PHY. Add nodes for these devices and enable them for EVB board. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 100 +++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index f5f0c4c9cb16..73565a5b99d1 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -272,6 +272,48 @@ rpm_msg_ram: memory@60000 { reg = <0x00060000 0x6000>; }; + usb3_phy: phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x00078000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + status = "disabled"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x0007a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x0007c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + qfprom: qfprom@a4000 { compatible = "qcom,qfprom"; reg = <0x000a4000 0x1000>; @@ -379,6 +421,64 @@ glink-edge { }; }; + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x07678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + status = "disabled"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x07580000 0xcd00>; + interrupts = ; + phys = <&usb2_phy_sec>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "otg"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x079b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + status = "disabled"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x078c0000 0xcc00>; + interrupts = ; + phys = <&usb2_phy_prim>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "peripheral"; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, From patchwork Wed Jan 15 14:13:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334849 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9A4301398 for ; Wed, 15 Jan 2020 14:13:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 78A2F24656 for ; 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Wed, 15 Jan 2020 06:13:22 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 13/19] arm64: dts: qcom: qcs404-evb: Define VBUS detect pin Date: Wed, 15 Jan 2020 14:13:27 +0000 Message-Id: <20200115141333.1222676-14-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org VBUS present/absent is presented to the SoC via a GPIO on the EVB. Define the pin mapping for later use by gpio-usb-conn. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 501a7330dbc8..6d53dc342f97 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -4,6 +4,8 @@ #include #include "qcs404.dtsi" #include "pms405.dtsi" +#include +#include / { aliases { @@ -270,6 +272,18 @@ rclk { }; }; +&pms405_gpios { + usb3_vbus_pin: usb3-vbus-pin { + pinconf { + pins = "gpio12"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + power-source = <1>; + }; + }; +}; + &wifi { status = "okay"; vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>; From patchwork Wed Jan 15 14:13:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334851 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2BEEB14B4 for ; Wed, 15 Jan 2020 14:13:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0AFA824671 for ; Wed, 15 Jan 2020 14:13:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="n5cjwfek" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730313AbgAOON0 (ORCPT ); Wed, 15 Jan 2020 09:13:26 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:37779 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730256AbgAOON0 (ORCPT ); Wed, 15 Jan 2020 09:13:26 -0500 Received: by mail-wm1-f67.google.com with SMTP id f129so18050691wmf.2 for ; Wed, 15 Jan 2020 06:13:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1UUsfm6fOWyuTi0Eboq7gj4QxZv+6wLGX1zbgK1JIts=; b=n5cjwfekoTs0bO7Gxvi12pv32MHjFchOy4wcgupRYkss/PEsjx3qEK66BQokfVb7Mg TKJkJFAde6xt/JPDtBi3nowq2BrdCqSacHLXdNkPDtQn4sq9KsZ9F9OmPcUwx697FhJF 5s0lR6MeA5p6sBKpNb/t77MqWSmjLy3S6oQspuEk01/JWWnK93i7/fY0o80Kx0f/dAea hqJ7M0m+3W3Cgsp1tjyMw+sZtOxPVfBHREC8P3YD0ED2Na36PFtNKqbhwoqlis8wzRLw NI2DOtC9GOHyKpzbjZnaMdM9BuqxTthrTBcyFuqQyt0yDhFXkYGTspqouOpNmPVIbC1Y 58Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1UUsfm6fOWyuTi0Eboq7gj4QxZv+6wLGX1zbgK1JIts=; b=TeE7N7RPo9vM1Kwv6buqWU9EUNhs8QK7nnaEzAW3k4nwZsEMY6We7kIaKC32P+40Uc JUSINlDnI2cjUtDC3mREX06dXXQKMI8FxmAAjvoW3/84sn7N991UMOoJ1tpxMjUYePXi LBzEKyjaIlfao76RZWI4yYYcD7tz+UiRjj9Tz13YqeF3bCF0w19wTrvtGzen28qqOlbY 4zS3wDqPQkr299nAsYCNRvvpTshF53uroWC6+L7hEWLrxoOBsEwGU/zk1bqz2t1vhNCk vBVGOLIJqn9H0p1cKFJsspnYI9Ju6XIatJnuQanbRp2wgHGRhWKfDf2BWe8NHZL2Izmp CVyA== X-Gm-Message-State: APjAAAV+N2RgaaOsnRM9UQlC4cXhdzEPyRUMQ2a7sA1nmRufh2YaJkOR gYTW6nK0HoEHZR+/G+hpwcObtCoJBB8= X-Google-Smtp-Source: APXvYqyfm3VxeVbpM723JQEBDho1BTKeTG1rCAIcodpK1fXm1E5JFt7BimzeXmAV1Uoc+Vrw7qiSvg== X-Received: by 2002:a05:600c:10cd:: with SMTP id l13mr35273221wmd.102.1579097604577; Wed, 15 Jan 2020 06:13:24 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:23 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 14/19] arm64: dts: qcom: qcs404-evb: Define VBUS boost pin Date: Wed, 15 Jan 2020 14:13:28 +0000 Message-Id: <20200115141333.1222676-15-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org An external regulator is used to trigger VBUS on/off via GPIO. This patch defines the relevant GPIO in the EVB dts. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 6d53dc342f97..b6147b5ab5cb 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -273,6 +273,14 @@ rclk { }; &pms405_gpios { + usb_vbus_boost_pin: usb-vbus-boost-pin { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = <1>; + }; + }; usb3_vbus_pin: usb3-vbus-pin { pinconf { pins = "gpio12"; From patchwork Wed Jan 15 14:13:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B95301398 for ; Wed, 15 Jan 2020 14:13:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 96EA924671 for ; Wed, 15 Jan 2020 14:13:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XmC1dJuO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730321AbgAOON2 (ORCPT ); Wed, 15 Jan 2020 09:13:28 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:43490 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729339AbgAOON2 (ORCPT ); Wed, 15 Jan 2020 09:13:28 -0500 Received: by mail-wr1-f68.google.com with SMTP id d16so15893170wre.10 for ; Wed, 15 Jan 2020 06:13:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V6kruRPkzy9lVUH/jwLgwsWhMI5CPdJk0wrirvWcE1I=; b=XmC1dJuO81CGqj/1DjpnBnet4KWs+DmVLk0IceBrNH8qWCQTOEr2Nkf57H5Q14EQhV i4bB9tyC/0+OD6WEYz+vOo/eusiY3zjJZVzHv0l0JaN0+dSZsOJI9Pi8/kTDRvYAdEWn EsKl9sD/GRwZ/UAPez95HVEsSR1ZW/n2X+cRs/la9bARu/lddlNj9NOUVXntWMn52jgx PM5XB0fKhlvqpTKJiGv3XNIR9fUGhfDxNWhRjRHaL5b3nkiTy9NY2uf3cx1joPRTl8V2 mMKO3dEATrbvFMkVz360LJvZyG4/9mQAqbekxw/CKOBQjg31PvP3edJRClwF3RQB3piH KmtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V6kruRPkzy9lVUH/jwLgwsWhMI5CPdJk0wrirvWcE1I=; b=frp/9Y6yw82JzSg3rONoM/m5XqiBO7O0/4xKaYObchn0y3MrqED6CwUa6ZWAoHIbqP RWgFxvPfC9MbknkHN/YiPeZizOXI6M+d2ycrIB/snll1TBI0XT1Q41z3iQMkT0RnVq3V miu3SCsRR5Q2wbxgbl/AF+vDVfl12W1u+VUHeY2/nA6tRGCZFE3OCw9U6nLY/5y7zZnP SXuwB7cBrV/F44EGjqoN23WLWBANgP86jw0JTETn08OBjeMCSh2V8uGc6a/GJcPEFL+W bCtcjsolrAYmi/7HlyK52fm1mtXAvfKhK9T7GM1ZWJe8V34h+XUxPy6ZhNzVjxKEbNhU VlZA== X-Gm-Message-State: APjAAAVjjSNR2os/bqHmZ/CcNLI6bbjqzrizy7BIaZGDX8IfJ2XBOZBE yiH/e8RALM/xpO74TMb6j6VJ7D72gxw= X-Google-Smtp-Source: APXvYqwobBcHZcRU3dqh7kWlkczK59C7gnida7SLcEdxJmjxzH20IAc+sKhPA2AJrfd823TrJbaNBw== X-Received: by 2002:adf:f484:: with SMTP id l4mr31382687wro.207.1579097605667; Wed, 15 Jan 2020 06:13:25 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:25 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 15/19] arm64: dts: qcom: qcs404-evb: Define USB ID pin Date: Wed, 15 Jan 2020 14:13:29 +0000 Message-Id: <20200115141333.1222676-16-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The USB ID pin is used to tell if a system is a Host or a Device. For our purposes we will bind this pin into gpio-usb-conn later. For now define the pin with its pinmux. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index b6147b5ab5cb..abfb2a9a37e9 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -270,6 +270,20 @@ rclk { bias-pull-down; }; }; + + usb3_id_pin: usb3-id-pin { + pinmux { + pins = "gpio116"; + function = "gpio"; + }; + + pinconf { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; }; &pms405_gpios { From patchwork Wed Jan 15 14:13:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334857 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EBEC292A for ; Wed, 15 Jan 2020 14:13:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CA5FD24679 for ; Wed, 15 Jan 2020 14:13:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="gs/z4tk4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728890AbgAOON3 (ORCPT ); Wed, 15 Jan 2020 09:13:29 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:38000 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730256AbgAOON3 (ORCPT ); Wed, 15 Jan 2020 09:13:29 -0500 Received: by mail-wr1-f68.google.com with SMTP id y17so15908056wrh.5 for ; Wed, 15 Jan 2020 06:13:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OAQIBEtAB539ew/tof0mNoTYE3sNhscOlsV6pfoQF5g=; b=gs/z4tk4uFXXpj/yR4pB6Y9QVxyxwScRANH5ordeJtq8PSbgKFB4RS0FmPEndaNOby idsxHHb+xh0XR7tA+nsp+f73HnB0SIKRMWzbLQIy1MPD1zYGnGc7Gi4on33Dqg3SxtSs I2mFJf47QTsU0r37z588nkk1sKl//Rc6r0f2EX90EmZnJ0EWSkQbeaeYMYrUGiPtrFFF EFQUQQIEXBhARL4asIi7vRhf4bjU67B4PLotwT6jfw8+IDgEu33xSFja/esqsDtDexMN KEanjCsHPesyOLZrnA3QKbuklE1CMcHj4VRrrtH3qijobgMMNtwEf/Q/CRDyD6rdsKfo i6QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OAQIBEtAB539ew/tof0mNoTYE3sNhscOlsV6pfoQF5g=; b=iTZdHwXdYyJ6Vk2dISgOuc5n6CvLGNFLBhkaU3lzlVxLyu3ahT2PIj7TPF6znD4jdZ sqRfgVz/UKyFZdyVYapXHpIHnB0cHdrXST4hyz90eH9RBsdTnQJ2YVbs74JTixiJh1S3 8Nrr9L8x1f9hUhL81iNVSvhMsNF2rvgKnwGhgUQs+vTa0g/ljFqbMzRB9a1Go1uf6u7L V6ZBytxCPN9dBriZgxScv3yoC9xLD6Slk+WWo3FbAWzW2MWb0kH62SEswa43BINfpEEy rMsFF7QLGEIz6IbrvvEV1AGYGS99gJmeh+wX+7HiPvGEO2/Cq49fPSfFO6VbJYOrLKOW 5cPw== X-Gm-Message-State: APjAAAUeSp8sv3uDvX/d2WshDk84Pvflk8a++cXsKDTL5H/WUlbQITaw Sr1+7lPZ8WsSgf4G1X+lOB4xhXWFv5I= X-Google-Smtp-Source: APXvYqzBNIB6sLizgF8/elzXx2JKJwR3Qm2h8MtVZZ6TJ6hyaGw3jAbQWdFFHKTn2qlDFLT5G/I1vQ== X-Received: by 2002:a5d:4481:: with SMTP id j1mr32581677wrq.348.1579097607065; Wed, 15 Jan 2020 06:13:27 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:26 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 16/19] arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator Date: Wed, 15 Jan 2020 14:13:30 +0000 Message-Id: <20200115141333.1222676-17-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org VBUS is supplied by an external regulator controlled by a GPIO pin. This patch models the regulator as regulator-usb3-vbus. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index abfb2a9a37e9..01ef59e8e5b7 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -33,6 +33,18 @@ vdd_esmps3_3p3: vdd-esmps3-3p3-regulator { regulator-max-microvolt = <3300000>; regulator-always-on; }; + + usb3_vbus_reg: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_BOOST_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_vbus_boost_pin>; + vin-supply = <&vph_pwr>; + enable-active-high; + }; }; &blsp1_uart3 { From patchwork Wed Jan 15 14:13:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334871 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A17BC1398 for ; Wed, 15 Jan 2020 14:13:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7F76C24671 for ; Wed, 15 Jan 2020 14:13:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="h2avPzgt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730540AbgAOONq (ORCPT ); Wed, 15 Jan 2020 09:13:46 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:41521 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729526AbgAOONa (ORCPT ); Wed, 15 Jan 2020 09:13:30 -0500 Received: by mail-wr1-f68.google.com with SMTP id c9so15894043wrw.8 for ; Wed, 15 Jan 2020 06:13:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=utrms9phUtFiuVDkbSHkMcIIB+hqEFiylLVtYFCLs98=; b=h2avPzgtHS2x2OYDax1t4VNWKLqty6XA4E9ZjqJab0pKdQByRf1PEj7tqgfbT1rFOC +tENLeDKBOT8PQfZQe4cJQdhBk5tDerzipgC46tWGHbhhRloQqY8NwK1VT/2R2mK4Kzn HnmQjbZbdO0t1U07yQe5h3IcPXYY7KVs51OCDTYJ7FEJa/dKyH7I0jB53geercfQdC7X NBdP4Gr+LnIaavxzM3YZP+XkJUNe5G7KuTt9eLSjyv7pVluSs06/y2ulrPilSIYBrFtl asFezWef6PblRiEpOXxP1wUQcQHrUtHDJm5iDEE6KAyGtXOMq1YXk3HbGOAsY1DGaaTT WNGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=utrms9phUtFiuVDkbSHkMcIIB+hqEFiylLVtYFCLs98=; b=V5kUQHqlm+AbVGcWdlIy9kTTk6RW8UTRb3Xke9/9iywzeVhyydjC4f3KezblsOIwte pdfMBE8Wtk81Bj2j8ewVXMfmZN6YtfjLMMLwOOPboqCHosb766yRSkmiDRKeXakuRlng 3aDmOugF+sCNsjuDgS+4jd4kmTogr3SIDMoY5eCL0JqQixcc3v8IwzkhTiThm8wqrBAw ZAhdOPV+n9UsF6WdLcRpA9bqd4WXl9qEMkmc8/7Yxc9o8R1QF9EUCxMeUb+UDx7xVVJm OuJLXP5eLQNx2TJilc3RKVxvJUlS49ajoHHsoJl2NSxmJ8lS5oFhKYQG2zFYiYPly/AJ 6HRg== X-Gm-Message-State: APjAAAVXVt/QyGB9MRDAtlunX6Xs/GElWsV4fjvmXXlpqSKhQqnOihhW 3d7jxfyqISrTpIm2bJLTt7LM4fbSlb0= X-Google-Smtp-Source: APXvYqyTuamJ9fHx0PYuc9zHO/uCqxLay9MiZeaYDixnvT9qgiT7T1DxVJet5UBmYWb5t8PaSKTN9A== X-Received: by 2002:a5d:6a8e:: with SMTP id s14mr32360617wru.150.1579097608303; Wed, 15 Jan 2020 06:13:28 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:27 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 17/19] arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage Date: Wed, 15 Jan 2020 14:13:31 +0000 Message-Id: <20200115141333.1222676-18-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rather than set the minimum microvolt for this regulator in the USB SS PHY driver, set it in the DTS. Suggested-by: Bjorn Andersson Cc: Andy Gross Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 01ef59e8e5b7..0fff50f755ef 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -199,7 +199,7 @@ vreg_l11_sdc2: l11 { }; vreg_l12_3p3: l12 { - regulator-min-microvolt = <2968000>; + regulator-min-microvolt = <3050000>; regulator-max-microvolt = <3300000>; }; From patchwork Wed Jan 15 14:13:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334863 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DAB3792A for ; Wed, 15 Jan 2020 14:13:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B96672467D for ; Wed, 15 Jan 2020 14:13:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="wCQz6rlV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728899AbgAOONc (ORCPT ); Wed, 15 Jan 2020 09:13:32 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:38005 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730370AbgAOONb (ORCPT ); Wed, 15 Jan 2020 09:13:31 -0500 Received: by mail-wr1-f68.google.com with SMTP id y17so15908183wrh.5 for ; Wed, 15 Jan 2020 06:13:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=77YZKi21/UFq8ab0fDgwp8wX61rx924yS+pIUFv8pqU=; b=wCQz6rlV/caolVVopEqfe57+az1sdm5RSdCHSFdWGeF4WYqBkG9XXDkH4HF8pgsJ+5 llOyCpeZIWYHO2nKQS9WOgJQqccwJC/cSYFhDjjJ000GH6McGos4apLez8qtzikjBV6C tfRNjGjtvoHSx/VoE/x8iFT8uLHY6BQSa8EX2AQ3LNwL1BUhgRNb4Yt7JWwDZ6H8hssB hbDU8pQmBQA3R33RahIPV1mSqNuBdyRWqQGj1v8iNp+FSxKSMt68XHu8N6xC4PjoKhQ5 JJZ7Gv9vs9jg9glxHvRVP3AyGVpV08yMolIZ3X3mRrQBnHr9UrInllWHXos+IBij/jvY 85Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=77YZKi21/UFq8ab0fDgwp8wX61rx924yS+pIUFv8pqU=; b=eX9n6zGJm1T0i2U0tTLNbP2UwXyUiUsHd/Xeidr/eD0U9FwihlrN9sAONuXdsjG3sY Vne7i+Nsn7vcQoSsgJ1aakNHFwSu1YCfTVzkq0/axRa5tJtyqywewjk/bO9huIUZrZU+ OlbXLP4UhhlxFp/86SSiYT3kslEdn1A3q9Txc6UFfx7r1EtMZgdQBWialvBRsKaRlByT oByP439z/jqPRXDeBVptrpDB1j2L/RgaSMYm4QKmehcdgCrVIcvj4XHc9BY9MSAo8AN6 gZhcIzEpzciwHBvtLSrDgGBmUlFwKg2tifCgA8JkUBw2W3IskskrrlA0V2dG8VVa72/+ +p0Q== X-Gm-Message-State: APjAAAV8Ct3b9A2xJVRK/dvoi+hzkexCLkvnb2RRmDSF/LGNDCKzklcg 2IPY4aPWuo4YqTjr41gkmy8UKUa/qQU= X-Google-Smtp-Source: APXvYqyrN4dg5SAaK8uSWRpjXcMLagOgensqOz0vk3mNJsx/Gh/cXJYEd3RmoRtdbliIPlXHsKJ3Mg== X-Received: by 2002:adf:ec4c:: with SMTP id w12mr30586906wrn.124.1579097609430; Wed, 15 Jan 2020 06:13:29 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:28 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 18/19] arm64: dts: qcom: qcs404-evb: Enable secondary USB controller Date: Wed, 15 Jan 2020 14:13:32 +0000 Message-Id: <20200115141333.1222676-19-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch enables the second DWC3 controller which has one USB Hi-Speed PHY attached to it. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 0fff50f755ef..07d6d793a922 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -318,6 +318,17 @@ pinconf { }; }; +&usb2 { + status = "okay"; +}; + +&usb2_phy_sec { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + &wifi { status = "okay"; vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>; From patchwork Wed Jan 15 14:13:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 11334867 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BBAAA1398 for ; Wed, 15 Jan 2020 14:13:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9A14A24671 for ; Wed, 15 Jan 2020 14:13:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bgELX9jo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729288AbgAOONh (ORCPT ); Wed, 15 Jan 2020 09:13:37 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:37796 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730390AbgAOONc (ORCPT ); Wed, 15 Jan 2020 09:13:32 -0500 Received: by mail-wm1-f67.google.com with SMTP id f129so18051201wmf.2 for ; Wed, 15 Jan 2020 06:13:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r9NPS5QGribeTtMFFZTTzMj+ynOYdzhVsWBEen9DiAQ=; b=bgELX9joHOCF4c8wcg5bLvZ9uHtZsi/3FsyK//KbYPrUw6pN7LvXNBNEYrxRO70Rop nn+AUaycmrXtYvRkeR229xqVRDf2p3kJhulb6igviGwnVBB+42wXPIqCsJraKKpEeWJ1 CNeSvEpPmTnxXV7Koldzqb7XJl9y2viuiic6LeLAjr+xw2fdEeXszuCLtRfgyLkuHhRt eeMH73fnDAijT9U+X3STFKKzoU1lUx/oEfciCREPiErwhsKX249VKOAmAsMJolHzANSI SdBZfet0PZITXICNmLt778RTkTaL1pspzH57s9CdzN2nlTXpK8PDU5ajo3mSRh7uSy8D LEfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r9NPS5QGribeTtMFFZTTzMj+ynOYdzhVsWBEen9DiAQ=; b=BBqE8IiHZvoj3+Ox3JjZAo5rWga1qMKrd1uXIreq4jWOA+frfjvDD9Toxxhxw0jN9E HUztTcJKdb+Wm4mDJ43SDuOZIYH1zM0co9YtRrokr047m1ImsQX5wE0pfZ5hC2z4WK/O uqi1GBnJQ4ZVC4ywxxCcaVJ/Z3OOnce2SPTy6uAXzkbDqDoOpE7BfmzBnDvR6pMtqY5g rcrMZV3849t8boQTe92xFJC6h3x40ci+BIl9wI302kjTuy6iQipbA+370R5QixXWhi4c sM+624kIx1fxzCKEVDiQtpe3oiJ05QXfL7/pqF9KsXcAXkXX05XXmJPQp5J1vWB1UJBT Y7yQ== X-Gm-Message-State: APjAAAXrow4TjxiN6ZEYQwM/TZjySoksdhDiU/RrDswXd4XCxcsehemT ojbdyVsnt/hsg21t0MCryS/h0jb3fXY= X-Google-Smtp-Source: APXvYqw76gxyIdAYFEPqMKjvpzCtwovsDXs6SfcdlT6dpAzF6V+7DXdlLmrcgH28IHX9zjYJMtFEPg== X-Received: by 2002:a7b:cc6a:: with SMTP id n10mr35195527wmj.170.1579097610665; Wed, 15 Jan 2020 06:13:30 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id m21sm23730720wmi.27.2020.01.15.06.13.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2020 06:13:30 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andy Gross , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 19/19] arm64: dts: qcom: qcs404-evb: Enable primary USB controller Date: Wed, 15 Jan 2020 14:13:33 +0000 Message-Id: <20200115141333.1222676-20-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> References: <20200115141333.1222676-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch enables the primary USB controller which has - One USB3 SS PHY using gpio-usb-conn - One USB2 HS PHY in device mode only and no connector driver associated. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 29 ++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 07d6d793a922..a2cbca3a6124 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -329,6 +329,35 @@ &usb2_phy_sec { status = "okay"; }; +&usb3 { + status = "okay"; + dwc3@7580000 { + usb-role-switch; + usb_con: gpio_usb_connector { + compatible = "gpio-usb-b-connector"; + label = "USB-C"; + id-gpio = <&tlmm 116 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb3_vbus_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_id_pin>, <&usb3_vbus_pin>; + status = "okay"; + }; + }; +}; + +&usb2_phy_prim { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + +&usb3_phy { + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + status = "okay"; +}; + &wifi { status = "okay"; vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;