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Thu, 16 Jan 2020 00:41:14 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 Jan 2020 00:41:12 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 16 Jan 2020 16:40:43 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 16 Jan 2020 16:40:20 +0800 From: To: Hans Verkuil , Alexandre Courbot , Mauro Carvalho Chehab , "Matthias Brugger" , Thomas Gleixner , Tomasz Figa Subject: [PATCH][v2] media: mtk-vcodec: reset segment data then trig decoder Date: Thu, 16 Jan 2020 16:41:02 +0800 Message-ID: <20200116084102.5079-1-gtk_ruiwang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200116_004122_485890_97AA7D46 X-CRM114-Status: GOOD ( 11.88 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [216.200.240.184 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gtk_ruiwang@mediatek.com, Maoguang Meng , srv_heupstream@mediatek.com, Yunfei Dong , Longfei Wang , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Tiffany Lin , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: gtk_ruiwang VP9 bitstream specification indicate segment data should reset to default when meet key frames, intra only frames or enable error resilience mode. So memset segmentation map buffer before every decode process is not appropriate. Reset segment data only when needed, then start decoder hardware Signed-off-by: Rui Wang --- Changed in v2: - add bit3&bit4 for kernel and vpu-firmware compatibility --- .../platform/mtk-vcodec/vdec/vdec_vp9_if.c | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c index 24c1f0bf2147..083aeca288f6 100644 --- a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c @@ -110,7 +110,11 @@ struct vp9_sf_ref_fb { * @buf_len_sz_c : size used to store cbcr plane ufo info (AP-R, VPU-W) * @profile : profile sparsed from vpu (AP-R, VPU-W) - * @show_frame : display this frame or not (AP-R, VPU-W) + * @show_frame : [BIT(0)] display this frame or not (AP-R, VPU-W) + * [BIT(1)] reset segment data or not (AP-R, VPU-W) + * [BIT(2)] trig decoder hardware or not (AP-R, VPU-W) + * [BIT(3)] notify VPU set decoder behavior (AP-W, VPU-R) + * [BIT(4)] do not reset segment data before every frame (AP-R, VPU-W) * @show_existing_frame : inform this frame is show existing frame * (AP-R, VPU-W) * @frm_to_show_idx : index to show frame (AP-R, VPU-W) @@ -494,12 +498,12 @@ static void vp9_swap_frm_bufs(struct vdec_vp9_inst *inst) frm_to_show->fb->base_y.size); } if (!vp9_is_sf_ref_fb(inst, inst->cur_fb)) { - if (vsi->show_frame) + if (vsi->show_frame & BIT(0)) vp9_add_to_fb_disp_list(inst, inst->cur_fb); } } else { if (!vp9_is_sf_ref_fb(inst, inst->cur_fb)) { - if (vsi->show_frame) + if (vsi->show_frame & BIT(0)) vp9_add_to_fb_disp_list(inst, frm_to_show->fb); } } @@ -800,6 +804,9 @@ static int vdec_vp9_init(struct mtk_vcodec_ctx *ctx) } inst->vsi = (struct vdec_vp9_vsi *)inst->vpu.vsi; + + inst->vsi->show_frame |= BIT(3); + init_all_fb_lists(inst); ctx->drv_handle = inst; @@ -870,13 +877,27 @@ static int vdec_vp9_decode(void *h_vdec, struct mtk_vcodec_mem *bs, vsi->sf_frm_sz[idx]); } } - memset(inst->seg_id_buf.va, 0, inst->seg_id_buf.size); + + if (!(vsi->show_frame & BIT(4))) + memset(inst->seg_id_buf.va, 0, inst->seg_id_buf.size); + ret = vpu_dec_start(&inst->vpu, data, 3); if (ret) { mtk_vcodec_err(inst, "vpu_dec_start failed"); goto DECODE_ERROR; } + if (vsi->show_frame & BIT(1)) { + memset(inst->seg_id_buf.va, 0, inst->seg_id_buf.size); + + if (vsi->show_frame & BIT(2)) { + if (vpu_dec_start(&inst->vpu, NULL, 0)) { + mtk_vcodec_err(inst, "vpu trig decoder failed"); + goto DECODE_ERROR; + } + } + } + ret = validate_vsi_array_indexes(inst, vsi); if (ret) { mtk_vcodec_err(inst, "Invalid values from VPU.");