From patchwork Thu Jan 16 23:11:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11337943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6BAC9139A for ; Thu, 16 Jan 2020 23:12:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 53F962081E for ; Thu, 16 Jan 2020 23:12:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730992AbgAPXMI (ORCPT ); Thu, 16 Jan 2020 18:12:08 -0500 Received: from foss.arm.com ([217.140.110.172]:34046 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729336AbgAPXMI (ORCPT ); Thu, 16 Jan 2020 18:12:08 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DAA4D11FB; Thu, 16 Jan 2020 15:12:07 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 00CC33F68E; Thu, 16 Jan 2020 15:12:05 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Cc: linux-spi@vger.kernel.org, Mark Brown , Icenowy Zheng , Mark Rutland , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, devicetree@vger.kernel.org Subject: [PATCH v3 1/3] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes Date: Thu, 16 Jan 2020 23:11:46 +0000 Message-Id: <20200116231148.1490-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20200116231148.1490-1-andre.przywara@arm.com> References: <20200116231148.1490-1-andre.przywara@arm.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, but with the added capability of 3-wire and 4-wire operation modes. For now the driver does not support those, but the SPI registers are fully backwards-compatible, just adding bits and registers which were formerly reserved. So we can use the existing driver in "legacy" SPI modes, for instance to access the SPI NOR flash soldered on the PineH64 board. We use an H6 specific compatible string in addition to the existing H3 string, so when the driver later gains QSPI support, it should work automatically without any DT changes. Tested by accessing the SPI flash on a Pine H64 board (SPI0), also connecting another SPI flash to the SPI1 header pins. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 3329283e38ab..41b58ffa8596 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -338,6 +338,31 @@ bias-pull-up; }; + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC0", "PC2", "PC3"; + function = "spi0"; + }; + + /* pin shared with MMC2-CMD (eMMC) */ + /omit-if-no-ref/ + spi0_cs_pin: spi0-cs-pin { + pins = "PC5"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pins: spi1-pins { + pins = "PH4", "PH5", "PH6"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs_pin: spi1-cs-pin { + pins = "PH3"; + function = "spi1"; + }; + spdif_tx_pin: spdif-tx-pin { pins = "PH7"; function = "spdif"; @@ -504,6 +529,36 @@ #size-cells = <0>; }; + spi0: spi@5010000 { + compatible = "allwinner,sun50i-h6-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05010000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@5011000 { + compatible = "allwinner,sun50i-h6-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05011000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@5020000 { compatible = "allwinner,sun50i-h6-emac", "allwinner,sun50i-a64-emac"; From patchwork Thu Jan 16 23:11:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11337945 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C67D36C1 for ; Thu, 16 Jan 2020 23:12:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A59F82072B for ; Thu, 16 Jan 2020 23:12:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388115AbgAPXMK (ORCPT ); Thu, 16 Jan 2020 18:12:10 -0500 Received: from foss.arm.com ([217.140.110.172]:34060 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729336AbgAPXMK (ORCPT ); Thu, 16 Jan 2020 18:12:10 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D3F4D11D4; Thu, 16 Jan 2020 15:12:09 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2723C3F68E; Thu, 16 Jan 2020 15:12:08 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Cc: linux-spi@vger.kernel.org, Mark Brown , Icenowy Zheng , Mark Rutland , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, devicetree@vger.kernel.org Subject: [PATCH v3 2/3] arm64: dts: allwinner: h6: Pine H64: Add SPI flash node Date: Thu, 16 Jan 2020 23:11:47 +0000 Message-Id: <20200116231148.1490-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20200116231148.1490-1-andre.przywara@arm.com> References: <20200116231148.1490-1-andre.przywara@arm.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The Pine H64 board comes with SPI flash soldered on the board, connected to the SPI0 pins (so it can also boot from there). Add the required SPI flash DT node to describe this. Unfortunately the SPI CS0 pin collides with the eMMC CMD pin, so we can't use both eMMC and SPI flash at the same time (the first to claim the pin would win, the other's probe routine would then fail). To avoid losing the more useful eMMC device by chance, mark the SPI device as "disabled" for now. A user or some U-Boot code could fix this up if needed, for instance if no eMMC has been detected (it's socketed). Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index d1c2aa5b3a20..3c9dd0d69754 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -14,6 +14,7 @@ aliases { ethernet0 = &emac; serial0 = &uart0; + spi0 = &spi0; }; chosen { @@ -278,6 +279,24 @@ vcc-pm-supply = <®_aldo1>; }; +/* + * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI + * flash and eMMC at the same time, as one of them would fail probing. + * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can + * fix this up in no eMMC is connected. + */ +&spi0 { + pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>; + pinctrl-names = "default"; + status = "disabled"; + + flash@0 { + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; From patchwork Thu Jan 16 23:11:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11337947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0595C6C1 for ; Thu, 16 Jan 2020 23:12:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D6B192077B for ; Thu, 16 Jan 2020 23:12:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389798AbgAPXMM (ORCPT ); Thu, 16 Jan 2020 18:12:12 -0500 Received: from foss.arm.com ([217.140.110.172]:34078 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729336AbgAPXMM (ORCPT ); Thu, 16 Jan 2020 18:12:12 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA9BF11FB; Thu, 16 Jan 2020 15:12:11 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 208A63F68E; Thu, 16 Jan 2020 15:12:10 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Cc: linux-spi@vger.kernel.org, Mark Brown , Icenowy Zheng , Mark Rutland , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, devicetree@vger.kernel.org Subject: [PATCH v3 3/3] dt-bindings: spi: sunxi: Document new compatible strings Date: Thu, 16 Jan 2020 23:11:48 +0000 Message-Id: <20200116231148.1490-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20200116231148.1490-1-andre.przywara@arm.com> References: <20200116231148.1490-1-andre.przywara@arm.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The Allwinner H6 SPI controller has advanced features over the H3 version, but remains compatible with it. Document the usual "specific", "fallback" compatible string pair. Also add the R40 version while at it. Signed-off-by: Andre Przywara --- .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index f36c46d236d7..c8ccbc2fd1e3 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -18,9 +18,14 @@ properties: "#size-cells": true compatible: - enum: - - allwinner,sun6i-a31-spi - - allwinner,sun8i-h3-spi + oneOf: + - const: allwinner,sun6i-a31-spi + - const: allwinner,sun8i-h3-spi + - items: + - enum: + - allwinner,sun8i-r40-spi + - allwinner,sun50i-h6-spi + - const: allwinner,sun8i-h3-spi reg: maxItems: 1