From patchwork Sat Jan 18 17:26:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11340169 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1AB95109A for ; Sat, 18 Jan 2020 17:26:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EC4352469A for ; Sat, 18 Jan 2020 17:26:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gYDJjvdJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726846AbgARR00 (ORCPT ); Sat, 18 Jan 2020 12:26:26 -0500 Received: from mail-yb1-f196.google.com ([209.85.219.196]:36258 "EHLO mail-yb1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726460AbgARR0Z (ORCPT ); Sat, 18 Jan 2020 12:26:25 -0500 Received: by mail-yb1-f196.google.com with SMTP id w9so7141396ybs.3; Sat, 18 Jan 2020 09:26:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=mYutcDqqXCVJkllEBh65f1oEzPxP2d/7QBN12EzRdLI=; b=gYDJjvdJYrOL6JKiimJBL3fKckUQQDmkj3e6BpkNgkdg+sTxqu5aOwQoza7msdFR5w yYPkx2VBuCWWYMubyQMiZMMu7LSUcjYD2V+yOe0wqzLSJa9VakYrUhKQAMOEcyAxS/Ta hkfs/pu6nQcPMalkI0sX70Z4SSiTdJ/r5mIPowq8TXvUhZug73CNrqi6g94SPWH+2uWt iJxGif/y1Be7XPGWc4PfU+4R8y4tkHspLH1dX6XTe5qaSyNur8Zpjhma+fCkA3euGn0a QaZFGFzW3PbzCK8dGgMnBIr4gs+sneDa9CV47kEijHiFKYCQOauyljUdulwfwX2GRZPa C2Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=mYutcDqqXCVJkllEBh65f1oEzPxP2d/7QBN12EzRdLI=; b=g9Xgi2TVjQprIWD/yaFnRBva5c+hfTj3/yX0gq3epupqiHtM05yLYcSUTACQ+2TFgF ScO/Z7ZUBgxdAYuEA9SP7iVGstt0H/ejAhBZ1l3XwML9r/ItINvjuPXPSgMJZlmEGttH 4UFB0AbA+FnfXV4IltViYHIJkbQyeBaooQSf5Afau2j6U9+YhQ5TjO+1hhSwFrLiNnF3 atpAcq08z78typte2qGdcud/60ZxA423W7KXUIhK8Oml/7K0Hg+CHV7bC/p7vuxCcFcG b6oJYRspLSZR0ZA6F1EVMVSduT1mj50B1ZKq2tTMsj6vRITDoXrhkM1FXO1h2mbr6S86 S9dw== X-Gm-Message-State: APjAAAW58MoHitTa6O68r0/n8WGmapemzM9KdIR3H/770BjJGobKq7EB zVWF1RPPnkpIvSosUTNdn87YTV2X X-Google-Smtp-Source: APXvYqxco9kMfPRYXynoJ6ZDFZy7d2/TVXiDf0c+DkfwQalvdETa6Qdmcn7YQdIWNLxoxrjA4Thq9w== X-Received: by 2002:a25:1841:: with SMTP id 62mr36297649yby.405.1579368384383; Sat, 18 Jan 2020 09:26:24 -0800 (PST) Received: from localhost ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id b192sm13252447ywe.2.2020.01.18.09.26.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Jan 2020 09:26:24 -0800 (PST) From: Guenter Roeck To: linux-hwmon@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Clemens Ladisch , Jean Delvare , Darren Salt , Bernhard Gebetsberger , Ken Moffat , =?utf-8?q?Ondrej_=C4=8Cerman?= , Holger Kiehl , Sebastian Reichel , Brad Campbell , Guenter Roeck Subject: [PATCH v2 1/5] hwmon: (k10temp) Use bitops Date: Sat, 18 Jan 2020 09:26:11 -0800 Message-Id: <20200118172615.26329-2-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200118172615.26329-1-linux@roeck-us.net> References: <20200118172615.26329-1-linux@roeck-us.net> Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Using bitops makes bit masks and shifts easier to read. Tested-by: Bernhard Gebetsberger Tested-by: Darren Salt Signed-off-by: Guenter Roeck --- v2: Added Tested-by: tags drivers/hwmon/k10temp.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index 5c1dddde193c..8807d7da68db 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -5,6 +5,7 @@ * Copyright (c) 2009 Clemens Ladisch */ +#include #include #include #include @@ -31,22 +32,22 @@ static DEFINE_MUTEX(nb_smu_ind_mutex); #endif /* CPUID function 0x80000001, ebx */ -#define CPUID_PKGTYPE_MASK 0xf0000000 +#define CPUID_PKGTYPE_MASK GENMASK(31, 28) #define CPUID_PKGTYPE_F 0x00000000 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 /* DRAM controller (PCI function 2) */ #define REG_DCT0_CONFIG_HIGH 0x094 -#define DDR3_MODE 0x00000100 +#define DDR3_MODE BIT(8) /* miscellaneous (PCI function 3) */ #define REG_HARDWARE_THERMAL_CONTROL 0x64 -#define HTC_ENABLE 0x00000001 +#define HTC_ENABLE BIT(0) #define REG_REPORTED_TEMPERATURE 0xa4 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 -#define NB_CAP_HTC 0x00000400 +#define NB_CAP_HTC BIT(10) /* * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL @@ -60,6 +61,9 @@ static DEFINE_MUTEX(nb_smu_ind_mutex); /* F17h M01h Access througn SMN */ #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800 +#define CUR_TEMP_SHIFT 21 +#define CUR_TEMP_RANGE_SEL_MASK BIT(19) + struct k10temp_data { struct pci_dev *pdev; void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); @@ -129,7 +133,7 @@ static unsigned int get_raw_temp(struct k10temp_data *data) u32 regval; data->read_tempreg(data->pdev, ®val); - temp = (regval >> 21) * 125; + temp = (regval >> CUR_TEMP_SHIFT) * 125; if (regval & data->temp_adjust_mask) temp -= 49000; return temp; @@ -312,7 +316,7 @@ static int k10temp_probe(struct pci_dev *pdev, data->read_htcreg = read_htcreg_nb_f15; data->read_tempreg = read_tempreg_nb_f15; } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { - data->temp_adjust_mask = 0x80000; + data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK; data->read_tempreg = read_tempreg_nb_f17; data->show_tdie = true; } else { From patchwork Sat Jan 18 17:26:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11340171 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D765B14B4 for ; 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Sat, 18 Jan 2020 09:26:34 -0800 (PST) Received: from localhost ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id 71sm12857041ywd.59.2020.01.18.09.26.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Jan 2020 09:26:34 -0800 (PST) From: Guenter Roeck To: linux-hwmon@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Clemens Ladisch , Jean Delvare , Darren Salt , Bernhard Gebetsberger , Ken Moffat , =?utf-8?q?Ondrej_=C4=8Cerman?= , Holger Kiehl , Sebastian Reichel , Brad Campbell , Guenter Roeck Subject: [PATCH v2 2/5] hmon: (k10temp) Convert to use devm_hwmon_device_register_with_info Date: Sat, 18 Jan 2020 09:26:12 -0800 Message-Id: <20200118172615.26329-3-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200118172615.26329-1-linux@roeck-us.net> References: <20200118172615.26329-1-linux@roeck-us.net> Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Convert driver to use devm_hwmon_device_register_with_info to simplify the code and to reduce its size. Old size (x86_64): text data bss dec hex filename 8247 4488 64 12799 31ff drivers/hwmon/k10temp.o New size: text data bss dec hex filename 6778 2792 64 9634 25a2 drivers/hwmon/k10temp.o Tested-by: Bernhard Gebetsberger Tested-by: Darren Salt Signed-off-by: Guenter Roeck --- v2: Added Tested-by: tags drivers/hwmon/k10temp.c | 213 +++++++++++++++++++++------------------- 1 file changed, 112 insertions(+), 101 deletions(-) diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index 8807d7da68db..c45f6498a59b 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -1,14 +1,15 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring + * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h + * processor hardware monitoring * * Copyright (c) 2009 Clemens Ladisch + * Copyright (c) 2020 Guenter Roeck */ #include #include #include -#include #include #include #include @@ -127,10 +128,10 @@ static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval) F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval); } -static unsigned int get_raw_temp(struct k10temp_data *data) +static long get_raw_temp(struct k10temp_data *data) { - unsigned int temp; u32 regval; + long temp; data->read_tempreg(data->pdev, ®val); temp = (regval >> CUR_TEMP_SHIFT) * 125; @@ -139,118 +140,108 @@ static unsigned int get_raw_temp(struct k10temp_data *data) return temp; } -static ssize_t temp1_input_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct k10temp_data *data = dev_get_drvdata(dev); - unsigned int temp = get_raw_temp(data); - - if (temp > data->temp_offset) - temp -= data->temp_offset; - else - temp = 0; - - return sprintf(buf, "%u\n", temp); -} - -static ssize_t temp2_input_show(struct device *dev, - struct device_attribute *devattr, char *buf) -{ - struct k10temp_data *data = dev_get_drvdata(dev); - unsigned int temp = get_raw_temp(data); - - return sprintf(buf, "%u\n", temp); -} - -static ssize_t temp_label_show(struct device *dev, - struct device_attribute *devattr, char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - - return sprintf(buf, "%s\n", attr->index ? "Tctl" : "Tdie"); -} +const char *k10temp_temp_label[] = { + "Tdie", + "Tctl", +}; -static ssize_t temp1_max_show(struct device *dev, - struct device_attribute *attr, char *buf) +static int k10temp_read_labels(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) { - return sprintf(buf, "%d\n", 70 * 1000); + *str = k10temp_temp_label[channel]; + return 0; } -static ssize_t temp_crit_show(struct device *dev, - struct device_attribute *devattr, char *buf) +static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) { - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct k10temp_data *data = dev_get_drvdata(dev); - int show_hyst = attr->index; u32 regval; - int value; - data->read_htcreg(data->pdev, ®val); - value = ((regval >> 16) & 0x7f) * 500 + 52000; - if (show_hyst) - value -= ((regval >> 24) & 0xf) * 500; - return sprintf(buf, "%d\n", value); + switch (attr) { + case hwmon_temp_input: + switch (channel) { + case 0: /* Tdie */ + *val = get_raw_temp(data) - data->temp_offset; + if (*val < 0) + *val = 0; + break; + case 1: /* Tctl */ + *val = get_raw_temp(data); + if (*val < 0) + *val = 0; + break; + default: + return -EOPNOTSUPP; + } + break; + case hwmon_temp_max: + *val = 70 * 1000; + break; + case hwmon_temp_crit: + data->read_htcreg(data->pdev, ®val); + *val = ((regval >> 16) & 0x7f) * 500 + 52000; + break; + case hwmon_temp_crit_hyst: + data->read_htcreg(data->pdev, ®val); + *val = (((regval >> 16) & 0x7f) + - ((regval >> 24) & 0xf)) * 500 + 52000; + break; + default: + return -EOPNOTSUPP; + } + return 0; } -static DEVICE_ATTR_RO(temp1_input); -static DEVICE_ATTR_RO(temp1_max); -static SENSOR_DEVICE_ATTR_RO(temp1_crit, temp_crit, 0); -static SENSOR_DEVICE_ATTR_RO(temp1_crit_hyst, temp_crit, 1); - -static SENSOR_DEVICE_ATTR_RO(temp1_label, temp_label, 0); -static DEVICE_ATTR_RO(temp2_input); -static SENSOR_DEVICE_ATTR_RO(temp2_label, temp_label, 1); - -static umode_t k10temp_is_visible(struct kobject *kobj, - struct attribute *attr, int index) +static umode_t k10temp_is_visible(const void *_data, + enum hwmon_sensor_types type, + u32 attr, int channel) { - struct device *dev = container_of(kobj, struct device, kobj); - struct k10temp_data *data = dev_get_drvdata(dev); + const struct k10temp_data *data = _data; struct pci_dev *pdev = data->pdev; u32 reg; - switch (index) { - case 0 ... 1: /* temp1_input, temp1_max */ - default: - break; - case 2 ... 3: /* temp1_crit, temp1_crit_hyst */ - if (!data->read_htcreg) - return 0; - - pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES, - ®); - if (!(reg & NB_CAP_HTC)) - return 0; - - data->read_htcreg(data->pdev, ®); - if (!(reg & HTC_ENABLE)) - return 0; - break; - case 4 ... 6: /* temp1_label, temp2_input, temp2_label */ - if (!data->show_tdie) + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + if (channel && !data->show_tdie) + return 0; + break; + case hwmon_temp_max: + if (channel) + return 0; + break; + case hwmon_temp_crit: + case hwmon_temp_crit_hyst: + if (channel || !data->read_htcreg) + return 0; + + pci_read_config_dword(pdev, + REG_NORTHBRIDGE_CAPABILITIES, + ®); + if (!(reg & NB_CAP_HTC)) + return 0; + + data->read_htcreg(data->pdev, ®); + if (!(reg & HTC_ENABLE)) + return 0; + break; + case hwmon_temp_label: + if (!data->show_tdie) + return 0; + break; + default: return 0; + } break; + default: + return 0; } - return attr->mode; + return 0444; } -static struct attribute *k10temp_attrs[] = { - &dev_attr_temp1_input.attr, - &dev_attr_temp1_max.attr, - &sensor_dev_attr_temp1_crit.dev_attr.attr, - &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, - &sensor_dev_attr_temp1_label.dev_attr.attr, - &dev_attr_temp2_input.attr, - &sensor_dev_attr_temp2_label.dev_attr.attr, - NULL -}; - -static const struct attribute_group k10temp_group = { - .attrs = k10temp_attrs, - .is_visible = k10temp_is_visible, -}; -__ATTRIBUTE_GROUPS(k10temp); - static bool has_erratum_319(struct pci_dev *pdev) { u32 pkg_type, reg_dram_cfg; @@ -285,8 +276,27 @@ static bool has_erratum_319(struct pci_dev *pdev) (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); } -static int k10temp_probe(struct pci_dev *pdev, - const struct pci_device_id *id) +static const struct hwmon_channel_info *k10temp_info[] = { + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_MAX | + HWMON_T_CRIT | HWMON_T_CRIT_HYST | + HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL), + NULL +}; + +static const struct hwmon_ops k10temp_hwmon_ops = { + .is_visible = k10temp_is_visible, + .read = k10temp_read, + .read_string = k10temp_read_labels, +}; + +static const struct hwmon_chip_info k10temp_chip_info = { + .ops = &k10temp_hwmon_ops, + .info = k10temp_info, +}; + +static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) { int unreliable = has_erratum_319(pdev); struct device *dev = &pdev->dev; @@ -334,8 +344,9 @@ static int k10temp_probe(struct pci_dev *pdev, } } - hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data, - k10temp_groups); + hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data, + &k10temp_chip_info, + NULL); return PTR_ERR_OR_ZERO(hwmon_dev); } From patchwork Sat Jan 18 17:26:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11340175 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA191184C for ; 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Sat, 18 Jan 2020 09:26:36 -0800 (PST) Received: from localhost ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id l200sm13458445ywl.106.2020.01.18.09.26.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Jan 2020 09:26:36 -0800 (PST) From: Guenter Roeck To: linux-hwmon@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Clemens Ladisch , Jean Delvare , Darren Salt , Bernhard Gebetsberger , Ken Moffat , =?utf-8?q?Ondrej_=C4=8Cerman?= , Holger Kiehl , Sebastian Reichel , Brad Campbell , Guenter Roeck Subject: [PATCH v2 3/5] hwmon: (k10temp) Report temperatures per CPU die Date: Sat, 18 Jan 2020 09:26:13 -0800 Message-Id: <20200118172615.26329-4-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200118172615.26329-1-linux@roeck-us.net> References: <20200118172615.26329-1-linux@roeck-us.net> Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Zen2 reports reporting temperatures per CPU die (called Core Complex Dies, or CCD, by AMD). Add support for it to the k10temp driver. Tested-by: Bernhard Gebetsberger Tested-by: Darren Salt Signed-off-by: Guenter Roeck --- v2: Added Tested-by: tags drivers/hwmon/k10temp.c | 79 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index c45f6498a59b..944ba8008bc4 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -5,6 +5,12 @@ * * Copyright (c) 2009 Clemens Ladisch * Copyright (c) 2020 Guenter Roeck + * + * Implementation notes: + * - CCD1 and CCD2 register address information as well as the calculation to + * convert raw register values is from https://github.com/ocerman/zenpower. + * The information is not confirmed from chip datasheets, but experiments + * suggest that it provides reasonable temperature values. */ #include @@ -61,6 +67,8 @@ static DEFINE_MUTEX(nb_smu_ind_mutex); /* F17h M01h Access througn SMN */ #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800 +#define F17H_M70H_CCD1_TEMP 0x00059954 +#define F17H_M70H_CCD2_TEMP 0x00059958 #define CUR_TEMP_SHIFT 21 #define CUR_TEMP_RANGE_SEL_MASK BIT(19) @@ -72,6 +80,8 @@ struct k10temp_data { int temp_offset; u32 temp_adjust_mask; bool show_tdie; + bool show_tccd1; + bool show_tccd2; }; struct tctl_offset { @@ -143,6 +153,8 @@ static long get_raw_temp(struct k10temp_data *data) const char *k10temp_temp_label[] = { "Tdie", "Tctl", + "Tccd1", + "Tccd2", }; static int k10temp_read_labels(struct device *dev, @@ -172,6 +184,16 @@ static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, if (*val < 0) *val = 0; break; + case 2: /* Tccd1 */ + amd_smn_read(amd_pci_dev_to_node_id(data->pdev), + F17H_M70H_CCD1_TEMP, ®val); + *val = (regval & 0xfff) * 125 - 305000; + break; + case 3: /* Tccd2 */ + amd_smn_read(amd_pci_dev_to_node_id(data->pdev), + F17H_M70H_CCD2_TEMP, ®val); + *val = (regval & 0xfff) * 125 - 305000; + break; default: return -EOPNOTSUPP; } @@ -206,8 +228,24 @@ static umode_t k10temp_is_visible(const void *_data, case hwmon_temp: switch (attr) { case hwmon_temp_input: - if (channel && !data->show_tdie) + switch (channel) { + case 0: /* Tdie, or Tctl if we don't show it */ + break; + case 1: /* Tctl */ + if (!data->show_tdie) + return 0; + break; + case 2: /* Tccd1 */ + if (!data->show_tccd1) + return 0; + break; + case 3: /* Tccd2 */ + if (!data->show_tccd2) + return 0; + break; + default: return 0; + } break; case hwmon_temp_max: if (channel) @@ -229,8 +267,24 @@ static umode_t k10temp_is_visible(const void *_data, return 0; break; case hwmon_temp_label: + /* No labels if we don't show the die temperature */ if (!data->show_tdie) return 0; + switch (channel) { + case 0: /* Tdie */ + case 1: /* Tctl */ + break; + case 2: /* Tccd1 */ + if (!data->show_tccd1) + return 0; + break; + case 3: /* Tccd2 */ + if (!data->show_tccd2) + return 0; + break; + default: + return 0; + } break; default: return 0; @@ -281,6 +335,8 @@ static const struct hwmon_channel_info *k10temp_info[] = { HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL), NULL }; @@ -326,9 +382,30 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) data->read_htcreg = read_htcreg_nb_f15; data->read_tempreg = read_tempreg_nb_f15; } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { + u32 regval; + data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK; data->read_tempreg = read_tempreg_nb_f17; data->show_tdie = true; + + switch (boot_cpu_data.x86_model) { + case 0x1: /* Zen */ + case 0x8: /* Zen+ */ + case 0x11: /* Zen APU */ + case 0x18: /* Zen+ APU */ + break; + case 0x71: /* Zen2 */ + amd_smn_read(amd_pci_dev_to_node_id(pdev), + F17H_M70H_CCD1_TEMP, ®val); + if (regval & 0xfff) + data->show_tccd1 = true; + + amd_smn_read(amd_pci_dev_to_node_id(pdev), + F17H_M70H_CCD2_TEMP, ®val); + if (regval & 0xfff) + data->show_tccd2 = true; + break; + } } else { data->read_htcreg = read_htcreg_pci; data->read_tempreg = read_tempreg_pci; From patchwork Sat Jan 18 17:26:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11340173 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67C6014B4 for ; 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Sat, 18 Jan 2020 09:26:38 -0800 (PST) Received: from localhost ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id d13sm13272444ywj.91.2020.01.18.09.26.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Jan 2020 09:26:38 -0800 (PST) From: Guenter Roeck To: linux-hwmon@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Clemens Ladisch , Jean Delvare , Darren Salt , Bernhard Gebetsberger , Ken Moffat , =?utf-8?q?Ondrej_=C4=8Cerman?= , Holger Kiehl , Sebastian Reichel , Brad Campbell , Guenter Roeck Subject: [PATCH v2 4/5] hwmon: (k10temp) Show core and SoC current and voltages on Ryzen CPUs Date: Sat, 18 Jan 2020 09:26:14 -0800 Message-Id: <20200118172615.26329-5-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200118172615.26329-1-linux@roeck-us.net> References: <20200118172615.26329-1-linux@roeck-us.net> Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Ryzen CPUs report core and SoC voltages and currents. Add support for it to the k10temp driver. For the time being, only report voltages and currents for Ryzen CPUs. Threadripper and EPYC appear to use a different mechanism. Tested-by: Bernhard Gebetsberger Tested-by: Darren Salt Signed-off-by: Guenter Roeck --- v2: Added Tested-by: tags. Don't try to report voltage and current information on Threadripper and EPYC CPUs. drivers/hwmon/k10temp.c | 126 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 123 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index 944ba8008bc4..a4313b662a3a 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -11,6 +11,13 @@ * convert raw register values is from https://github.com/ocerman/zenpower. * The information is not confirmed from chip datasheets, but experiments * suggest that it provides reasonable temperature values. + * - Register addresses to read chip voltage and current is also from + * https://github.com/ocerman/zenpower, and not confirmed from chip + * datasheets. Experiments suggest that reported current and voltage + * information is reasonable. + * - It is unknown if the mechanism to read CCD1/CCD2 temperature as well as + * current and voltage information works on higher-end Ryzen CPUs, or if + * additional information is available on those CPUs. */ #include @@ -70,6 +77,10 @@ static DEFINE_MUTEX(nb_smu_ind_mutex); #define F17H_M70H_CCD1_TEMP 0x00059954 #define F17H_M70H_CCD2_TEMP 0x00059958 +#define F17H_M01H_SVI 0x0005A000 +#define F17H_M01H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0xc) +#define F17H_M01H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0x10) + #define CUR_TEMP_SHIFT 21 #define CUR_TEMP_RANGE_SEL_MASK BIT(19) @@ -82,6 +93,9 @@ struct k10temp_data { bool show_tdie; bool show_tccd1; bool show_tccd2; + u32 svi_addr[2]; + bool show_current; + int cfactor[2]; }; struct tctl_offset { @@ -99,6 +113,16 @@ static const struct tctl_offset tctl_offset_table[] = { { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ }; +static bool is_threadripper(void) +{ + return strstr(boot_cpu_data.x86_model_id, "Threadripper"); +} + +static bool is_epyc(void) +{ + return strstr(boot_cpu_data.x86_model_id, "EPYC"); +} + static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) { pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); @@ -157,16 +181,76 @@ const char *k10temp_temp_label[] = { "Tccd2", }; +const char *k10temp_in_label[] = { + "Vcore", + "Vsoc", +}; + +const char *k10temp_curr_label[] = { + "Icore", + "Isoc", +}; + static int k10temp_read_labels(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, const char **str) { - *str = k10temp_temp_label[channel]; + switch (type) { + case hwmon_temp: + *str = k10temp_temp_label[channel]; + break; + case hwmon_in: + *str = k10temp_in_label[channel]; + break; + case hwmon_curr: + *str = k10temp_curr_label[channel]; + break; + default: + return -EOPNOTSUPP; + } return 0; } -static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, - u32 attr, int channel, long *val) +static int k10temp_read_curr(struct device *dev, u32 attr, int channel, + long *val) +{ + struct k10temp_data *data = dev_get_drvdata(dev); + u32 regval; + + switch (attr) { + case hwmon_curr_input: + amd_smn_read(amd_pci_dev_to_node_id(data->pdev), + data->svi_addr[channel], ®val); + *val = DIV_ROUND_CLOSEST(data->cfactor[channel] * + (regval & 0xff), + 1000); + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +static int k10temp_read_in(struct device *dev, u32 attr, int channel, long *val) +{ + struct k10temp_data *data = dev_get_drvdata(dev); + u32 regval; + + switch (attr) { + case hwmon_in_input: + amd_smn_read(amd_pci_dev_to_node_id(data->pdev), + data->svi_addr[channel], ®val); + regval = (regval >> 16) & 0xff; + *val = DIV_ROUND_CLOSEST(155000 - regval * 625, 100); + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +static int k10temp_read_temp(struct device *dev, u32 attr, int channel, + long *val) { struct k10temp_data *data = dev_get_drvdata(dev); u32 regval; @@ -216,6 +300,21 @@ static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, return 0; } +static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + switch (type) { + case hwmon_temp: + return k10temp_read_temp(dev, attr, channel, val); + case hwmon_in: + return k10temp_read_in(dev, attr, channel, val); + case hwmon_curr: + return k10temp_read_curr(dev, attr, channel, val); + default: + return -EOPNOTSUPP; + } +} + static umode_t k10temp_is_visible(const void *_data, enum hwmon_sensor_types type, u32 attr, int channel) @@ -290,6 +389,11 @@ static umode_t k10temp_is_visible(const void *_data, return 0; } break; + case hwmon_in: + case hwmon_curr: + if (!data->show_current) + return 0; + break; default: return 0; } @@ -338,6 +442,12 @@ static const struct hwmon_channel_info *k10temp_info[] = { HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL), + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL), + HWMON_CHANNEL_INFO(curr, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL), NULL }; @@ -393,8 +503,18 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) case 0x8: /* Zen+ */ case 0x11: /* Zen APU */ case 0x18: /* Zen+ APU */ + data->show_current = !is_threadripper() && !is_epyc(); + data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0; + data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1; + data->cfactor[0] = 1039211; /* core */ + data->cfactor[1] = 360772; /* SoC */ break; case 0x71: /* Zen2 */ + data->show_current = !is_threadripper() && !is_epyc(); + data->cfactor[0] = 658823; /* core */ + data->cfactor[1] = 294300; /* SoC */ + data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE1; + data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE0; amd_smn_read(amd_pci_dev_to_node_id(pdev), F17H_M70H_CCD1_TEMP, ®val); if (regval & 0xfff) From patchwork Sat Jan 18 17:26:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11340177 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4393A13BD for ; Sat, 18 Jan 2020 17:26:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 21A3B2469A for ; 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Sat, 18 Jan 2020 09:26:45 -0800 (PST) From: Guenter Roeck To: linux-hwmon@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Clemens Ladisch , Jean Delvare , Darren Salt , Bernhard Gebetsberger , Ken Moffat , =?utf-8?q?Ondrej_=C4=8Cerman?= , Holger Kiehl , Sebastian Reichel , Brad Campbell , Guenter Roeck Subject: [PATCH v2 5/5] hwmon: (k10temp) Don't show temperature limits on Ryzen (Zen) CPUs Date: Sat, 18 Jan 2020 09:26:15 -0800 Message-Id: <20200118172615.26329-6-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200118172615.26329-1-linux@roeck-us.net> References: <20200118172615.26329-1-linux@roeck-us.net> Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org The maximum Tdie or Tctl is not published for Ryzen CPUs. What is known, however, is that the traditional value of 70 degrees C is no longer correct. Displaying it is meaningless, confusing, and wrong. Stop doing it. Signed-off-by: Guenter Roeck --- v2: Added patch. drivers/hwmon/k10temp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index a4313b662a3a..cdfebe435003 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -347,7 +347,7 @@ static umode_t k10temp_is_visible(const void *_data, } break; case hwmon_temp_max: - if (channel) + if (channel || data->show_tdie) return 0; break; case hwmon_temp_crit: