From patchwork Tue Jan 21 14:31:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wambui Karuga X-Patchwork-Id: 11344299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9BAE8109A for ; Tue, 21 Jan 2020 17:20:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 797CE24655 for ; Tue, 21 Jan 2020 17:20:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="td1MpXYY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 797CE24655 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C86C6EDEF; Tue, 21 Jan 2020 17:20:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by gabe.freedesktop.org (Postfix) with ESMTPS id C75A96ED20; Tue, 21 Jan 2020 14:32:06 +0000 (UTC) Received: by mail-wr1-x441.google.com with SMTP id d16so3419827wre.10; Tue, 21 Jan 2020 06:32:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=BKzjh1mWJS7uNNwFhcl5hs0Za+t5SKpiQwE1FgRQkiQ=; b=td1MpXYYP+u4O83G5ICBFAQlKeMrKixBYsdWGrUVak43GHHbVTyjeSHz9zWTSwJykf cNz+R4PIR0ohFjDXpF1lVBGAmsAfJV6/F0AyQjAW5Vk2P2IIrH2e23X6uicKNa2HkhOP OBed30ErQP0aLGzzsG8YCy490oOcKOueQVgHgzgF+nQIyGfPQGJJyWqbB0jOZCpIDj5u sOlkWVTpkBNAwUx1k+L1G9anzGKz0lIWwRGz7ZZEqiSHQmXiJsXhX/p5jcWrGCEIUzph fk+ugL3syIKf4HUcwhRN1deguvagRbm/AWew9L1HthgO5vKtzp+JwG4voSg6LVsdWXSZ 3U3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=BKzjh1mWJS7uNNwFhcl5hs0Za+t5SKpiQwE1FgRQkiQ=; b=q3ysaZh2RQi0B5ASz7xIx8P+z4AB0n91CmmXZbmfxcjLygKRJb87H1mLoTVsiJ8aZs CoSRjqbiKcqJXygbDMkjk2ZirFaCU/9FlK/804LXNGswfN0b6mG/cjqe2u4GhxLRXhWe iaudNPc0kUFnv0fRPj0AvBaAAli+NTyC+pTSod26jI+nPyFbjy9g92I6XGhL4GUjOZwX KfVK7iA8Cl6QImW5IL/xLAd3idmHrJXb/43xDJjEJeFjfraPu/CNDAl8o1rD5IEDs7oj QqvTjjXI4vZlkWPWcK6vxKwEVdMLzuHSf6utm4iKSxPxazqj8n/nS253uFW1PyIQ+OAI JrBQ== X-Gm-Message-State: APjAAAWMoLospj6LySwqA5gnWi23p3ijBZv3cGrj/lR6pNFctGGvvx5c z/BqcPr7Zq1nIF+gmvf/2a8= X-Google-Smtp-Source: APXvYqy/C0mpc16YxEaeK4DdXQgEaQwtt/G6BnYWePDQWWWTONNTqzUGxWBWd/Q9Xcy4KDvhpXEg6g== X-Received: by 2002:a5d:4ed0:: with SMTP id s16mr5658252wrv.144.1579617125395; Tue, 21 Jan 2020 06:32:05 -0800 (PST) Received: from localhost.localdomain ([197.254.95.38]) by smtp.googlemail.com with ESMTPSA id g2sm52781284wrw.76.2020.01.21.06.32.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2020 06:32:04 -0800 (PST) From: Wambui Karuga To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, airlied@linux.ie, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Tue, 21 Jan 2020 17:31:50 +0300 Message-Id: <20200121143155.20856-2-wambui.karugax@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200121143155.20856-1-wambui.karugax@gmail.com> References: <20200121143155.20856-1-wambui.karugax@gmail.com> X-Mailman-Approved-At: Tue, 21 Jan 2020 17:20:38 +0000 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/dsi: conversion to struct drm_device log macros X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This converts the more straightforward instances of the printk based logging macros with the struct drm_device based logging macros. This transformation was achieved using coccinelle and the following script for matching an existing struct drm_i915_private device: @rule1@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @rule2@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } New checkpatch warnings were fixed manually. Signed-off-by: Wambui Karuga --- drivers/gpu/drm/i915/display/icl_dsi.c | 82 ++++++++++++++++---------- 1 file changed, 51 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index a7457303c62e..1186a5df057e 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -55,7 +55,7 @@ static void wait_for_header_credits(struct drm_i915_private *dev_priv, { if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= MAX_HEADER_CREDIT, 100)) - DRM_ERROR("DSI header credits not released\n"); + drm_err(&dev_priv->drm, "DSI header credits not released\n"); } static void wait_for_payload_credits(struct drm_i915_private *dev_priv, @@ -63,7 +63,7 @@ static void wait_for_payload_credits(struct drm_i915_private *dev_priv, { if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= MAX_PLOAD_CREDIT, 100)) - DRM_ERROR("DSI payload credits not released\n"); + drm_err(&dev_priv->drm, "DSI payload credits not released\n"); } static enum transcoder dsi_port_to_transcoder(enum port port) @@ -97,7 +97,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) dsi->channel = 0; ret = mipi_dsi_dcs_nop(dsi); if (ret < 0) - DRM_ERROR("error sending DCS NOP command\n"); + drm_err(&dev_priv->drm, + "error sending DCS NOP command\n"); } /* wait for header credits to be released */ @@ -111,7 +112,7 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) dsi_trans = dsi_port_to_transcoder(port); if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) & LPTX_IN_PROGRESS), 20)) - DRM_ERROR("LPTX bit not cleared\n"); + drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); } } @@ -129,7 +130,8 @@ static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, free_credits = payload_credits_available(dev_priv, dsi_trans); if (free_credits < 1) { - DRM_ERROR("Payload credit not available\n"); + drm_err(&dev_priv->drm, + "Payload credit not available\n"); return false; } @@ -154,7 +156,8 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host, /* check if header credit available */ free_credits = header_credits_available(dev_priv, dsi_trans); if (free_credits < 1) { - DRM_ERROR("send pkt header failed, not enough hdr credits\n"); + drm_err(&dev_priv->drm, + "send pkt header failed, not enough hdr credits\n"); return -1; } @@ -286,7 +289,8 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) - DRM_ERROR("DL buffer depth exceed max value\n"); + drm_err(&dev_priv->drm, + "DL buffer depth exceed max value\n"); dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); @@ -500,7 +504,8 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 500)) - DRM_ERROR("DDI port:%c buffer idle\n", port_name(port)); + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", + port_name(port)); } } @@ -780,7 +785,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, dsi_trans = dsi_port_to_transcoder(port); if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) & LINK_READY), 2500)) - DRM_ERROR("DSI link not ready\n"); + drm_err(&dev_priv->drm, "DSI link not ready\n"); } } @@ -836,11 +841,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, /* minimum hactive as per bspec: 256 pixels */ if (adjusted_mode->crtc_hdisplay < 256) - DRM_ERROR("hactive is less then 256 pixels\n"); + drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); /* if RGB666 format, then hactive must be multiple of 4 pixels */ if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) - DRM_ERROR("hactive pixels are not multiple of 4\n"); + drm_err(&dev_priv->drm, + "hactive pixels are not multiple of 4\n"); /* program TRANS_HTOTAL register */ for_each_dsi_port(port, intel_dsi->ports) { @@ -855,11 +861,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { /* BSPEC: hsync size should be atleast 16 pixels */ if (hsync_size < 16) - DRM_ERROR("hsync size < 16 pixels\n"); + drm_err(&dev_priv->drm, + "hsync size < 16 pixels\n"); } if (hback_porch < 16) - DRM_ERROR("hback porch < 16 pixels\n"); + drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); if (intel_dsi->dual_link) { hsync_start /= 2; @@ -887,10 +894,10 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, } if (vsync_end < vsync_start || vsync_end > vtotal) - DRM_ERROR("Invalid vsync_end value\n"); + drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); if (vsync_start < vactive) - DRM_ERROR("vsync_start less than vactive\n"); + drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); /* program TRANS_VSYNC register */ for_each_dsi_port(port, intel_dsi->ports) { @@ -937,7 +944,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) /* wait for transcoder to be enabled */ if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), I965_PIPECONF_ACTIVE, 10)) - DRM_ERROR("DSI transcoder not enabled\n"); + drm_err(&dev_priv->drm, + "DSI transcoder not enabled\n"); } } @@ -1048,7 +1056,8 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) dsi = intel_dsi->dsi_hosts[port]->device; ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); if (ret < 0) - DRM_ERROR("error setting max return pkt size%d\n", tmp); + drm_err(&dev_priv->drm, + "error setting max return pkt size%d\n", tmp); } /* panel power on related mipi dsi vbt sequences */ @@ -1120,7 +1129,8 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) /* wait for transcoder to be disabled */ if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), I965_PIPECONF_ACTIVE, 50)) - DRM_ERROR("DSI trancoder not disabled\n"); + drm_err(&dev_priv->drm, + "DSI trancoder not disabled\n"); } } @@ -1155,7 +1165,7 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) & LINK_IN_ULPS), 10)) - DRM_ERROR("DSI link not in ULPS\n"); + drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); } /* disable ddi function */ @@ -1193,8 +1203,9 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 8)) - DRM_ERROR("DDI port:%c buffer not idle\n", - port_name(port)); + drm_err(&dev_priv->drm, + "DDI port:%c buffer not idle\n", + port_name(port)); } gen11_dsi_gate_clocks(encoder); } @@ -1458,7 +1469,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, *pipe = PIPE_D; break; default: - DRM_ERROR("Invalid PIPE input\n"); + drm_err(&dev_priv->drm, "Invalid PIPE input\n"); goto out; } @@ -1582,7 +1593,8 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) */ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); if (prepare_cnt > ICL_PREPARE_CNT_MAX) { - DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt); + drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", + prepare_cnt); prepare_cnt = ICL_PREPARE_CNT_MAX; } @@ -1590,28 +1602,33 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - ths_prepare_ns, tlpx_ns); if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt); + drm_dbg_kms(&dev_priv->drm, + "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; } /* trail cnt in escape clocks*/ trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); if (trail_cnt > ICL_TRAIL_CNT_MAX) { - DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt); + drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", + trail_cnt); trail_cnt = ICL_TRAIL_CNT_MAX; } /* tclk pre count in escape clocks */ tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { - DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); + drm_dbg_kms(&dev_priv->drm, + "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; } /* tclk post count in escape clocks */ tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { - DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt); + drm_dbg_kms(&dev_priv->drm, + "tclk_post_cnt out of range (%d)\n", + tclk_post_cnt); tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; } @@ -1619,14 +1636,17 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - ths_prepare_ns, tlpx_ns); if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt); + drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", + hs_zero_cnt); hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; } /* hs exit zero cnt in escape clocks */ exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt); + drm_dbg_kms(&dev_priv->drm, + "exit_zero_cnt out of range (%d)\n", + exit_zero_cnt); exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; } @@ -1737,7 +1757,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) mutex_unlock(&dev->mode_config.mutex); if (!fixed_mode) { - DRM_ERROR("DSI fixed mode info missing\n"); + drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); goto err; } @@ -1763,7 +1783,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) } if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { - DRM_DEBUG_KMS("no device found\n"); + drm_dbg_kms(&dev_priv->drm, "no device found\n"); goto err; } From patchwork Tue Jan 21 14:31:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wambui Karuga X-Patchwork-Id: 11344301 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5BDAD92A for ; Tue, 21 Jan 2020 17:20:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 39B37206A2 for ; Tue, 21 Jan 2020 17:20:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kUH73IJB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 39B37206A2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C90026EDF2; Tue, 21 Jan 2020 17:20:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by gabe.freedesktop.org (Postfix) with ESMTPS id EB7C26ED20; Tue, 21 Jan 2020 14:32:09 +0000 (UTC) Received: by mail-wr1-x435.google.com with SMTP id d16so3420057wre.10; Tue, 21 Jan 2020 06:32:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=IT//qMtbtxRD3keMQqlPTrb+eQNrrlZsz6D2ttnYJck=; b=kUH73IJBeSl+zazqNetwsi11WxkDFHvd4JLAWEFzHR88AT6QJ8iho5nPbLXGw6MxtB 2FvEO29diqUI52pS4V2yjoTg0DLeH6Oy3aFnVEU4SHq5rXViHM+3TMmnd53jDYgZ18Gr dPb0ZPq5/GriOIKzpg4XdeZ4o//9UdhrjYvWqIl8BXtqiZXkLP7mcRPtO+Ne4IQUCjGU P0EGwcYKzh3bkZaBkD4XmG+E0ET/a2tM67tznKb64FH+YhBEUFqU5oQPzQH0BAVsM9tX GVfuCKxETnX2yuLFoBCjHCrZ6FsT2tetdEpB0v2fR2SLJAxpG4dO3559InfEW3t4jm2g dClQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=IT//qMtbtxRD3keMQqlPTrb+eQNrrlZsz6D2ttnYJck=; b=AV3xtJrq1G8q40dHis8lCIObOj4kqw781CKEHgB0lO0tP97lAS9oaomQ2IddsUP+po 3wagx5oCifzH3siu/Kzpq8s+wsDAo//P7F7L1HWNptte25EtjSuY6rPP6OoiStsTU3G4 eUESsqvPi1/A/OV5my4Op7SRmwjvFSMuYeuVTueLZNnu3G8o68iXem3A+U7Rwt7qkn9X tbEiT8vBWLZ72EDQ/ApTpBsjEOq2+wMQEIMfK9pE2KxhkM8zAsdUqQ0W72i7biVbQ8do ewdM5Rg1YKjeK5BNsv7dQ4Kz++pc4pADqw9O2aR/TuiQE3Zk7bYC/JQHm15W/osvrzEO bCtA== X-Gm-Message-State: APjAAAX6IAe264JPLwd/G7guDRRkNuDiRtuLgRAzzU0eWxOFbeax4ZiO sa4WuJtNyXkThynlcFmpymOJ/WSm X-Google-Smtp-Source: APXvYqw7BIr2X5mpVimNYyuIdD/GpL3p2DVRhihOq4WkPRmBwNwYDblilSKG/2c6Ssb8zv909BtxKg== X-Received: by 2002:adf:ea88:: with SMTP id s8mr5571291wrm.293.1579617128425; Tue, 21 Jan 2020 06:32:08 -0800 (PST) Received: from localhost.localdomain ([197.254.95.38]) by smtp.googlemail.com with ESMTPSA id g2sm52781284wrw.76.2020.01.21.06.32.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2020 06:32:07 -0800 (PST) From: Wambui Karuga To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, airlied@linux.ie, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Tue, 21 Jan 2020 17:31:51 +0300 Message-Id: <20200121143155.20856-3-wambui.karugax@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200121143155.20856-1-wambui.karugax@gmail.com> References: <20200121143155.20856-1-wambui.karugax@gmail.com> X-Mailman-Approved-At: Tue, 21 Jan 2020 17:20:38 +0000 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/ddi: convert to struct drm_device log macros. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch converts various instances of the printk based logging macros into the struct drm_device based macros. This was achieved using the following coccinelle script for matching existing struct drm_i915_private devices: @rule1@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @rule2@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } Checkpatch warnings were addressed manually. Signed-off-by: Wambui Karuga --- drivers/gpu/drm/i915/display/intel_ddi.c | 98 +++++++++++++++--------- 1 file changed, 60 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 18a8186699f9..001e6e8fbd43 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1076,7 +1076,8 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, if (I915_READ(reg) & DDI_BUF_IS_IDLE) return; } - DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", + port_name(port)); } static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) @@ -1229,7 +1230,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, temp = I915_READ(DP_TP_STATUS(PORT_E)); if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { - DRM_DEBUG_KMS("FDI link training done on step %d\n", i); + drm_dbg_kms(&dev_priv->drm, + "FDI link training done on step %d\n", i); break; } @@ -1238,7 +1240,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, * Results in less fireworks from the state checker. */ if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { - DRM_ERROR("FDI link training failed!\n"); + drm_err(&dev_priv->drm, "FDI link training failed!\n"); break; } @@ -2005,7 +2007,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { - DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n"); + drm_dbg_kms(&dev_priv->drm, + "Quirk Increase DDI disabled time\n"); /* Quirk time at 100ms for reliable operation */ msleep(100); } @@ -2183,20 +2186,23 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, } if (!*pipe_mask) - DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n", - encoder->base.base.id, encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "No pipe for [ENCODER:%d:%s] found\n", + encoder->base.base.id, encoder->base.name); if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { - DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", - encoder->base.base.id, encoder->base.name, - *pipe_mask); + drm_dbg_kms(&dev_priv->drm, + "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", + encoder->base.base.id, encoder->base.name, + *pipe_mask); *pipe_mask = BIT(ffs(*pipe_mask) - 1); } if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) - DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", - encoder->base.base.id, encoder->base.name, - *pipe_mask, mst_pipe_mask); + drm_dbg_kms(&dev_priv->drm, + "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", + encoder->base.base.id, encoder->base.name, + *pipe_mask, mst_pipe_mask); else *is_dp_mst = mst_pipe_mask; @@ -2206,9 +2212,10 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | BXT_PHY_LANE_POWERDOWN_ACK | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) - DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? " - "(PHY_CTL %08x)\n", encoder->base.base.id, - encoder->base.name, tmp); + drm_err(&dev_priv->drm, + "[ENCODER:%d:%s] enabled but PHY powered down? " + "(PHY_CTL %08x)\n", encoder->base.base.id, + encoder->base.name, tmp); } intel_display_power_put(dev_priv, encoder->power_domain, wakeref); @@ -2365,7 +2372,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, /* Make sure that the requested I_boost is valid */ if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { - DRM_ERROR("Invalid I_boost value %u\n", iboost); + drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); return; } @@ -2617,7 +2624,9 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, return; if (level >= n_entries) { - DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); + drm_dbg_kms(&dev_priv->drm, + "DDI translation not found for level %d. Using %d instead.", + level, n_entries - 1); level = n_entries - 1; } @@ -2743,8 +2752,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, ddi_translations = icl_mg_phy_ddi_translations; /* The table does not have values for level 3 and level 9. */ if (level >= n_entries || level == 3 || level == 9) { - DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", - level, n_entries - 2); + drm_dbg_kms(&dev_priv->drm, + "DDI translation not found for level %d. Using %d instead.", + level, n_entries - 2); level = n_entries - 2; } @@ -3324,7 +3334,8 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder, if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) - DRM_ERROR("Timed out waiting for FEC Enable Status\n"); + drm_err(&dev_priv->drm, + "Timed out waiting for FEC Enable Status\n"); } static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, @@ -3407,7 +3418,8 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder, return; cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines; - DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline); + drm_dbg_kms(&dev_priv->drm, "DC3CO exit scanlines %d\n", + cstate->dc3co_exitline); } static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state) @@ -3856,8 +3868,9 @@ static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_ if (old_crtc_state->master_transcoder == INVALID_TRANSCODER) return; - DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n", - transcoder_name(old_crtc_state->cpu_transcoder)); + drm_dbg_kms(&dev_priv->drm, + "Disabling Transcoder Port Sync on Slave Transcoder %s\n", + transcoder_name(old_crtc_state->cpu_transcoder)); I915_WRITE(TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0); } @@ -4007,8 +4020,9 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, if (!intel_hdmi_handle_sink_scrambling(encoder, connector, crtc_state->hdmi_high_tmds_clock_ratio, crtc_state->hdmi_scrambling)) - DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", - connector->base.id, connector->name); + drm_err(&dev_priv->drm, + "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", + connector->base.id, connector->name); /* Display WA #1143: skl,kbl,cfl */ if (IS_GEN9_BC(dev_priv)) { @@ -4385,9 +4399,10 @@ void intel_ddi_get_config(struct intel_encoder *encoder, pipe_config->fec_enable = I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; - DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n", - encoder->base.base.id, encoder->base.name, - pipe_config->fec_enable); + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] Fec status: %u\n", + encoder->base.base.id, encoder->base.name, + pipe_config->fec_enable); } break; @@ -4427,8 +4442,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, * up by the BIOS, and thus we can't get the mode at module * load. */ - DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", - pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); + drm_dbg_kms(&dev_priv->drm, + "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", + pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; } @@ -4625,7 +4641,8 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); if (ret < 0) { - DRM_ERROR("Failed to read TMDS config: %d\n", ret); + drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", + ret); return 0; } @@ -4770,7 +4787,8 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) * so we use the proper lane count for our calculations. */ if (intel_ddi_a_force_4_lanes(intel_dport)) { - DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n"); + drm_dbg_kms(&dev_priv->drm, + "Forcing DDI_A_4_LANES for port A\n"); intel_dport->saved_port_bits |= DDI_A_4_LANES; max_lanes = 4; } @@ -4798,12 +4816,14 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) init_dp = true; init_lspcon = true; init_hdmi = false; - DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); + drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", + port_name(port)); } if (!init_dp && !init_hdmi) { - DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", - port_name(port)); + drm_dbg_kms(&dev_priv->drm, + "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", + port_name(port)); return; } @@ -4879,14 +4899,16 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) if (init_lspcon) { if (lspcon_init(intel_dig_port)) /* TODO: handle hdmi info frame part */ - DRM_DEBUG_KMS("LSPCON init success on port %c\n", - port_name(port)); + drm_dbg_kms(&dev_priv->drm, + "LSPCON init success on port %c\n", + port_name(port)); else /* * LSPCON init faied, but DP init was success, so * lets try to drive as DP++ port. */ - DRM_ERROR("LSPCON init failed on port %c\n", + drm_err(&dev_priv->drm, + "LSPCON init failed on port %c\n", port_name(port)); } From patchwork Tue Jan 21 14:31:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wambui Karuga X-Patchwork-Id: 11344309 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5AE9E92A for ; Tue, 21 Jan 2020 17:20:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3876D206A2 for ; Tue, 21 Jan 2020 17:20:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OzdGyL9H" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3876D206A2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E33EB6FADF; Tue, 21 Jan 2020 17:20:41 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A47A6ED2D; Tue, 21 Jan 2020 14:32:13 +0000 (UTC) Received: by mail-wr1-x441.google.com with SMTP id g17so3476872wro.2; Tue, 21 Jan 2020 06:32:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=R0xmmVCoR2GBppFOHhKKqiSMnSpBmqHLgezC2QrEWw4=; b=OzdGyL9HPpK8FtXXPl2FiWn2zGkKNMjKlynrWJmQsGvafsWsTLZUrbLM5uvey0ktjh /LCwQC5bqRuHtZRLjX6M+ukFHqbaI/B+JgasxN11+OFXjiMhFImiVif5lgKraPxVWy2f Gj8BxJ9lrqoNnZ2fCifMq8em4Glj4/R7e7TCBfug0yEUzHIO6W93AXLg9mXnBouRbHHa pXpu69q5jOtMsCZD1hfpEZDq6tXa8jR5a2Ob9Sd4QoPVR5Q/tL+ZQjPm4Ihtmp5d1eUx 31otF45yNkRynvED5gIOj9/5KbDssXtw8rzQNynnpsbgjwOIIGhX1IDBFamwbHtyZ2Vn 0ROA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=R0xmmVCoR2GBppFOHhKKqiSMnSpBmqHLgezC2QrEWw4=; b=AZ6OwqdzsCie2jFbFjOe5C/LTVTa7xXAumf4ynIGg1gk6ciTmA3HtWyF2NRuM4ATum Kt3+TL6uENR0N7g1o5Lh3yFxzRlE4voQe8Yd0H7RNOeI/KZ0+K0Y1i2yBuKUe+ZZiIqs /1KoYX8s8B0DJFK256g/D8ERjtZ3mylrffvadwWkNQAUIHrfdBXNkVV3HjkYb5OU8fze I1hSYBXnfeF7dayrzos6vwgG+jXl9d2M5Tl4OTrzBQz3SPRDQYMKYQNNGxNYIV79G/zl hjIEiYwQxr/9fUz4W3tqc3aspqQwo9HeXrWzhwDgI5i/F90Q8ldAe4cE6We7pLAl5+2o p6Uw== X-Gm-Message-State: APjAAAW1nzcMyyshJAPsIw9nl8umHq0V7tBoIRpErSoikY+Y+xOf8zmA FAPRu56qp0LEj4SaIUjU+5g= X-Google-Smtp-Source: APXvYqxfg82+HvT3B4nao7EfsBiewEOy51gnCWEpt32Vwmt0XuHPVk3t+5l65JQmfvUcGahC7COtfA== X-Received: by 2002:a5d:558d:: with SMTP id i13mr5538116wrv.364.1579617131640; Tue, 21 Jan 2020 06:32:11 -0800 (PST) Received: from localhost.localdomain ([197.254.95.38]) by smtp.googlemail.com with ESMTPSA id g2sm52781284wrw.76.2020.01.21.06.32.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2020 06:32:11 -0800 (PST) From: Wambui Karuga To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, airlied@linux.ie, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Tue, 21 Jan 2020 17:31:52 +0300 Message-Id: <20200121143155.20856-4-wambui.karugax@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200121143155.20856-1-wambui.karugax@gmail.com> References: <20200121143155.20856-1-wambui.karugax@gmail.com> X-Mailman-Approved-At: Tue, 21 Jan 2020 17:20:38 +0000 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/power: convert to struct drm_device macros in display/intel_display_power.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Converts various instances of the printk based logging macros in i915/display/intel_display_power.c to the struct drm_device based logging macros using the following coccinelle script: @rule1@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @rule2@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } Checkpatch warnings were fixed manually. Signed-off-by: Wambui Karuga --- .../drm/i915/display/intel_display_power.c | 177 ++++++++++-------- 1 file changed, 99 insertions(+), 78 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 21561acfa3ac..18d8bfdcb086 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -159,7 +159,7 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) static void intel_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name); + drm_dbg_kms(&dev_priv->drm, "enabling %s\n", power_well->desc->name); power_well->desc->ops->enable(dev_priv, power_well); power_well->hw_enabled = true; } @@ -167,7 +167,7 @@ static void intel_power_well_enable(struct drm_i915_private *dev_priv, static void intel_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name); + drm_dbg_kms(&dev_priv->drm, "disabling %s\n", power_well->desc->name); power_well->hw_enabled = false; power_well->desc->ops->disable(dev_priv, power_well); } @@ -289,8 +289,8 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ if (intel_de_wait_for_set(dev_priv, regs->driver, HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) { - DRM_DEBUG_KMS("%s power well enable timeout\n", - power_well->desc->name); + drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n", + power_well->desc->name); /* An AUX timeout is expected if the TBT DP tunnel is down. */ WARN_ON(!power_well->desc->hsw.is_tc_tbt); @@ -336,9 +336,10 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, if (disabled) return; - DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", - power_well->desc->name, - !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); + drm_dbg_kms(&dev_priv->drm, + "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", + power_well->desc->name, + !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); } static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, @@ -568,7 +569,8 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port), DKL_CMN_UC_DW27_UC_HEALTH, 1)) - DRM_WARN("Timeout waiting TC uC health\n"); + drm_warn(&dev_priv->drm, + "Timeout waiting TC uC health\n"); } } @@ -676,13 +678,15 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv, } while (rewrites < 100); if (v != state) - DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", - state, v); + drm_err(&dev_priv->drm, + "Writing dc state to 0x%x failed, now 0x%x\n", + state, v); /* Most of the times we need one retry, avoid spam */ if (rewrites > 1) - DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", - state, rewrites); + drm_dbg_kms(&dev_priv->drm, + "Rewrote dc state to 0x%x %d times\n", + state, rewrites); } static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) @@ -710,8 +714,9 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); - DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", - dev_priv->csr.dc_state, val); + drm_dbg_kms(&dev_priv->drm, + "Resetting DC state tracking from %02x to %02x\n", + dev_priv->csr.dc_state, val); dev_priv->csr.dc_state = val; } @@ -748,13 +753,13 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) val = I915_READ(DC_STATE_EN); mask = gen9_dc_mask(dev_priv); - DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", - val & mask, state); + drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n", + val & mask, state); /* Check if DMC is ignoring our DC state requests */ if ((val & mask) != dev_priv->csr.dc_state) - DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", - dev_priv->csr.dc_state, val & mask); + drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n", + dev_priv->csr.dc_state, val & mask); val &= ~mask; val |= state; @@ -791,7 +796,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv, static void tgl_enable_dc3co(struct drm_i915_private *dev_priv) { - DRM_DEBUG_KMS("Enabling DC3CO\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n"); gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); } @@ -799,7 +804,7 @@ static void tgl_disable_dc3co(struct drm_i915_private *dev_priv) { u32 val; - DRM_DEBUG_KMS("Disabling DC3CO\n"); + drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n"); val = I915_READ(DC_STATE_EN); val &= ~DC_STATE_DC3CO_STATUS; I915_WRITE(DC_STATE_EN, val); @@ -814,7 +819,7 @@ static void bxt_enable_dc9(struct drm_i915_private *dev_priv) { assert_can_enable_dc9(dev_priv); - DRM_DEBUG_KMS("Enabling DC9\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n"); /* * Power sequencer reset is not needed on * platforms with South Display Engine on PCH, @@ -829,7 +834,7 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv) { assert_can_disable_dc9(dev_priv); - DRM_DEBUG_KMS("Disabling DC9\n"); + drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n"); gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); @@ -928,7 +933,7 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv) { assert_can_enable_dc5(dev_priv); - DRM_DEBUG_KMS("Enabling DC5\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n"); /* Wa Display #1183: skl,kbl,cfl */ if (IS_GEN9_BC(dev_priv)) @@ -952,7 +957,7 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv) { assert_can_enable_dc6(dev_priv); - DRM_DEBUG_KMS("Enabling DC6\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n"); /* Wa Display #1183: skl,kbl,cfl */ if (IS_GEN9_BC(dev_priv)) @@ -1163,9 +1168,10 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv, vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); if (wait_for(COND, 100)) - DRM_ERROR("timeout setting power well state %08x (%08x)\n", - state, - vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); + drm_err(&dev_priv->drm, + "timeout setting power well state %08x (%08x)\n", + state, + vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); #undef COND @@ -1467,9 +1473,10 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv) */ if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS, phy_status_mask, phy_status, 10)) - DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", - I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, - phy_status, dev_priv->chv_phy_control); + drm_err(&dev_priv->drm, + "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", + I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, + phy_status, dev_priv->chv_phy_control); } #undef BITS_SET @@ -1499,7 +1506,8 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, /* Poll for phypwrgood signal */ if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS, PHY_POWERGOOD(phy), 1)) - DRM_ERROR("Display PHY %d is not power up\n", phy); + drm_err(&dev_priv->drm, "Display PHY %d is not power up\n", + phy); vlv_dpio_get(dev_priv); @@ -1529,8 +1537,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); - DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", - phy, dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, + "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", + phy, dev_priv->chv_phy_control); assert_chv_phy_status(dev_priv); } @@ -1557,8 +1566,9 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, vlv_set_power_well(dev_priv, power_well, false); - DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", - phy, dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, + "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", + phy, dev_priv->chv_phy_control); /* PHY is fully reset now, so we can enable the PHY state asserts */ dev_priv->chv_phy_assert[phy] = true; @@ -1648,8 +1658,9 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); - DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", - phy, ch, dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, + "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", + phy, ch, dev_priv->chv_phy_control); assert_chv_phy_status(dev_priv); @@ -1679,8 +1690,9 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); - DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", - phy, ch, mask, dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, + "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", + phy, ch, mask, dev_priv->chv_phy_control); assert_chv_phy_status(dev_priv); @@ -1742,9 +1754,10 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); if (wait_for(COND, 100)) - DRM_ERROR("timeout setting power well state %08x (%08x)\n", - state, - vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); + drm_err(&dev_priv->drm, + "timeout setting power well state %08x (%08x)\n", + state, + vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); #undef COND @@ -4204,11 +4217,13 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, } else if (enable_dc == -1) { requested_dc = max_dc; } else if (enable_dc > max_dc && enable_dc <= 4) { - DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", - enable_dc, max_dc); + drm_dbg_kms(&dev_priv->drm, + "Adjusting requested max DC state (%d->%d)\n", + enable_dc, max_dc); requested_dc = max_dc; } else { - DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); + drm_err(&dev_priv->drm, + "Unexpected value for enable_dc (%d)\n", enable_dc); requested_dc = max_dc; } @@ -4227,7 +4242,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, break; } - DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); + drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask); return mask; } @@ -4379,8 +4394,8 @@ bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv, status = I915_READ(reg) & DBUF_POWER_STATE; if ((enable && !status) || (!enable && status)) { - DRM_ERROR("DBus power %s timeout!\n", - enable ? "enable" : "disable"); + drm_err(&dev_priv->drm, "DBus power %s timeout!\n", + enable ? "enable" : "disable"); return false; } return true; @@ -4410,7 +4425,8 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, bool ret; if (req_slices > intel_dbuf_max_slices(dev_priv)) { - DRM_ERROR("Invalid number of dbuf slices requested\n"); + drm_err(&dev_priv->drm, + "Invalid number of dbuf slices requested\n"); return; } @@ -4436,7 +4452,7 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv) if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) - DRM_ERROR("DBuf power enable timeout\n"); + drm_err(&dev_priv->drm, "DBuf power enable timeout\n"); else /* * FIXME: for now pretend that we only have 1 slice, see @@ -4455,7 +4471,7 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv) if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) - DRM_ERROR("DBuf power disable timeout!\n"); + drm_err(&dev_priv->drm, "DBuf power disable timeout!\n"); else /* * FIXME: for now pretend that the first slice is always @@ -4487,13 +4503,13 @@ static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) */ if (val & LCPLL_CD_SOURCE_FCLK) - DRM_ERROR("CDCLK source is not LCPLL\n"); + drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); if (val & LCPLL_PLL_DISABLE) - DRM_ERROR("LCPLL is disabled\n"); + drm_err(&dev_priv->drm, "LCPLL is disabled\n"); if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) - DRM_ERROR("LCPLL not using non-SSC reference\n"); + drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n"); } static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) @@ -4549,7 +4565,8 @@ static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) if (IS_HASWELL(dev_priv)) { if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) - DRM_DEBUG_KMS("Failed to write to D_COMP\n"); + drm_dbg_kms(&dev_priv->drm, + "Failed to write to D_COMP\n"); } else { I915_WRITE(D_COMP_BDW, val); POSTING_READ(D_COMP_BDW); @@ -4579,7 +4596,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, if (wait_for_us(I915_READ(LCPLL_CTL) & LCPLL_CD_SOURCE_FCLK_DONE, 1)) - DRM_ERROR("Switching to FCLK failed\n"); + drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); val = I915_READ(LCPLL_CTL); } @@ -4589,7 +4606,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, POSTING_READ(LCPLL_CTL); if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) - DRM_ERROR("LCPLL still locked\n"); + drm_err(&dev_priv->drm, "LCPLL still locked\n"); val = hsw_read_dcomp(dev_priv); val |= D_COMP_COMP_DISABLE; @@ -4598,7 +4615,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) - DRM_ERROR("D_COMP RCOMP still in progress\n"); + drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n"); if (allow_power_down) { val = I915_READ(LCPLL_CTL); @@ -4644,7 +4661,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) I915_WRITE(LCPLL_CTL, val); if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) - DRM_ERROR("LCPLL not locked yet\n"); + drm_err(&dev_priv->drm, "LCPLL not locked yet\n"); if (val & LCPLL_CD_SOURCE_FCLK) { val = I915_READ(LCPLL_CTL); @@ -4653,7 +4670,8 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) if (wait_for_us((I915_READ(LCPLL_CTL) & LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) - DRM_ERROR("Switching back to LCPLL failed\n"); + drm_err(&dev_priv->drm, + "Switching back to LCPLL failed\n"); } intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); @@ -4689,7 +4707,7 @@ static void hsw_enable_pc8(struct drm_i915_private *dev_priv) { u32 val; - DRM_DEBUG_KMS("Enabling package C8+\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n"); if (HAS_PCH_LPT_LP(dev_priv)) { val = I915_READ(SOUTH_DSPCLK_GATE_D); @@ -4705,7 +4723,7 @@ static void hsw_disable_pc8(struct drm_i915_private *dev_priv) { u32 val; - DRM_DEBUG_KMS("Disabling package C8+\n"); + drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n"); hsw_restore_lcpll(dev_priv); intel_init_pch_refclk(dev_priv); @@ -4964,7 +4982,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) break; if (table[i].page_mask == 0) { - DRM_DEBUG_DRIVER("Unknown memory configuration; disabling address buddy logic.\n"); + drm_dbg(&dev_priv->drm, + "Unknown memory configuration; disabling address buddy logic.\n"); I915_WRITE(BW_BUDDY1_CTL, BW_BUDDY_DISABLE); I915_WRITE(BW_BUDDY2_CTL, BW_BUDDY_DISABLE); } else { @@ -5125,8 +5144,8 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); - DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", - dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n", + dev_priv->chv_phy_control); } static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) @@ -5142,7 +5161,7 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) I915_READ(DPIO_CTL) & DPIO_CMNRST) return; - DRM_DEBUG_KMS("toggling display PHY side reset\n"); + drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n"); /* cmnlane needs DPLL registers */ disp2d->desc->ops->enable(dev_priv, disp2d); @@ -5417,13 +5436,13 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915) for_each_power_well(i915, power_well) { enum intel_display_power_domain domain; - DRM_DEBUG_DRIVER("%-25s %d\n", - power_well->desc->name, power_well->count); + drm_dbg(&i915->drm, "%-25s %d\n", + power_well->desc->name, power_well->count); for_each_power_domain(domain, power_well->desc->domains) - DRM_DEBUG_DRIVER(" %-23s %d\n", - intel_display_power_domain_str(domain), - power_domains->domain_use_count[domain]); + drm_dbg(&i915->drm, " %-23s %d\n", + intel_display_power_domain_str(domain), + power_domains->domain_use_count[domain]); } } @@ -5456,19 +5475,21 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915) enabled = power_well->desc->ops->is_enabled(i915, power_well); if ((power_well->count || power_well->desc->always_on) != enabled) - DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)", - power_well->desc->name, - power_well->count, enabled); + drm_err(&i915->drm, + "power well %s state mismatch (refcount %d/enabled %d)", + power_well->desc->name, + power_well->count, enabled); domains_count = 0; for_each_power_domain(domain, power_well->desc->domains) domains_count += power_domains->domain_use_count[domain]; if (power_well->count != domains_count) { - DRM_ERROR("power well %s refcount/domain refcount mismatch " - "(refcount %d/domains refcount %d)\n", - power_well->desc->name, power_well->count, - domains_count); + drm_err(&i915->drm, + "power well %s refcount/domain refcount mismatch " + "(refcount %d/domains refcount %d)\n", + power_well->desc->name, power_well->count, + domains_count); dump_domain_info = true; } } From patchwork Tue Jan 21 14:31:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wambui Karuga X-Patchwork-Id: 11344295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE88392A for ; Tue, 21 Jan 2020 17:20:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB28B206A2 for ; Tue, 21 Jan 2020 17:20:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Pj3adZwn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BB28B206A2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DCD9B6EDE6; Tue, 21 Jan 2020 17:20:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id DCC216FADE; Tue, 21 Jan 2020 14:32:16 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id f129so3285131wmf.2; Tue, 21 Jan 2020 06:32:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=GCjWYLv/54CzryQk1PV5EEmYO6InO/2XIjjVII15PXM=; b=Pj3adZwnw1JNyHE4nI7A279N4OU4vEdBpoqIXi/UeUVyskG1n39t9ULoPB+mC4TZ8x igg/YIw5XPZWqlx/Piy2HwSA7xhAtPlh0XOIQ3jUMWORcy9HujnYhhCAfPYjiYptoQEg W4PjpVk/hzW298uvusyjRd+jU/ISfT+fcMxeqmoAmrmB9yeEHwbVYX0NsJrdyrkuYxZJ vElUGSn+Fv81fXBehWFkF8AYx6WD+VYQPGXkbquXNCD7vKbagr/T5YyNVcO57qopeALT xKaAq92uVF1X1IR/1d1R8yk5Jzf2F8BcpkRsaKGZv+RxsFfj6rg7S86+mryB6v4f/VBP +Uqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=GCjWYLv/54CzryQk1PV5EEmYO6InO/2XIjjVII15PXM=; b=tCupEXgUHOSv+Fjy69cauJ5v+pOOEaSxsofvSVmfsxo0BgGJd2fIOhy7Brxm/Uf7Xg utL0nIi6vr3+MvX8C9CVIIWDngKk+KwVKuSJWQLNNYPGwyNOoft7OM6NnvScXIkb19zt j+AedW1BQjRvM6qa37tuKynL89GB6U5s8f98OmVJQLmxgYyaOjvW8McfFrreHG+6x71M /h8TR6AigCg+jB/KkpB8pt4rYFB6NUa+xGiFcAGnuWw7Q57wlBBuiUFs6GVNXJAOBsJy ESN+KyYjwy8CKf1RT08qLWZq0eEr1RlRWF9IGYmQTfvOu0W08onIxXGDr3Rd6ixq6277 QVww== X-Gm-Message-State: APjAAAX3yef5TU7m4ogFbPYQ1oibA/LbpWez86qLv/vJjFj/AGYraWin s38x20JRj63DvQh/LChb9Zs= X-Google-Smtp-Source: APXvYqzOI/yhCSpygmyMOy7uxcYPdLp/C96EZwnk2Aea85Nbopgt8zuBAkOIw0240vv3jO0O6LSbvg== X-Received: by 2002:a1c:638a:: with SMTP id x132mr4552137wmb.43.1579617135097; Tue, 21 Jan 2020 06:32:15 -0800 (PST) Received: from localhost.localdomain ([197.254.95.38]) by smtp.googlemail.com with ESMTPSA id g2sm52781284wrw.76.2020.01.21.06.32.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2020 06:32:14 -0800 (PST) From: Wambui Karuga To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, airlied@linux.ie, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Tue, 21 Jan 2020 17:31:53 +0300 Message-Id: <20200121143155.20856-5-wambui.karugax@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200121143155.20856-1-wambui.karugax@gmail.com> References: <20200121143155.20856-1-wambui.karugax@gmail.com> X-Mailman-Approved-At: Tue, 21 Jan 2020 17:20:38 +0000 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/dp: conversion to struct drm_device logging macros. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This converts various instances of printk based logging macros in i915/display/intel_dp.c with the new struct drm_device based logging macros using the following coccinelle script: @rule1@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @rule2@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } New checkpatch warnings were fixed manually. Signed-off-by: Wambui Karuga --- drivers/gpu/drm/i915/display/intel_dp.c | 349 ++++++++++++++---------- 1 file changed, 201 insertions(+), 148 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8718f079b0d4..9737590c81d5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -519,12 +519,13 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, */ bits_per_pixel = (link_clock * lane_count * 8) / intel_dp_mode_to_fec_clock(mode_clock); - DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel); + drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; - DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram); + drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n", + max_bpp_small_joiner_ram); /* * Greatest allowed DSC BPP = MIN (output BPP from available Link BW @@ -534,8 +535,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, /* Error out if the max bpp is less than smallest allowed valid bpp */ if (bits_per_pixel < valid_dsc_bpp[0]) { - DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n", - bits_per_pixel, valid_dsc_bpp[0]); + drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", + bits_per_pixel, valid_dsc_bpp[0]); return 0; } @@ -766,9 +767,10 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) intel_dig_port->base.base.name)) return; - DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, + "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", + pipe_name(pipe), intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); /* Preserve the BIOS-computed detected bit. This is * supposed to be read-only. @@ -795,8 +797,9 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { - DRM_ERROR("Failed to force on pll for pipe %c!\n", - pipe_name(pipe)); + drm_err(&dev_priv->drm, + "Failed to force on pll for pipe %c!\n", + pipe_name(pipe)); return; } } @@ -886,10 +889,11 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) vlv_steal_power_sequencer(dev_priv, pipe); intel_dp->pps_pipe = pipe; - DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n", - pipe_name(intel_dp->pps_pipe), - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, + "picked pipe %c power sequencer for [ENCODER:%d:%s]\n", + pipe_name(intel_dp->pps_pipe), + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); /* init power sequencer on this pipe and port */ intel_dp_init_panel_power_sequencer(intel_dp); @@ -997,16 +1001,18 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ if (intel_dp->pps_pipe == INVALID_PIPE) { - DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, + "no initial power sequencer for [ENCODER:%d:%s]\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); return; } - DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name, - pipe_name(intel_dp->pps_pipe)); + drm_dbg_kms(&dev_priv->drm, + "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name, + pipe_name(intel_dp->pps_pipe)); intel_dp_init_panel_power_sequencer(intel_dp); intel_dp_init_panel_power_sequencer_registers(intel_dp, false); @@ -1168,9 +1174,9 @@ intel_dp_check_edp(struct intel_dp *intel_dp) if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { WARN(1, "eDP powered off while attempting aux channel communication.\n"); - DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", - I915_READ(_pp_stat_reg(intel_dp)), - I915_READ(_pp_ctrl_reg(intel_dp))); + drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n", + I915_READ(_pp_stat_reg(intel_dp)), + I915_READ(_pp_ctrl_reg(intel_dp))); } } @@ -1191,8 +1197,9 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); if (!done) - DRM_ERROR("%s did not complete or timeout within %ums (status 0x%08x)\n", - intel_dp->aux.name, timeout_ms, status); + drm_err(&i915->drm, + "%s did not complete or timeout within %ums (status 0x%08x)\n", + intel_dp->aux.name, timeout_ms, status); #undef C return status; @@ -1440,7 +1447,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, } if ((status & DP_AUX_CH_CTL_DONE) == 0) { - DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); + drm_err(&i915->drm, "dp_aux_ch not done status 0x%08x\n", + status); ret = -EBUSY; goto out; } @@ -1450,7 +1458,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, * Timeouts occur when the sink is not connected */ if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { - DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); + drm_err(&i915->drm, "dp_aux_ch receive error status 0x%08x\n", + status); ret = -EIO; goto out; } @@ -1458,7 +1467,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, /* Timeouts occur when the device isn't connected, so they're * "normal" -- don't fill the kernel log with these */ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { - DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); + drm_dbg_kms(&i915->drm, "dp_aux_ch timeout status 0x%08x\n", + status); ret = -ETIMEDOUT; goto out; } @@ -1473,8 +1483,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, * drm layer takes care for the necessary retries. */ if (recv_bytes == 0 || recv_bytes > 20) { - DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", - recv_bytes); + drm_dbg_kms(&i915->drm, + "Forbidden recv_bytes = %d on aux transaction\n", + recv_bytes); ret = -EBUSY; goto out; } @@ -1918,8 +1929,9 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, /* Get bpp from vbt only for panels that dont have bpp in edid */ if (intel_connector->base.display_info.bpc == 0 && dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { - DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", - dev_priv->vbt.edp.bpp); + drm_dbg_kms(&dev_priv->drm, + "clamping bpp for eDP panel to BIOS-provided %i\n", + dev_priv->vbt.edp.bpp); bpp = dev_priv->vbt.edp.bpp; } } @@ -2115,7 +2127,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, /* Min Input BPC for ICL+ is 8 */ if (pipe_bpp < 8 * 3) { - DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); + drm_dbg_kms(&dev_priv->drm, + "No DSC support for less than 8bpc\n"); return -EINVAL; } @@ -2150,7 +2163,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay); if (!dsc_max_output_bpp || !dsc_dp_slice_count) { - DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); + drm_dbg_kms(&dev_priv->drm, + "Compressed BPP/Slice Count not supported\n"); return -EINVAL; } pipe_config->dsc.compressed_bpp = min_t(u16, @@ -2167,26 +2181,28 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (pipe_config->dsc.slice_count > 1) { pipe_config->dsc.dsc_split = true; } else { - DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); + drm_dbg_kms(&dev_priv->drm, + "Cannot split stream to use 2 VDSC instances\n"); return -EINVAL; } } ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); if (ret < 0) { - DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d " - "Compressed BPP = %d\n", - pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp); + drm_dbg_kms(&dev_priv->drm, + "Cannot compute valid DSC parameters for Input Bpp = %d " + "Compressed BPP = %d\n", + pipe_config->pipe_bpp, + pipe_config->dsc.compressed_bpp); return ret; } pipe_config->dsc.compression_enable = true; - DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " - "Compressed Bpp = %d Slice Count = %d\n", - pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp, - pipe_config->dsc.slice_count); + drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " + "Compressed Bpp = %d Slice Count = %d\n", + pipe_config->pipe_bpp, + pipe_config->dsc.compressed_bpp, + pipe_config->dsc.slice_count); return 0; } @@ -2590,18 +2606,20 @@ static void wait_panel_status(struct intel_dp *intel_dp, pp_stat_reg = _pp_stat_reg(intel_dp); pp_ctrl_reg = _pp_ctrl_reg(intel_dp); - DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", - mask, value, - I915_READ(pp_stat_reg), - I915_READ(pp_ctrl_reg)); + drm_dbg_kms(&dev_priv->drm, + "mask %08x value %08x status %08x control %08x\n", + mask, value, + I915_READ(pp_stat_reg), + I915_READ(pp_ctrl_reg)); if (intel_de_wait_for_register(dev_priv, pp_stat_reg, mask, value, 5000)) - DRM_ERROR("Panel status timeout: status %08x control %08x\n", - I915_READ(pp_stat_reg), - I915_READ(pp_ctrl_reg)); + drm_err(&dev_priv->drm, + "Panel status timeout: status %08x control %08x\n", + I915_READ(pp_stat_reg), + I915_READ(pp_ctrl_reg)); - DRM_DEBUG_KMS("Wait complete\n"); + drm_dbg_kms(&dev_priv->drm, "Wait complete\n"); } static void wait_panel_on(struct intel_dp *intel_dp) @@ -2696,9 +2714,9 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) intel_display_power_get(dev_priv, intel_aux_power_domain(intel_dig_port)); - DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD on\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); if (!edp_have_panel_power(intel_dp)) wait_panel_power_cycle(intel_dp); @@ -2711,15 +2729,16 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) I915_WRITE(pp_ctrl_reg, pp); POSTING_READ(pp_ctrl_reg); - DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", - I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); + drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", + I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); /* * If the panel wasn't on, delay before accessing aux channel */ if (!edp_have_panel_power(intel_dp)) { - DRM_DEBUG_KMS("[ENCODER:%d:%s] panel power wasn't enabled\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] panel power wasn't enabled\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); msleep(intel_dp->panel_power_up_delay); } @@ -2764,9 +2783,9 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) if (!edp_have_panel_vdd(intel_dp)) return; - DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD off\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); pp = ilk_get_pp_control(intel_dp); pp &= ~EDP_FORCE_VDD; @@ -2778,8 +2797,8 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) POSTING_READ(pp_ctrl_reg); /* Make sure sequencer is idle before allowing subsequent activity */ - DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", - I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); + drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", + I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); if ((pp & PANEL_POWER_ON) == 0) intel_dp->panel_power_off_time = ktime_get_boottime(); @@ -2851,9 +2870,9 @@ static void edp_panel_on(struct intel_dp *intel_dp) if (!intel_dp_is_edp(intel_dp)) return; - DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power on\n", - dp_to_dig_port(intel_dp)->base.base.base.id, - dp_to_dig_port(intel_dp)->base.base.name); + drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n", + dp_to_dig_port(intel_dp)->base.base.base.id, + dp_to_dig_port(intel_dp)->base.base.name); if (WARN(edp_have_panel_power(intel_dp), "[ENCODER:%d:%s] panel power already on\n", @@ -2913,8 +2932,8 @@ static void edp_panel_off(struct intel_dp *intel_dp) if (!intel_dp_is_edp(intel_dp)) return; - DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power off\n", - dig_port->base.base.base.id, dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n", + dig_port->base.base.base.id, dig_port->base.base.name); WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n", dig_port->base.base.base.id, dig_port->base.base.name); @@ -3089,8 +3108,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, assert_dp_port_disabled(intel_dp); assert_edp_pll_disabled(dev_priv); - DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", - pipe_config->port_clock); + drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n", + pipe_config->port_clock); intel_dp->DP &= ~DP_PLL_FREQ_MASK; @@ -3129,7 +3148,7 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp, assert_dp_port_disabled(intel_dp); assert_edp_pll_enabled(dev_priv); - DRM_DEBUG_KMS("disabling eDP PLL\n"); + drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n"); intel_dp->DP &= ~DP_PLL_ENABLE; @@ -3222,7 +3241,8 @@ static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, } } - DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port)); + drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n", + port_name(port)); /* must initialize pipe to something for the asserts */ *pipe = PIPE_A; @@ -3353,8 +3373,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder, * up by the BIOS, and thus we can't get the mode at module * load. */ - DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", - pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); + drm_dbg_kms(&dev_priv->drm, + "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", + pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; } } @@ -3447,8 +3468,9 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); if (dp_train_pat & train_pat_mask) - DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", - dp_train_pat & train_pat_mask); + drm_dbg_kms(&dev_priv->drm, + "Using DP training pattern TPS%d\n", + dp_train_pat & train_pat_mask); if (HAS_DDI(dev_priv)) { u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl); @@ -3494,7 +3516,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, *DP |= DP_LINK_TRAIN_PAT_2_CPT; break; case DP_TRAINING_PATTERN_3: - DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); + drm_dbg_kms(&dev_priv->drm, + "TPS3 not supported, using TPS2 instead\n"); *DP |= DP_LINK_TRAIN_PAT_2_CPT; break; } @@ -3513,7 +3536,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, *DP |= DP_LINK_TRAIN_PAT_2; break; case DP_TRAINING_PATTERN_3: - DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); + drm_dbg_kms(&dev_priv->drm, + "TPS3 not supported, using TPS2 instead\n"); *DP |= DP_LINK_TRAIN_PAT_2; break; } @@ -3583,8 +3607,8 @@ static void intel_enable_dp(struct intel_encoder *encoder, intel_dp_stop_link_train(intel_dp); if (pipe_config->has_audio) { - DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", - pipe_name(pipe)); + drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n", + pipe_name(pipe)); intel_audio_codec_enable(encoder, pipe_config, conn_state); } } @@ -3641,9 +3665,10 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) * port select always when logically disconnecting a power sequencer * from a port. */ - DRM_DEBUG_KMS("detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, + "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", + pipe_name(pipe), intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); I915_WRITE(pp_on_reg, 0); POSTING_READ(pp_on_reg); @@ -3668,9 +3693,10 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, if (intel_dp->pps_pipe != pipe) continue; - DRM_DEBUG_KMS("stealing pipe %c power sequencer from [ENCODER:%d:%s]\n", - pipe_name(pipe), encoder->base.base.id, - encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n", + pipe_name(pipe), encoder->base.base.id, + encoder->base.name); /* make sure vdd is off before we steal it */ vlv_detach_power_sequencer(intel_dp); @@ -3712,9 +3738,10 @@ static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, /* now it's all ours */ intel_dp->pps_pipe = crtc->pipe; - DRM_DEBUG_KMS("initializing pipe %c power sequencer for [ENCODER:%d:%s]\n", - pipe_name(intel_dp->pps_pipe), encoder->base.base.id, - encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n", + pipe_name(intel_dp->pps_pipe), encoder->base.base.id, + encoder->base.name); /* init power sequencer on this pipe and port */ intel_dp_init_panel_power_sequencer(intel_dp); @@ -4140,13 +4167,14 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) } if (mask) - DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); + drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", + signal_levels); - DRM_DEBUG_KMS("Using vswing level %d\n", - train_set & DP_TRAIN_VOLTAGE_SWING_MASK); - DRM_DEBUG_KMS("Using pre-emphasis level %d\n", - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> - DP_TRAIN_PRE_EMPHASIS_SHIFT); + drm_dbg_kms(&dev_priv->drm, "Using vswing level %d\n", + train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d\n", + (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT); intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; @@ -4195,7 +4223,8 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, DP_TP_STATUS_IDLE_DONE, 1)) - DRM_ERROR("Timed out waiting for DP idle patterns\n"); + drm_err(&dev_priv->drm, + "Timed out waiting for DP idle patterns\n"); } static void @@ -4211,7 +4240,7 @@ intel_dp_link_down(struct intel_encoder *encoder, if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) return; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { @@ -4390,8 +4419,9 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == sizeof(intel_dp->edp_dpcd)) - DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd), - intel_dp->edp_dpcd); + drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", + (int)sizeof(intel_dp->edp_dpcd), + intel_dp->edp_dpcd); /* * This has to be called after intel_dp->edp_dpcd is filled, PSR checks @@ -5281,7 +5311,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp) intel_psr_short_pulse(intel_dp); if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { - DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); + drm_dbg_kms(&dev_priv->drm, + "Link Training Compliance Test requested\n"); /* Send a Hotplug Uevent to userspace to start modeset */ drm_kms_helper_hotplug_event(&dev_priv->drm); } @@ -5656,8 +5687,8 @@ intel_dp_detect(struct drm_connector *connector, struct intel_encoder *encoder = &dig_port->base; enum drm_connector_status status; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", - connector->base.id, connector->name); + drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); /* Can't disconnect eDP */ @@ -5673,9 +5704,10 @@ intel_dp_detect(struct drm_connector *connector, memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); if (intel_dp->is_mst) { - DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", - intel_dp->is_mst, - intel_dp->mst_mgr.mst_state); + drm_dbg_kms(&dev_priv->drm, + "MST device may have disappeared %d vs %d\n", + intel_dp->is_mst, + intel_dp->mst_mgr.mst_state); intel_dp->is_mst = false; drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); @@ -5763,8 +5795,8 @@ intel_dp_force(struct drm_connector *connector) intel_aux_power_domain(dig_port); intel_wakeref_t wakeref; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", - connector->base.id, connector->name); + drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); intel_dp_unset_edid(intel_dp); if (connector->status != connector_status_connected) @@ -6492,7 +6524,8 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) * schedule a vdd off, so we don't hold on to the reference * indefinitely. */ - DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); + drm_dbg_kms(&dev_priv->drm, + "VDD left on by BIOS, adjusting state tracking\n"); intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port)); edp_panel_vdd_schedule_off(intel_dp); @@ -6768,8 +6801,9 @@ intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) */ if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); - DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n", - vbt.t11_t12); + drm_dbg_kms(&dev_priv->drm, + "Increasing T12 panel delay as per the quirk to %d\n", + vbt.t11_t12); } /* T11_T12 delay is special and actually in units of 100ms, but zero * based in the hw (so we need to add 100 ms). But the sw vbt @@ -6811,12 +6845,15 @@ intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) intel_dp->panel_power_cycle_delay = get_delay(t11_t12); #undef get_delay - DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", - intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, - intel_dp->panel_power_cycle_delay); + drm_dbg_kms(&dev_priv->drm, + "panel power up delay %d, power down delay %d, power cycle delay %d\n", + intel_dp->panel_power_up_delay, + intel_dp->panel_power_down_delay, + intel_dp->panel_power_cycle_delay); - DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", - intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); + drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n", + intel_dp->backlight_on_delay, + intel_dp->backlight_off_delay); /* * We override the HW backlight delays to 1 because we do manual waits @@ -6868,7 +6905,8 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); if (pp & EDP_FORCE_VDD) - DRM_DEBUG_KMS("VDD already on, disabling first\n"); + drm_dbg_kms(&dev_priv->drm, + "VDD already on, disabling first\n"); pp &= ~EDP_FORCE_VDD; @@ -6922,12 +6960,13 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, I915_WRITE(regs.pp_ctrl, pp_ctl); } - DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", - I915_READ(regs.pp_on), - I915_READ(regs.pp_off), - i915_mmio_reg_valid(regs.pp_div) ? - I915_READ(regs.pp_div) : - (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); + drm_dbg_kms(&dev_priv->drm, + "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", + I915_READ(regs.pp_on), + I915_READ(regs.pp_off), + i915_mmio_reg_valid(regs.pp_div) ? + I915_READ(regs.pp_div) : + (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); } static void intel_dp_pps_init(struct intel_dp *intel_dp) @@ -6964,22 +7003,24 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, enum drrs_refresh_rate_type index = DRRS_HIGH_RR; if (refresh_rate <= 0) { - DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); + drm_dbg_kms(&dev_priv->drm, + "Refresh rate should be positive non-zero.\n"); return; } if (intel_dp == NULL) { - DRM_DEBUG_KMS("DRRS not supported.\n"); + drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); return; } if (!intel_crtc) { - DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); + drm_dbg_kms(&dev_priv->drm, + "DRRS: intel_crtc not initialized\n"); return; } if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { - DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); + drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); return; } @@ -6988,13 +7029,14 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, index = DRRS_LOW_RR; if (index == dev_priv->drrs.refresh_rate_type) { - DRM_DEBUG_KMS( - "DRRS requested for previously set RR...ignoring\n"); + drm_dbg_kms(&dev_priv->drm, + "DRRS requested for previously set RR...ignoring\n"); return; } if (!crtc_state->hw.active) { - DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); + drm_dbg_kms(&dev_priv->drm, + "eDP encoder disabled. CRTC not Active\n"); return; } @@ -7008,7 +7050,8 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, break; case DRRS_MAX_RR: default: - DRM_ERROR("Unsupported refreshrate type\n"); + drm_err(&dev_priv->drm, + "Unsupported refreshrate type\n"); } } else if (INTEL_GEN(dev_priv) > 6) { i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); @@ -7031,7 +7074,8 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, dev_priv->drrs.refresh_rate_type = index; - DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); + drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n", + refresh_rate); } /** @@ -7047,18 +7091,19 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); if (!crtc_state->has_drrs) { - DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); + drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n"); return; } if (dev_priv->psr.enabled) { - DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR enabled. Not enabling DRRS.\n"); return; } mutex_lock(&dev_priv->drrs.mutex); if (dev_priv->drrs.dp) { - DRM_DEBUG_KMS("DRRS already enabled\n"); + drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n"); goto unlock; } @@ -7284,25 +7329,28 @@ intel_dp_drrs_init(struct intel_connector *connector, mutex_init(&dev_priv->drrs.mutex); if (INTEL_GEN(dev_priv) <= 6) { - DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); + drm_dbg_kms(&dev_priv->drm, + "DRRS supported for Gen7 and above\n"); return NULL; } if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { - DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); + drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n"); return NULL; } downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); if (!downclock_mode) { - DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); + drm_dbg_kms(&dev_priv->drm, + "Downclock mode is not found. DRRS not supported\n"); return NULL; } dev_priv->drrs.type = dev_priv->vbt.drrs_type; dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; - DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); + drm_dbg_kms(&dev_priv->drm, + "seamless DRRS supported for eDP panel.\n"); return downclock_mode; } @@ -7332,7 +7380,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, */ if (intel_get_lvds_encoder(dev_priv)) { WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); - DRM_INFO("LVDS was detected, not registering eDP\n"); + drm_info(&dev_priv->drm, + "LVDS was detected, not registering eDP\n"); return false; } @@ -7348,7 +7397,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, if (!has_dpcd) { /* if this fails, presume the device is a ghost */ - DRM_INFO("failed to retrieve link info, disabling eDP\n"); + drm_info(&dev_priv->drm, + "failed to retrieve link info, disabling eDP\n"); goto out_vdd_off; } @@ -7393,8 +7443,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, if (pipe != PIPE_A && pipe != PIPE_B) pipe = PIPE_A; - DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", - pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, + "using pipe %c for initial backlight setup\n", + pipe_name(pipe)); } intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); @@ -7506,9 +7557,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, port != PORT_B && port != PORT_C)) return false; - DRM_DEBUG_KMS("Adding %s connector on [ENCODER:%d:%s]\n", - type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", - intel_encoder->base.base.id, intel_encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "Adding %s connector on [ENCODER:%d:%s]\n", + type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", + intel_encoder->base.base.id, intel_encoder->base.name); drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); @@ -7546,7 +7598,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim); if (ret) - DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); + drm_dbg_kms(&dev_priv->drm, + "HDCP init failed, skipping.\n"); } /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written From patchwork Tue Jan 21 14:31:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wambui Karuga X-Patchwork-Id: 11344311 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 264BE109A for ; Tue, 21 Jan 2020 17:20:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 03EC0206A2 for ; Tue, 21 Jan 2020 17:20:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eAL75MWR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 03EC0206A2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 185536EE0C; Tue, 21 Jan 2020 17:20:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id C53236FADE; Tue, 21 Jan 2020 14:32:19 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id q6so3409580wro.9; Tue, 21 Jan 2020 06:32:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=eX5dN8pc5/AqQ+ewdF/FEabxhls400zFnN0NLpFFaDA=; b=eAL75MWRemE56AlCJlVhLsDsLrAhVKygtm+5/hGMVxCEXNkFiVxDLRV3+hMFoBOOm9 FGkX6TldQegc/uHiCibQlmjspUHMEclyuYSICDEiy7Nhx3mDa1QPutYrXB6JWdJ74s5b 0uWxKGzNeEX6hqzHjQdD5F6vPbr35ztd0wfMr1MgGFcqkbjg3KVSOcP762Mc1vgo2EcN qTkwMngOtDLYsZVUo9v4z15wloxFnMl6g0600hofW2buiBgfoqUTsrRq/RfiG/FFb45O 3tiOS1kmzbw8iPsA09jIsmIZr8rugBA0WvqjG0TCCA1bAu5GUhVgzDBZ2BK+/X3uRMDK ftww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=eX5dN8pc5/AqQ+ewdF/FEabxhls400zFnN0NLpFFaDA=; b=YbZamyE81p1az2yVWkHWrK5ON555Qnj9QjnCfI+rKgnDH1sh4eT7hLtoafyOrmeEwT WO6Gc1sz8HuMQsSJD7nZ5Ey3V6awqlbnOGa7rxcWv5Nuv6JocLl0cIQJhuqRhDBpolZF RoYzfK7229llEcLO479iXwabqch+c35OZjEfAh9uO06MaJN7EmdDboEyUgMVcuhh8PwN 3I24CtN58ZphCquHLSgWziOtNSvLdToHKLqleukKpNrhL/EnCmcp2ayF2Iq4zrO9miJ9 C684UQAM2AT2ul5lSJVxQxMFV0LXcz7JNDB5hT0r/R7b7bSBNk9JOa54RHW/BlQg4yy7 uPEg== X-Gm-Message-State: APjAAAWxY/e3sOFbx1M0q3s8K24OzYywO2J0OEHCKWwIfib/biIQ57ys POtaRh2ZanqJ0+zKHlnxheA= X-Google-Smtp-Source: APXvYqz6InHDLh7rzauyvAAYGvJ6r9cK9ZIPHHmBGJEtEFBxO7YIdkD7pi+SR+8X9zP9jIRVa5jb8w== X-Received: by 2002:a5d:6344:: with SMTP id b4mr5496384wrw.414.1579617138212; Tue, 21 Jan 2020 06:32:18 -0800 (PST) Received: from localhost.localdomain ([197.254.95.38]) by smtp.googlemail.com with ESMTPSA id g2sm52781284wrw.76.2020.01.21.06.32.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2020 06:32:17 -0800 (PST) From: Wambui Karuga To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, airlied@linux.ie, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Tue, 21 Jan 2020 17:31:54 +0300 Message-Id: <20200121143155.20856-6-wambui.karugax@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200121143155.20856-1-wambui.karugax@gmail.com> References: <20200121143155.20856-1-wambui.karugax@gmail.com> X-Mailman-Approved-At: Tue, 21 Jan 2020 17:20:38 +0000 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/opregion: conversion to struct drm_device logging macros. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This converts various instances of the printk based logging macros in i915/display/intel_opregion.c with the new struct drm_device based logging macros using the following coccinelle script: @rule1@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @rule2@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } Checkpatch warnings were addressed manually. Signed-off-by: Wambui Karuga --- drivers/gpu/drm/i915/display/intel_opregion.c | 134 +++++++++++------- 1 file changed, 80 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index e59b4992ba1b..b54fe4dc0423 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -311,7 +311,7 @@ static int swsci(struct drm_i915_private *dev_priv, /* The spec tells us to do this, but we are the only user... */ scic = swsci->scic; if (scic & SWSCI_SCIC_INDICATOR) { - DRM_DEBUG_DRIVER("SWSCI request already in progress\n"); + drm_dbg(&dev_priv->drm, "SWSCI request already in progress\n"); return -EBUSY; } @@ -335,7 +335,7 @@ static int swsci(struct drm_i915_private *dev_priv, /* Poll for the result. */ #define C (((scic = swsci->scic) & SWSCI_SCIC_INDICATOR) == 0) if (wait_for(C, dslp)) { - DRM_DEBUG_DRIVER("SWSCI request timed out\n"); + drm_dbg(&dev_priv->drm, "SWSCI request timed out\n"); return -ETIMEDOUT; } @@ -344,7 +344,7 @@ static int swsci(struct drm_i915_private *dev_priv, /* Note: scic == 0 is an error! */ if (scic != SWSCI_SCIC_EXIT_STATUS_SUCCESS) { - DRM_DEBUG_DRIVER("SWSCI request error %u\n", scic); + drm_dbg(&dev_priv->drm, "SWSCI request error %u\n", scic); return -EIO; } @@ -448,10 +448,11 @@ static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp) struct opregion_asle *asle = dev_priv->opregion.asle; struct drm_device *dev = &dev_priv->drm; - DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp); + drm_dbg(&dev_priv->drm, "bclp = 0x%08x\n", bclp); if (acpi_video_get_backlight_type() == acpi_backlight_native) { - DRM_DEBUG_KMS("opregion backlight request ignored\n"); + drm_dbg_kms(&dev_priv->drm, + "opregion backlight request ignored\n"); return 0; } @@ -468,7 +469,8 @@ static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp) * Update backlight on all connectors that support backlight (usually * only one). */ - DRM_DEBUG_KMS("updating opregion backlight %d/255\n", bclp); + drm_dbg_kms(&dev_priv->drm, "updating opregion backlight %d/255\n", + bclp); drm_connector_list_iter_begin(dev, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) intel_panel_set_backlight_acpi(connector->base.state, bclp, 255); @@ -485,13 +487,13 @@ static u32 asle_set_als_illum(struct drm_i915_private *dev_priv, u32 alsi) { /* alsi is the current ALS reading in lux. 0 indicates below sensor range, 0xffff indicates above sensor range. 1-0xfffe are valid */ - DRM_DEBUG_DRIVER("Illum is not supported\n"); + drm_dbg(&dev_priv->drm, "Illum is not supported\n"); return ASLC_ALS_ILLUM_FAILED; } static u32 asle_set_pwm_freq(struct drm_i915_private *dev_priv, u32 pfmb) { - DRM_DEBUG_DRIVER("PWM freq is not supported\n"); + drm_dbg(&dev_priv->drm, "PWM freq is not supported\n"); return ASLC_PWM_FREQ_FAILED; } @@ -499,30 +501,36 @@ static u32 asle_set_pfit(struct drm_i915_private *dev_priv, u32 pfit) { /* Panel fitting is currently controlled by the X code, so this is a noop until modesetting support works fully */ - DRM_DEBUG_DRIVER("Pfit is not supported\n"); + drm_dbg(&dev_priv->drm, "Pfit is not supported\n"); return ASLC_PFIT_FAILED; } static u32 asle_set_supported_rotation_angles(struct drm_i915_private *dev_priv, u32 srot) { - DRM_DEBUG_DRIVER("SROT is not supported\n"); + drm_dbg(&dev_priv->drm, "SROT is not supported\n"); return ASLC_ROTATION_ANGLES_FAILED; } static u32 asle_set_button_array(struct drm_i915_private *dev_priv, u32 iuer) { if (!iuer) - DRM_DEBUG_DRIVER("Button array event is not supported (nothing)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (nothing)\n"); if (iuer & ASLE_IUER_ROTATION_LOCK_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (rotation lock)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (rotation lock)\n"); if (iuer & ASLE_IUER_VOLUME_DOWN_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (volume down)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (volume down)\n"); if (iuer & ASLE_IUER_VOLUME_UP_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (volume up)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (volume up)\n"); if (iuer & ASLE_IUER_WINDOWS_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (windows)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (windows)\n"); if (iuer & ASLE_IUER_POWER_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (power)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (power)\n"); return ASLC_BUTTON_ARRAY_FAILED; } @@ -530,9 +538,11 @@ static u32 asle_set_button_array(struct drm_i915_private *dev_priv, u32 iuer) static u32 asle_set_convertible(struct drm_i915_private *dev_priv, u32 iuer) { if (iuer & ASLE_IUER_CONVERTIBLE) - DRM_DEBUG_DRIVER("Convertible is not supported (clamshell)\n"); + drm_dbg(&dev_priv->drm, + "Convertible is not supported (clamshell)\n"); else - DRM_DEBUG_DRIVER("Convertible is not supported (slate)\n"); + drm_dbg(&dev_priv->drm, + "Convertible is not supported (slate)\n"); return ASLC_CONVERTIBLE_FAILED; } @@ -540,16 +550,17 @@ static u32 asle_set_convertible(struct drm_i915_private *dev_priv, u32 iuer) static u32 asle_set_docking(struct drm_i915_private *dev_priv, u32 iuer) { if (iuer & ASLE_IUER_DOCKING) - DRM_DEBUG_DRIVER("Docking is not supported (docked)\n"); + drm_dbg(&dev_priv->drm, "Docking is not supported (docked)\n"); else - DRM_DEBUG_DRIVER("Docking is not supported (undocked)\n"); + drm_dbg(&dev_priv->drm, + "Docking is not supported (undocked)\n"); return ASLC_DOCKING_FAILED; } static u32 asle_isct_state(struct drm_i915_private *dev_priv) { - DRM_DEBUG_DRIVER("ISCT is not supported\n"); + drm_dbg(&dev_priv->drm, "ISCT is not supported\n"); return ASLC_ISCT_STATE_FAILED; } @@ -569,8 +580,8 @@ static void asle_work(struct work_struct *work) aslc_req = asle->aslc; if (!(aslc_req & ASLC_REQ_MSK)) { - DRM_DEBUG_DRIVER("No request on ASLC interrupt 0x%08x\n", - aslc_req); + drm_dbg(&dev_priv->drm, + "No request on ASLC interrupt 0x%08x\n", aslc_req); return; } @@ -739,11 +750,12 @@ static void intel_didl_outputs(struct drm_i915_private *dev_priv) } drm_connector_list_iter_end(&conn_iter); - DRM_DEBUG_KMS("%d outputs detected\n", i); + drm_dbg_kms(&dev_priv->drm, "%d outputs detected\n", i); if (i > max_outputs) - DRM_ERROR("More than %d outputs in connector list\n", - max_outputs); + drm_err(&dev_priv->drm, + "More than %d outputs in connector list\n", + max_outputs); /* If fewer than max outputs, the list must be null terminated */ if (i < max_outputs) @@ -823,7 +835,9 @@ static void swsci_setup(struct drm_i915_private *dev_priv) if (requested_callbacks) { u32 req = opregion->swsci_sbcb_sub_functions; if ((req & tmp) != req) - DRM_DEBUG_DRIVER("SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x)\n", req, tmp); + drm_dbg(&dev_priv->drm, + "SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x)\n", + req, tmp); /* XXX: for now, trust the requested callbacks */ /* opregion->swsci_sbcb_sub_functions &= tmp; */ } else { @@ -831,9 +845,10 @@ static void swsci_setup(struct drm_i915_private *dev_priv) } } - DRM_DEBUG_DRIVER("SWSCI GBDA callbacks %08x, SBCB callbacks %08x\n", - opregion->swsci_gbda_sub_functions, - opregion->swsci_sbcb_sub_functions); + drm_dbg(&dev_priv->drm, + "SWSCI GBDA callbacks %08x, SBCB callbacks %08x\n", + opregion->swsci_gbda_sub_functions, + opregion->swsci_sbcb_sub_functions); } static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id) @@ -867,15 +882,17 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) ret = request_firmware(&fw, name, &dev_priv->drm.pdev->dev); if (ret) { - DRM_ERROR("Requesting VBT firmware \"%s\" failed (%d)\n", - name, ret); + drm_err(&dev_priv->drm, + "Requesting VBT firmware \"%s\" failed (%d)\n", + name, ret); return ret; } if (intel_bios_is_valid_vbt(fw->data, fw->size)) { opregion->vbt_firmware = kmemdup(fw->data, fw->size, GFP_KERNEL); if (opregion->vbt_firmware) { - DRM_DEBUG_KMS("Found valid VBT firmware \"%s\"\n", name); + drm_dbg_kms(&dev_priv->drm, + "Found valid VBT firmware \"%s\"\n", name); opregion->vbt = opregion->vbt_firmware; opregion->vbt_size = fw->size; ret = 0; @@ -883,7 +900,8 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) ret = -ENOMEM; } } else { - DRM_DEBUG_KMS("Invalid VBT firmware \"%s\"\n", name); + drm_dbg_kms(&dev_priv->drm, "Invalid VBT firmware \"%s\"\n", + name); ret = -EINVAL; } @@ -910,9 +928,10 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400); pci_read_config_dword(pdev, ASLS, &asls); - DRM_DEBUG_DRIVER("graphic opregion physical addr: 0x%x\n", asls); + drm_dbg(&dev_priv->drm, "graphic opregion physical addr: 0x%x\n", + asls); if (asls == 0) { - DRM_DEBUG_DRIVER("ACPI OpRegion not supported!\n"); + drm_dbg(&dev_priv->drm, "ACPI OpRegion not supported!\n"); return -ENOTSUPP; } @@ -925,21 +944,21 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) memcpy(buf, base, sizeof(buf)); if (memcmp(buf, OPREGION_SIGNATURE, 16)) { - DRM_DEBUG_DRIVER("opregion signature mismatch\n"); + drm_dbg(&dev_priv->drm, "opregion signature mismatch\n"); err = -EINVAL; goto err_out; } opregion->header = base; opregion->lid_state = base + ACPI_CLID; - DRM_DEBUG_DRIVER("ACPI OpRegion version %u.%u.%u\n", - opregion->header->over.major, - opregion->header->over.minor, - opregion->header->over.revision); + drm_dbg(&dev_priv->drm, "ACPI OpRegion version %u.%u.%u\n", + opregion->header->over.major, + opregion->header->over.minor, + opregion->header->over.revision); mboxes = opregion->header->mboxes; if (mboxes & MBOX_ACPI) { - DRM_DEBUG_DRIVER("Public ACPI methods supported\n"); + drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n"); opregion->acpi = base + OPREGION_ACPI_OFFSET; /* * Indicate we handle monitor hotplug events ourselves so we do @@ -951,20 +970,20 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) } if (mboxes & MBOX_SWSCI) { - DRM_DEBUG_DRIVER("SWSCI supported\n"); + drm_dbg(&dev_priv->drm, "SWSCI supported\n"); opregion->swsci = base + OPREGION_SWSCI_OFFSET; swsci_setup(dev_priv); } if (mboxes & MBOX_ASLE) { - DRM_DEBUG_DRIVER("ASLE supported\n"); + drm_dbg(&dev_priv->drm, "ASLE supported\n"); opregion->asle = base + OPREGION_ASLE_OFFSET; opregion->asle->ardy = ASLE_ARDY_NOT_READY; } if (mboxes & MBOX_ASLE_EXT) - DRM_DEBUG_DRIVER("ASLE extension supported\n"); + drm_dbg(&dev_priv->drm, "ASLE extension supported\n"); if (intel_load_vbt_firmware(dev_priv) == 0) goto out; @@ -995,12 +1014,14 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) vbt = opregion->rvda; vbt_size = opregion->asle->rvds; if (intel_bios_is_valid_vbt(vbt, vbt_size)) { - DRM_DEBUG_KMS("Found valid VBT in ACPI OpRegion (RVDA)\n"); + drm_dbg_kms(&dev_priv->drm, + "Found valid VBT in ACPI OpRegion (RVDA)\n"); opregion->vbt = vbt; opregion->vbt_size = vbt_size; goto out; } else { - DRM_DEBUG_KMS("Invalid VBT in ACPI OpRegion (RVDA)\n"); + drm_dbg_kms(&dev_priv->drm, + "Invalid VBT in ACPI OpRegion (RVDA)\n"); memunmap(opregion->rvda); opregion->rvda = NULL; } @@ -1018,11 +1039,13 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) OPREGION_ASLE_EXT_OFFSET : OPREGION_SIZE; vbt_size -= OPREGION_VBT_OFFSET; if (intel_bios_is_valid_vbt(vbt, vbt_size)) { - DRM_DEBUG_KMS("Found valid VBT in ACPI OpRegion (Mailbox #4)\n"); + drm_dbg_kms(&dev_priv->drm, + "Found valid VBT in ACPI OpRegion (Mailbox #4)\n"); opregion->vbt = vbt; opregion->vbt_size = vbt_size; } else { - DRM_DEBUG_KMS("Invalid VBT in ACPI OpRegion (Mailbox #4)\n"); + drm_dbg_kms(&dev_priv->drm, + "Invalid VBT in ACPI OpRegion (Mailbox #4)\n"); } out: @@ -1058,20 +1081,22 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv) ret = swsci(dev_priv, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details); if (ret) { - DRM_DEBUG_KMS("Failed to get panel details from OpRegion (%d)\n", - ret); + drm_dbg_kms(&dev_priv->drm, + "Failed to get panel details from OpRegion (%d)\n", + ret); return ret; } ret = (panel_details >> 8) & 0xff; if (ret > 0x10) { - DRM_DEBUG_KMS("Invalid OpRegion panel type 0x%x\n", ret); + drm_dbg_kms(&dev_priv->drm, + "Invalid OpRegion panel type 0x%x\n", ret); return -EINVAL; } /* fall back to VBT panel type? */ if (ret == 0x0) { - DRM_DEBUG_KMS("No panel type in OpRegion\n"); + drm_dbg_kms(&dev_priv->drm, "No panel type in OpRegion\n"); return -ENODEV; } @@ -1081,7 +1106,8 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv) * via a quirk list :( */ if (!dmi_check_system(intel_use_opregion_panel_type)) { - DRM_DEBUG_KMS("Ignoring OpRegion panel type (%d)\n", ret - 1); + drm_dbg_kms(&dev_priv->drm, + "Ignoring OpRegion panel type (%d)\n", ret - 1); return -ENODEV; } From patchwork Tue Jan 21 14:31:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wambui Karuga X-Patchwork-Id: 11344285 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A69A3109A for ; Tue, 21 Jan 2020 17:20:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8055624656 for ; Tue, 21 Jan 2020 17:20:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZDwNg6lk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8055624656 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5DB866EDE3; Tue, 21 Jan 2020 17:20:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by gabe.freedesktop.org (Postfix) with ESMTPS id C849E6ED28; Tue, 21 Jan 2020 14:32:22 +0000 (UTC) Received: by mail-wr1-x443.google.com with SMTP id z3so3472379wru.3; Tue, 21 Jan 2020 06:32:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=k3sVQxFN9Jt4vZYxvCH5I4zJetCqBCSztJTvthu9bDk=; b=ZDwNg6lkgAofDtTf4YmV3wzBHeoRWwk44Ita5Sw6pJugWuO+ycqpbPP8rQAsOtrRBX FA9mFeMkyW8OeEEYZ45mPf8Lw9m7SzUAVyRrLE9+FmJU+N9lHAU+9f1YqsNesWmbxG0k byes1QMC+z0zVhm5RurL/MO6DAkW5hSM5xJ39bNylC0dxHMLVOkpLEWfxeBBqoNvOrnw Ye6lCM4bdsrNkuctLS15yDWnhAqWabZgpRhIJA8qeZ6sHk2UYyu+br4CRoWzFC5+LJ94 8vmlzhFRsi97ONJqkBpMkOACxLZVw4DcmaXtA+wqtafh8oMXoX/hqTxUZpGkpi47NEqD bEjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=k3sVQxFN9Jt4vZYxvCH5I4zJetCqBCSztJTvthu9bDk=; b=JlWN/UYR0zVZSmKDWJEBwVkitCQeL6CDQwkcEgGAKTu5oYRTtrcKtzHBQ1YMbKdRV7 6AbZSDR8vCFRlXnwMwURT+bt1pjmbefOpzEmbgBSWsizNlJqiT9lKjZqH8MX1FmmdGXg GUj6cRVN92uq5RKQkKki/ztHF5wDMkUBPl+S27aJVfQs1TAPLoDicWSCY8KTN8wdONUy oKLprv13t9I1pfDsy89UbIeAeKHm4HFwina5HoUOnNLNuorVkXpycVeCLDrAgcKwlRh/ 9lecM9Q20ZHTe8T8ZW9G8Wkj6/K8e8Vx1gbBB4Vtw1rpUQDEy7+SEfKnNCiUyARbsIDv Xx7Q== X-Gm-Message-State: APjAAAWralvyvZfo3k0+PcZQE7Rz5vStoWAcgCESEWkIVR+7tiHhPrAX QIw+ocXGlQKjaTXs+ANyrA0= X-Google-Smtp-Source: APXvYqzdkYCRQpsDwAOkJcDDv5Rg9uCF5l895NTMvUl9TehindAQTkm+WcovDHuIwOCYso3EA42sCA== X-Received: by 2002:adf:e58b:: with SMTP id l11mr5559237wrm.402.1579617141285; Tue, 21 Jan 2020 06:32:21 -0800 (PST) Received: from localhost.localdomain ([197.254.95.38]) by smtp.googlemail.com with ESMTPSA id g2sm52781284wrw.76.2020.01.21.06.32.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2020 06:32:20 -0800 (PST) From: Wambui Karuga To: jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, airlied@linux.ie, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Tue, 21 Jan 2020 17:31:55 +0300 Message-Id: <20200121143155.20856-7-wambui.karugax@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200121143155.20856-1-wambui.karugax@gmail.com> References: <20200121143155.20856-1-wambui.karugax@gmail.com> X-Mailman-Approved-At: Tue, 21 Jan 2020 17:20:38 +0000 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/hdcp: conversion to struct drm_device based logging macros X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Converts various instances of the printk based logging macros in i915/display/intel_hdcp.c with the struct drm_device based macros using coccinelle. The script matches based on the existence of an existing struct drm_i915_private device: @rule1@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @rule2@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } New checkpatch warnings were addressed manually. Signed-off-by: Wambui Karuga --- drivers/gpu/drm/i915/display/intel_hdcp.c | 138 +++++++++++++--------- 1 file changed, 81 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 0fdbd39f6641..01acf6c5d04d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -217,8 +217,9 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1); if (ret) { - DRM_ERROR("Failed to initiate HDCP key load (%d)\n", - ret); + drm_err(&dev_priv->drm, + "Failed to initiate HDCP key load (%d)\n", + ret); return ret; } } else { @@ -245,7 +246,7 @@ static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text) { I915_WRITE(HDCP_SHA_TEXT, sha_text); if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { - DRM_ERROR("Timed out waiting for SHA1 ready\n"); + drm_err(&dev_priv->drm, "Timed out waiting for SHA1 ready\n"); return -ETIMEDOUT; } return 0; @@ -270,7 +271,8 @@ u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv, return HDCP_TRANSD_REP_PRESENT | HDCP_TRANSD_SHA1_M0; default: - DRM_ERROR("Unknown transcoder %d\n", cpu_transcoder); + drm_err(&dev_priv->drm, "Unknown transcoder %d\n", + cpu_transcoder); return -EINVAL; } } @@ -287,7 +289,7 @@ u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv, case PORT_E: return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; default: - DRM_ERROR("Unknown port %d\n", port); + drm_err(&dev_priv->drm, "Unknown port %d\n", port); return -EINVAL; } } @@ -762,25 +764,26 @@ static int _intel_hdcp_disable(struct intel_connector *connector) enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; - DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n", - connector->base.name, connector->base.base.id); + drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n", + connector->base.name, connector->base.base.id); hdcp->hdcp_encrypted = false; I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port), 0); if (intel_de_wait_for_clear(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port), ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { - DRM_ERROR("Failed to disable HDCP, timeout clearing status\n"); + drm_err(&dev_priv->drm, + "Failed to disable HDCP, timeout clearing status\n"); return -ETIMEDOUT; } ret = hdcp->shim->toggle_signalling(intel_dig_port, false); if (ret) { - DRM_ERROR("Failed to disable HDCP signalling\n"); + drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n"); return ret; } - DRM_DEBUG_KMS("HDCP is disabled\n"); + drm_dbg_kms(&dev_priv->drm, "HDCP is disabled\n"); return 0; } @@ -790,11 +793,11 @@ static int _intel_hdcp_enable(struct intel_connector *connector) struct drm_i915_private *dev_priv = connector->base.dev->dev_private; int i, ret, tries = 3; - DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n", - connector->base.name, connector->base.base.id); + drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being enabled...\n", + connector->base.name, connector->base.base.id); if (!hdcp_key_loadable(dev_priv)) { - DRM_ERROR("HDCP key Load is not possible\n"); + drm_err(&dev_priv->drm, "HDCP key Load is not possible\n"); return -ENXIO; } @@ -805,7 +808,8 @@ static int _intel_hdcp_enable(struct intel_connector *connector) intel_hdcp_clear_keys(dev_priv); } if (ret) { - DRM_ERROR("Could not load HDCP keys, (%d)\n", ret); + drm_err(&dev_priv->drm, "Could not load HDCP keys, (%d)\n", + ret); return ret; } @@ -817,13 +821,14 @@ static int _intel_hdcp_enable(struct intel_connector *connector) return 0; } - DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret); + drm_dbg_kms(&dev_priv->drm, "HDCP Auth failure (%d)\n", ret); /* Ensuring HDCP encryption and signalling are stopped. */ _intel_hdcp_disable(connector); } - DRM_DEBUG_KMS("HDCP authentication failed (%d tries/%d)\n", tries, ret); + drm_dbg_kms(&dev_priv->drm, + "HDCP authentication failed (%d tries/%d)\n", tries, ret); return ret; } @@ -854,10 +859,11 @@ static int intel_hdcp_check_link(struct intel_connector *connector) } if (WARN_ON(!intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) { - DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n", - connector->base.name, connector->base.base.id, - I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, - port))); + drm_err(&dev_priv->drm, + "%s:%d HDCP link stopped encryption,%x\n", + connector->base.name, connector->base.base.id, + I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, + port))); ret = -ENXIO; hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); @@ -872,12 +878,13 @@ static int intel_hdcp_check_link(struct intel_connector *connector) goto out; } - DRM_DEBUG_KMS("[%s:%d] HDCP link failed, retrying authentication\n", - connector->base.name, connector->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "[%s:%d] HDCP link failed, retrying authentication\n", + connector->base.name, connector->base.base.id); ret = _intel_hdcp_disable(connector); if (ret) { - DRM_ERROR("Failed to disable hdcp (%d)\n", ret); + drm_err(&dev_priv->drm, "Failed to disable hdcp (%d)\n", ret); hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); goto out; @@ -885,7 +892,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) ret = _intel_hdcp_enable(connector); if (ret) { - DRM_ERROR("Failed to enable hdcp (%d)\n", ret); + drm_err(&dev_priv->drm, "Failed to enable hdcp (%d)\n", ret); hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); goto out; @@ -944,7 +951,8 @@ hdcp2_prepare_ake_init(struct intel_connector *connector, ret = comp->ops->initiate_hdcp2_session(comp->mei_dev, data, ake_data); if (ret) - DRM_DEBUG_KMS("Prepare_ake_init failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -974,7 +982,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, rx_cert, paired, ek_pub_km, msg_sz); if (ret < 0) - DRM_DEBUG_KMS("Verify rx_cert failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Verify rx_cert failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -998,7 +1007,7 @@ static int hdcp2_verify_hprime(struct intel_connector *connector, ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime); if (ret < 0) - DRM_DEBUG_KMS("Verify hprime failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Verify hprime failed. %d\n", ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1023,7 +1032,8 @@ hdcp2_store_pairing_info(struct intel_connector *connector, ret = comp->ops->store_pairing_info(comp->mei_dev, data, pairing_info); if (ret < 0) - DRM_DEBUG_KMS("Store pairing info failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Store pairing info failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1048,7 +1058,8 @@ hdcp2_prepare_lc_init(struct intel_connector *connector, ret = comp->ops->initiate_locality_check(comp->mei_dev, data, lc_init); if (ret < 0) - DRM_DEBUG_KMS("Prepare lc_init failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Prepare lc_init failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1073,7 +1084,8 @@ hdcp2_verify_lprime(struct intel_connector *connector, ret = comp->ops->verify_lprime(comp->mei_dev, data, rx_lprime); if (ret < 0) - DRM_DEBUG_KMS("Verify L_Prime failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Verify L_Prime failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1097,7 +1109,8 @@ static int hdcp2_prepare_skey(struct intel_connector *connector, ret = comp->ops->get_session_key(comp->mei_dev, data, ske_data); if (ret < 0) - DRM_DEBUG_KMS("Get session key failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Get session key failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1126,7 +1139,8 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, rep_topology, rep_send_ack); if (ret < 0) - DRM_DEBUG_KMS("Verify rep topology failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, + "Verify rep topology failed. %d\n", ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1151,7 +1165,7 @@ hdcp2_verify_mprime(struct intel_connector *connector, ret = comp->ops->verify_mprime(comp->mei_dev, data, stream_ready); if (ret < 0) - DRM_DEBUG_KMS("Verify mprime failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Verify mprime failed. %d\n", ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1174,7 +1188,8 @@ static int hdcp2_authenticate_port(struct intel_connector *connector) ret = comp->ops->enable_hdcp_authentication(comp->mei_dev, data); if (ret < 0) - DRM_DEBUG_KMS("Enable hdcp auth failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1536,8 +1551,9 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) if (hdcp->shim->toggle_signalling) { ret = hdcp->shim->toggle_signalling(intel_dig_port, true); if (ret) { - DRM_ERROR("Failed to enable HDCP signalling. %d\n", - ret); + drm_err(&dev_priv->drm, + "Failed to enable HDCP signalling. %d\n", + ret); return ret; } } @@ -1582,13 +1598,14 @@ static int hdcp2_disable_encryption(struct intel_connector *connector) LINK_ENCRYPTION_STATUS, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); if (ret == -ETIMEDOUT) - DRM_DEBUG_KMS("Disable Encryption Timedout"); + drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout"); if (hdcp->shim->toggle_signalling) { ret = hdcp->shim->toggle_signalling(intel_dig_port, false); if (ret) { - DRM_ERROR("Failed to disable HDCP signalling. %d\n", - ret); + drm_err(&dev_priv->drm, + "Failed to disable HDCP signalling. %d\n", + ret); return ret; } } @@ -1691,9 +1708,10 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) } if (WARN_ON(!intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) { - DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n", - I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, - port))); + drm_err(&dev_priv->drm, + "HDCP2.2 link stopped the encryption, %x\n", + I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, + port))); ret = -ENXIO; hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); @@ -1713,25 +1731,29 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) goto out; - DRM_DEBUG_KMS("HDCP2.2 Downstream topology change\n"); + drm_dbg_kms(&dev_priv->drm, + "HDCP2.2 Downstream topology change\n"); ret = hdcp2_authenticate_repeater_topology(connector); if (!ret) { hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; schedule_work(&hdcp->prop_work); goto out; } - DRM_DEBUG_KMS("[%s:%d] Repeater topology auth failed.(%d)\n", - connector->base.name, connector->base.base.id, - ret); + drm_dbg_kms(&dev_priv->drm, + "[%s:%d] Repeater topology auth failed.(%d)\n", + connector->base.name, connector->base.base.id, + ret); } else { - DRM_DEBUG_KMS("[%s:%d] HDCP2.2 link failed, retrying auth\n", - connector->base.name, connector->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "[%s:%d] HDCP2.2 link failed, retrying auth\n", + connector->base.name, connector->base.base.id); } ret = _intel_hdcp2_disable(connector); if (ret) { - DRM_ERROR("[%s:%d] Failed to disable hdcp2.2 (%d)\n", - connector->base.name, connector->base.base.id, ret); + drm_err(&dev_priv->drm, + "[%s:%d] Failed to disable hdcp2.2 (%d)\n", + connector->base.name, connector->base.base.id, ret); hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); goto out; @@ -1739,9 +1761,10 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) ret = _intel_hdcp2_enable(connector); if (ret) { - DRM_DEBUG_KMS("[%s:%d] Failed to enable hdcp2.2 (%d)\n", - connector->base.name, connector->base.base.id, - ret); + drm_dbg_kms(&dev_priv->drm, + "[%s:%d] Failed to enable hdcp2.2 (%d)\n", + connector->base.name, connector->base.base.id, + ret); hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); goto out; @@ -1772,7 +1795,7 @@ static int i915_hdcp_component_bind(struct device *i915_kdev, { struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); - DRM_DEBUG("I915 HDCP comp bind\n"); + drm_dbg(&dev_priv->drm, "I915 HDCP comp bind\n"); mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data; dev_priv->hdcp_master->mei_dev = mei_kdev; @@ -1786,7 +1809,7 @@ static void i915_hdcp_component_unbind(struct device *i915_kdev, { struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); - DRM_DEBUG("I915 HDCP comp unbind\n"); + drm_dbg(&dev_priv->drm, "I915 HDCP comp unbind\n"); mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv->hdcp_master = NULL; mutex_unlock(&dev_priv->hdcp_comp_mutex); @@ -1854,7 +1877,7 @@ static inline int initialize_hdcp_port_data(struct intel_connector *connector, sizeof(struct hdcp2_streamid_type), GFP_KERNEL); if (!data->streams) { - DRM_ERROR("Out of Memory\n"); + drm_err(&dev_priv->drm, "Out of Memory\n"); return -ENOMEM; } @@ -1888,7 +1911,8 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv) ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops, I915_COMPONENT_HDCP); if (ret < 0) { - DRM_DEBUG_KMS("Failed at component add(%d)\n", ret); + drm_dbg_kms(&dev_priv->drm, "Failed at component add(%d)\n", + ret); mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv->hdcp_comp_added = false; mutex_unlock(&dev_priv->hdcp_comp_mutex);