From patchwork Fri Jan 24 22:42:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351179 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C24AB921 for ; Fri, 24 Jan 2020 22:43:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A0F4A2071E for ; Fri, 24 Jan 2020 22:43:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="cL6KsxWn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387398AbgAXWnS (ORCPT ); Fri, 24 Jan 2020 17:43:18 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:44974 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729186AbgAXWnR (ORCPT ); Fri, 24 Jan 2020 17:43:17 -0500 Received: by mail-pf1-f195.google.com with SMTP id 62so1782948pfu.11 for ; Fri, 24 Jan 2020 14:43:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aUtLqcv/Vq5O1yPHr9lwO+Q2UaRXNLbVqC9iz4yzAPg=; b=cL6KsxWn65i8MFgUEzTp+bXeafZ/i2X7w0dWVLte1h4a9phyM7AkaNYA76gqLq3hdV sfTSY+rfJud6zwRGnrv6x3KeCEgrwx4OFCja6jk6Z3YhXkdDRd0ZCzFzBL61D8l8r4GI L2yxfewfPBbhLFhiBN7XwL6Bp+fSwrYzQTqIg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aUtLqcv/Vq5O1yPHr9lwO+Q2UaRXNLbVqC9iz4yzAPg=; b=ZrI4WXzWklkiUo3sAv+RAsdodjgfg3BnZNRwu5oEhznQBZqJm5qWzm3BytxCdXICz+ 73uQd6EmqZXY6t2g3KrvO+2eCRva6tj6OG2zLjTgBMDT3sBqJWS4WHgU0OsYgkmT6kXC zfe+eMtJo0qyW6tqZ3am8Hjyb85LbYzvCakcR1jeLMGVMcTi0AVpNH2alkt5s6cKVkay OGDvUwPEcXdqRxrTPkHlRM197zJZsJ23S1ZCxmjrlbS2CaoioMNcIwJdimXBCuh2rFSP 8TrcbfMdJ92Oha6qv8a0klW1jZY1+dMJzPcpHo2IX4IXKZ0+2AKasZg8FhCZ7EpkmSFm L51w== X-Gm-Message-State: APjAAAUkbx82d3bhOLrdCA/XiVrJa40+Ub83Lcuer1Y3X7yCCjMBoL7V TqFUJKiqd1TA6y7NryGDy7vZ2Q== X-Google-Smtp-Source: APXvYqz/yZrIXvlaesHWaGFX+hjcycDFPTVmoM0llXD8iTg1khhXkmxb5j/IXoOJGvU5uVMlzcYJSg== X-Received: by 2002:a63:e954:: with SMTP id q20mr6967695pgj.204.1579905796900; Fri, 24 Jan 2020 14:43:16 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:16 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v2 01/10] clk: qcom: rcg2: Don't crash if our parent can't be found; return an error Date: Fri, 24 Jan 2020 14:42:16 -0800 Message-Id: <20200124144154.v2.1.I7487325fe8e701a68a07d3be8a6a4b571eca9cfa@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When I got my clock parenting slightly wrong I ended up with a crash that looked like this: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 ... pc : clk_hw_get_rate+0x14/0x44 ... Call trace: clk_hw_get_rate+0x14/0x44 _freq_tbl_determine_rate+0x94/0xfc clk_rcg2_determine_rate+0x2c/0x38 clk_core_determine_round_nolock+0x4c/0x88 clk_core_round_rate_nolock+0x6c/0xa8 clk_core_round_rate_nolock+0x9c/0xa8 clk_core_set_rate_nolock+0x70/0x180 clk_set_rate+0x3c/0x6c of_clk_set_defaults+0x254/0x360 platform_drv_probe+0x28/0xb0 really_probe+0x120/0x2dc driver_probe_device+0x64/0xfc device_driver_attach+0x4c/0x6c __driver_attach+0xac/0xc0 bus_for_each_dev+0x84/0xcc driver_attach+0x2c/0x38 bus_add_driver+0xfc/0x1d0 driver_register+0x64/0xf8 __platform_driver_register+0x4c/0x58 msm_drm_register+0x5c/0x60 ... It turned out that clk_hw_get_parent_by_index() was returning NULL and we weren't checking. Let's check it so that we don't crash. Fixes: ac269395cdd8 ("clk: qcom: Convert to clk_hw based provider APIs") Signed-off-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke --- I haven't gone back and tried to reproduce this same crash on older kernels, but I'll put the blame on commit ac269395cdd8 ("clk: qcom: Convert to clk_hw based provider APIs"). Before that if we got a NULL parent back it was fine and dandy since a NULL "struct clk" is valid to use but a NULL "struct clk_hw" is not. Changes in v2: - Patch ("clk: qcom: rcg2: Don't crash...") new for v2. drivers/clk/qcom/clk-rcg2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index da045b200def..9098001ac805 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -218,6 +218,9 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, clk_flags = clk_hw_get_flags(hw); p = clk_hw_get_parent_by_index(hw, index); + if (!p) + return -EINVAL; + if (clk_flags & CLK_SET_RATE_PARENT) { rate = f->freq; if (f->pre_div) { From patchwork Fri Jan 24 22:42:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351183 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 41C1A184C for ; Fri, 24 Jan 2020 22:43:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 20DC02071E for ; Fri, 24 Jan 2020 22:43:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="DH4yPU/+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387404AbgAXWnT (ORCPT ); Fri, 24 Jan 2020 17:43:19 -0500 Received: from mail-pj1-f66.google.com ([209.85.216.66]:35045 "EHLO mail-pj1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387402AbgAXWnS (ORCPT ); Fri, 24 Jan 2020 17:43:18 -0500 Received: by mail-pj1-f66.google.com with SMTP id q39so474523pjc.0 for ; Fri, 24 Jan 2020 14:43:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XUY8OKSzBPGKXsy9C12HX4Zd6On+8bszenkjFTAhVcw=; b=DH4yPU/+4ENvZ1SHdmkXG/qDzhONJtANeKgsBWF2MKama9XzUmkblLRrT/cItCZKj8 8Y2BMYOHgoRy5Bf8ONQUvRQ9k0wgYTzO7ax770GkY60FXeHJNdvANDEoCA0UBkaZmXuq QICm4GNs/WQDglT6iZ7Ib965Jp/q1Yqp5t0JY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XUY8OKSzBPGKXsy9C12HX4Zd6On+8bszenkjFTAhVcw=; b=Tkb3PcXzdYJ+0cbTv+ptmtIfOpwZFHQljt9xwlYtjLU1CRsM9laFfhBcvmpdiFG1GH evcnOTVarGApUZGY/qoxr5nT1Xycbt/ZYpO64iK5WSiLKbdapUwxiugvQQEMIwEYqv4n x/bjGaq4m6pyXpq3JdZHThJDHOgZG8TWNmgIyOXtp1u0QlwDZef+gzwMGrAAOrOSik5r cndMzQeFs2zfAdeAAFp51L8VN69K+bBt2OPG9mx+sQPpA8bBwQsYuYIeM1SjxDrQ8b2e gOhcfqZTA2VdHf0I2PGmd58TOchuQh5PNEyZqhOa8YbSknnvDtv+wqDzdxvKnwTvuLEH ZnHA== X-Gm-Message-State: APjAAAVzQhhhnngKCYL1E+CI60gHCA4BB1FiXKofbcSNw/Nh07qRhNTp STdtNptTy7yiiceCnkbDR8vzog== X-Google-Smtp-Source: APXvYqx5KfK3OEW+qx8AJSVzFCWaLqn2Fo+x2QCA7ODGdtOJTbEJkWdllo7poK33dXuSQDkC1pMurw== X-Received: by 2002:a17:90b:342:: with SMTP id fh2mr1666659pjb.23.1579905797991; Fri, 24 Jan 2020 14:43:17 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:17 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v2 02/10] dt-bindings: clock: Fix qcom,dispcc bindings for sdm845/sc7180 Date: Fri, 24 Jan 2020 14:42:17 -0800 Message-Id: <20200124144154.v2.2.I0c4bbb0f75a0880cd4bd90d8b267271e2375e0d0@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The qcom,dispcc bindings had a few problems with them: 1. They didn't specify all the clocks that dispcc is a client of. Specifically on sc7180 there are two clocks from the DSI PHY and two from the DP PHY. On sdm845 there are actually two DSI PHYs (each of which has two clocks). These all need to be specified. 2. The sdm845.dtsi has existed for quite some time without specifying the clocks. The Linux driver was relying on global names to match things up. While we should transition things, it should be noted in the bindings. NOTE: It may be slightly controversial that I didn't re-order the clocks and name the "DSI" clocks on sc7180 to "dsi0". That would have allowed me to have a single table and just use minItems/maxItems to specify that sc7180 only had one DSI PHY. I almost did that, but it felt a little weird. Why did the DSI clock have a 0 but not the DP clock? If we add a SoC that has a 2nd DP port then we can't retroactively name old ones. What if we have a SoC that has HDMI but only one DSI lane? It felt cleaner to me to just duplicate. Also note that I updated the example. Fixes: 5d28e44ba630 ("dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings") Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("dt-bindings: clock: Fix qcom,dispcc...") new for v2. .../bindings/clock/qcom,dispcc.yaml | 87 +++++++++++++++---- 1 file changed, 71 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml index 9c58e02a1de1..560c52ce3da5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml @@ -19,18 +19,6 @@ properties: - qcom,sc7180-dispcc - qcom,sdm845-dispcc - clocks: - minItems: 1 - maxItems: 2 - items: - - description: Board XO source - - description: GPLL0 source from GCC - - clock-names: - items: - - const: xo - - const: gpll0 - '#clock-cells': const: 1 @@ -52,16 +40,83 @@ required: - '#reset-cells' - '#power-domain-cells' +if: + properties: + compatible: + contains: + const: qcom,sc7180-dispcc +then: + properties: + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: xo + - const: gpll0 + - const: dsi_phy_pll_byte + - const: dsi_phy_pll_pixel + - const: dp_phy_pll_link + - const: dp_phy_pll_vco_div + +else: + if: + # NOTE: sdm845.dtsi existed for quite some time and specified no clocks. + # The code had to use hardcoded mechanisms to find the input clocks. + # Any sdm845 device trees should be transitioned, but actual code may + # need to handle old dts files. + properties: + compatible: + contains: + const: qcom,sdm845-dispcc + then: + properties: + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: xo + - const: gpll0 + - const: dsi0_phy_pll_byte + - const: dsi0_phy_pll_pixel + - const: dsi1_phy_pll_byte + - const: dsi1_phy_pll_pixel + - const: dp_phy_pll_link + - const: dp_phy_pll_vco_div + examples: # Example of DISPCC with clock node properties for SDM845: - | + #include + #include clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; - reg = <0xaf00000 0x10000>; - clocks = <&rpmhcc 0>, <&gcc 24>; - clock-names = "xo", "gpll0"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&dsi0_phy 0>, <&dsi0_phy 1>, + <&dsi1_phy 0>, <&dsi1_phy 1>, + <&dp_phy 0>, <&dp_phy 1>; + clock-names = "xo", "gpll0", + "dsi0_phy_pll_byte", "dsi0_phy_pll_pixel", + "dsi1_phy_pll_byte", "dsi1_phy_pll_pixel", + "dp_phy_pll_link", "dp_phy_pll_vco_div"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - }; + }; ... From patchwork Fri Jan 24 22:42:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351215 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0AC8139A for ; Fri, 24 Jan 2020 22:43:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CF5E92087E for ; Fri, 24 Jan 2020 22:43:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="H5M3q6aW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387406AbgAXWnT (ORCPT ); Fri, 24 Jan 2020 17:43:19 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:38959 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387407AbgAXWnT (ORCPT ); Fri, 24 Jan 2020 17:43:19 -0500 Received: by mail-pf1-f196.google.com with SMTP id q10so1798945pfs.6 for ; Fri, 24 Jan 2020 14:43:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LCy4d/uPw5BLn8Wtp8APLodtLD4pO2HOn2Pu/h6vPEQ=; b=H5M3q6aWRWGz+DPDkuDKKDp9JmGrdLbld1dKDiQUVp3fn2wQvRevBwkem3NygaawT/ eRqCOrI1rSecV50Rs2vF8UXdyTv1JEJ7vAaCBQYa2uM9shXTNvrJdFW2lmTnxJhaDWot dLWxiqt3t4KkiP56kPl5Abs3KcMMZPahXAbfo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LCy4d/uPw5BLn8Wtp8APLodtLD4pO2HOn2Pu/h6vPEQ=; b=rvYVoW4ibbwydaoq87MlSEnqljYsu+em2vpEpHJq2PzT0FxDq2OP8AoGvpVil1Ia8c vyr/h4gHpkNs/MQ/cT5EemlC5GAdGNza2ttKB4U1DzikLMRK7/XbEqAZtdWzmB5ky1KM KfVfZh9dZlvJZpi1GFwO+gtCgeK1QTAkL/dSTX1/Xw4873qKswhzO/Xpg2t2bwkTMEVM cO6jomoO8A7IM910UfvpQF+Gl7enQDvkDR5n99oK0SyLafRa+A/6uFCYH1Py5NEGYAF+ gk3i22Lj7dFP+72JGHcpLxbWyJRNChlGI58tZThQ1RYco/jA32wUQScb0PXgZN0+VTcn 0tGg== X-Gm-Message-State: APjAAAViZ/oNohJxIBynSj1YBZzZ9qI4Ji8fuoIBvahJu94SFyaXAO/5 xw5OZRUSe7xha8q1mO8zHUw7Rw== X-Google-Smtp-Source: APXvYqwqOj229OreenHXwJi4oidfVVbTHzeOfUUBBvLdizzGOX34wX6hYI9c93bqiOm2N75XvR3FNg== X-Received: by 2002:a63:5818:: with SMTP id m24mr6680605pgb.358.1579905799008; Fri, 24 Jan 2020 14:43:19 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:18 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 03/10] arm64: dts: qcom: sdm845: Add the missing clocks on the dispcc Date: Fri, 24 Jan 2020 14:42:18 -0800 Message-Id: <20200124144154.v2.3.Ie80fa74e1774f4317d80d70d30ef4b78f16cc8df@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We're transitioning over to requiring the Qualcomm Display Clock Controller to specify all the input clocks. Let's add them for sdm845. NOTES: - Until the Linux driver for sdm845's dispcc is updated, these clocks will not actually be used in Linux. It will continue to use global clock names to match things up. - Although the clocks from the DP PHY are required, the DP PHY isn't represented in the dts yet. Apparently the magic for this is just to use <0>. Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("arm64: dts: qcom: sdm845: Add...dispcc") new for v2. arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d42302b8889b..01354533a61b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2933,6 +2933,18 @@ opp-200000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <0>, + <0>; + clock-names = "xo", "gpll0", + "dsi0_phy_pll_byte", "dsi0_phy_pll_pixel", + "dsi1_phy_pll_byte", "dsi1_phy_pll_pixel", + "dp_phy_pll_link", "dp_phy_pll_vco_div"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Fri Jan 24 22:42:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351185 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C1271398 for ; Fri, 24 Jan 2020 22:43:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4B7E12071E for ; Fri, 24 Jan 2020 22:43:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="W+AWfGtY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387400AbgAXWnV (ORCPT ); Fri, 24 Jan 2020 17:43:21 -0500 Received: from mail-pf1-f176.google.com ([209.85.210.176]:37525 "EHLO mail-pf1-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387425AbgAXWnU (ORCPT ); Fri, 24 Jan 2020 17:43:20 -0500 Received: by mail-pf1-f176.google.com with SMTP id p14so1801109pfn.4 for ; Fri, 24 Jan 2020 14:43:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fR36UAT87Z0TKgzJqLSUdRVGW5KC0xvFs4pz6EoaSEs=; b=W+AWfGtYERngYx58+JdIqakd2DAkpetfVaeID9hwBCBbON7jnjF1idcPZDN1OLhN3w 622xZcGgQxsvPHvZRkgWq4dOLsTOXwAZNJpdMf7SjRPUPWSR5XzyvfIPtF37IF8PcLyF eG2poAj44PWrspC186mA54CivpdLZzf8SEW8k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fR36UAT87Z0TKgzJqLSUdRVGW5KC0xvFs4pz6EoaSEs=; b=pjD9rlfIB96TsurtP0sBapMTwsF8MiHsd4wW5PzKvCXDqNNHRU3ytUccvY3l8V0UfL lhHoDzUnZpvkCDSrNEgFWbde6w+CTCw30GaUS7wWw5HXmBpeg4DXRJgGWrHscRxYwCBz qJMt3yYj8zbG8QaGjA01pRAVOtbHxMe0hEoz+zgn8DzDLCCPC7b+u29PxJg8Br8UkFxp 8fj0dsYgfOumhfEJr4VGkkH7q2IqUhhvyWy+6geREntBrkInkHj78GN2JrqAWKcz6xy6 qNUgr32YyvZ1vY/gYxWf6qe3LLiK0jZRw3l3rKklp2CUaI7Pq2JUUoLFAn6iUjMg+5jA B12Q== X-Gm-Message-State: APjAAAUf8BzT8cKydfAAAuY42psSp92qQOTxte1vwlWqpiCjGlDpe/tg 836C9ta4VyetGqJqV0t8wjUJBw== X-Google-Smtp-Source: APXvYqzQWhWF4MQsZ7Z+9Immx0ruH/IjtEERzHTTTIJYCcURTdVPjfvN5BCLXulZMP1xLv21An1JIQ== X-Received: by 2002:a63:1a19:: with SMTP id a25mr6709867pga.447.1579905800195; Fri, 24 Jan 2020 14:43:20 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:19 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v2 04/10] dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998 Date: Fri, 24 Jan 2020 14:42:19 -0800 Message-Id: <20200124144154.v2.4.I513cd73b16665065ae6c22cf594d8b543745e28c@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The qcom,dispcc bindings had a few problems with them: 1. When things were converted to yaml the name of the "gpll0 main" clock got changed from "gpll0" to "gpll0_main". Change it back. 2. The bindings are written so that new boards don't have to specify all the clocks. That doesn't really make sense. Make it so that on new boards all 3 clocks are required. This also updates the example to be sc7180 and use symbolic names for clock indicies. NOTE: It seems that we can only make things _more_ restrictive in the per-SoC overrides for minItems/maxItems. ...so by default we start out with a loose min=2, max=3 (implicit). Then we restrict msm8998 to exactly 2 and everything else to exactly 3. Fixes: 5c6f3a36b913 ("dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings") Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("dt-bindings: clock: Fix qcom,gpucc...") new for v2. .../devicetree/bindings/clock/qcom,gpucc.yaml | 42 ++++++++++++++----- 1 file changed, 31 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 622845aa643f..64cf3c450325 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -21,19 +21,17 @@ properties: - qcom,sdm845-gpucc clocks: - minItems: 1 - maxItems: 3 + minItems: 2 items: - description: Board XO source - - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src) - - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src) + - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src) + - description: GPLL0 div branch source (gcc_gpu_gpll0_div_clk_src) clock-names: - minItems: 1 - maxItems: 3 + minItems: 2 items: - const: xo - - const: gpll0_main + - const: gpll0 - const: gpll0_div '#clock-cells': @@ -57,16 +55,38 @@ required: - '#reset-cells' - '#power-domain-cells' +if: + properties: + compatible: + contains: + const: qcom,msm8998-gpucc +then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 +else: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + examples: # Example of GPUCC with clock node properties for SDM845: - | + #include + #include clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; - reg = <0x5090000 0x9000>; - clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>; - clock-names = "xo", "gpll0_main", "gpll0_div"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "xo", "gpll0", "gpll0_div"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - }; + }; ... From patchwork Fri Jan 24 22:42:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351213 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97D34921 for ; Fri, 24 Jan 2020 22:43:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 62CB22075D for ; Fri, 24 Jan 2020 22:43:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="V2NA5DrG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387559AbgAXWnx (ORCPT ); Fri, 24 Jan 2020 17:43:53 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:34496 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387435AbgAXWnW (ORCPT ); Fri, 24 Jan 2020 17:43:22 -0500 Received: by mail-pf1-f196.google.com with SMTP id i6so1810593pfc.1 for ; Fri, 24 Jan 2020 14:43:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WwMmfsPkXdXCpaGsa/Vhjbeiu4wcqbZZLVDwLapzju4=; b=V2NA5DrGCfEhQgH9jV86zkbxJnkeRBelGIWAFB97cPgMuGMopB1kx/VIBF3t8ZswoL XVlURC/Q7V2+fK/5NFs18VgfPm0YfDfIZql6rDGJCazPqE9rjkLyMi2Os7KONIl49Wop VsfQ5cOrJMXbbi0CifDItHNoEiHEiZAoKp2MA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WwMmfsPkXdXCpaGsa/Vhjbeiu4wcqbZZLVDwLapzju4=; b=IlvjmBTg1eHExeAdh7C6Sdli1UjIYue2DFdqeY2+vnjtc2qyMlyfaPp3Vk5RtqDR5s 9DJhUpzGho6Me2ciP3mpEHWghDdxlIGfSU5YkQw2wao+DoYQPpylLZwdbuokWFoCrFOx V0Y0k1cL/lAyT1uhtbisnZw3IwzX2OMWhAukZ/9hOSAR59bXIoMtL74+lmtxEGbE+IEo H8FRWFh0yZYxsgYqQxpmTqPynNfxjuebD269nTYNMSFdapu2txcMtkdvMPZVRlk4W4o8 sShELyGODE4RcFwp6yOIbe5pLGN9YiTOy8PhU2SeQkLCG09RkuSQ450pjdI8EZd9ksAp jm0g== X-Gm-Message-State: APjAAAXYz+QeOFABpo31n4+D+JBzIT33fuoqI9mgXrJ0lZCGgTt34+HW WpsXtrHdL5Wa6DW0UgVzsfgW8g== X-Google-Smtp-Source: APXvYqz09IB9wjq2TIbSib3i7IBWc2d69f4jcnNd7AKOKXWKfAq7g+mY64Cbl3ttZtEXDtRT6EGNZg== X-Received: by 2002:aa7:864a:: with SMTP id a10mr5567180pfo.233.1579905801319; Fri, 24 Jan 2020 14:43:21 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:20 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v2 05/10] clk: qcom: Fix sc7180 dispcc parent data Date: Fri, 24 Jan 2020 14:42:20 -0800 Message-Id: <20200124144154.v2.5.If590c468722d2985cea63adf60c0d2b3098f37d9@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The bindings file (qcom,dispcc.yaml) says that the two clocks that dispcc is a client of are named "xo" and "gpll0". That means we have to refer to them by those names. We weren't referring to "xo" properly in the driver. Then, in the patch ("dt-bindings: clock: Fix qcom,dispcc bindings for sdm845/sc7180") we clarify the names for all of the clocks that we are a client of. Fix all those too, also getting rid of the "fallback" names for them. Since sc7180 is still in infancy there is no reason to specify a fallback name. People should just get the device tree right. Since we didn't add the "test" clock to the bindings (apparently it's never used), kill it from the driver. If someone has a use for it we should add it to the bindings and bring it back. Instead of updating all of the sizes of the arrays now that the test clock is gone, switch to using the less error-prone ARRAY_SIZE. Not sure why it didn't always use that. Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180") Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("clk: qcom: Fix sc7180 dispcc parent data") new for v2. drivers/clk/qcom/dispcc-sc7180.c | 63 ++++++++++++-------------------- 1 file changed, 24 insertions(+), 39 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 30c1e25d3edb..380eca3f847d 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -43,7 +43,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_pll0", .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", + .fw_name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, @@ -76,40 +76,32 @@ static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = { static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_0[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, }; static const struct parent_map disp_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_DP_PHY_PLL_LINK_CLK, 1 }, { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_1[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" }, - { .fw_name = "dp_phy_pll_vco_div_clk", - .name = "dp_phy_pll_vco_div_clk"}, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, + { .fw_name = "dp_phy_pll_link" }, + { .fw_name = "dp_phy_pll_vco_div" }, }; static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_2[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "dsi0_phy_pll_out_byteclk", - .name = "dsi0_phy_pll_out_byteclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, + { .fw_name = "dsi_phy_pll_byte" }, }; static const struct parent_map disp_cc_parent_map_3[] = { @@ -117,40 +109,33 @@ static const struct parent_map disp_cc_parent_map_3[] = { { P_DISP_CC_PLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 4 }, { P_DISP_CC_PLL0_OUT_EVEN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_3[] = { - { .fw_name = "bi_tcxo" }, + { .fw_name = "xo" }, { .hw = &disp_cc_pll0.clkr.hw }, - { .fw_name = "gcc_disp_gpll0_clk_src" }, + { .fw_name = "gpll0" }, { .hw = &disp_cc_pll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 4 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_4[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "gcc_disp_gpll0_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, + { .fw_name = "gpll0" }, }; static const struct parent_map disp_cc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_5[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "dsi0_phy_pll_out_dsiclk", - .name = "dsi0_phy_pll_out_dsiclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, + { .fw_name = "dsi_phy_pll_pixel" }, }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { @@ -169,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk_src", .parent_data = disp_cc_parent_data_4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -183,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -203,7 +188,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_aux_clk_src", .parent_data = disp_cc_parent_data_0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -216,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -230,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -244,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, @@ -259,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -282,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -295,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_5, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -310,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -324,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .parent_data = disp_cc_parent_data_0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; From patchwork Fri Jan 24 22:42:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351207 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CD75921 for ; Fri, 24 Jan 2020 22:43:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4BD8521556 for ; Fri, 24 Jan 2020 22:43:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="jShQ2pX8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387459AbgAXWno (ORCPT ); Fri, 24 Jan 2020 17:43:44 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:33704 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387445AbgAXWnX (ORCPT ); Fri, 24 Jan 2020 17:43:23 -0500 Received: by mail-pg1-f195.google.com with SMTP id 6so1864392pgk.0 for ; Fri, 24 Jan 2020 14:43:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9BRqMxL/+QF9fXGxsodaUnU1nURwqkQVRb7Veb8jqnw=; b=jShQ2pX8IQIHGNrvrIOhAsqUK/C01VqaM9/g6/e7k6X2Xc4duWVu1GLO4DYADKLj8h DB1G4XhIeSlzDcjW5h0qV2Ri0rmkCIl/+sDXQ/FYpddk2u405IOAnDMRnaomXKuXhIYv rlfKquY9Gm+95wPB7AhitjDpdpTbpS0Fl/u1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9BRqMxL/+QF9fXGxsodaUnU1nURwqkQVRb7Veb8jqnw=; b=tjjwagdwdP3o9pDcVFTpUHF9eLe4hjhkU7rYYCbWVqYQJ/fsSeOIvm0xtQGKLoPDvQ YIbkYlmGx2MOUm2u5L+oOIV5olTYCKHfhKkdW3if++2R8lrHXi914zxBVH7Hg2OQ9eCb Ng1aU4HGQ2XdVrILiGWnwufuRnqRiJrRhQq0yx4hF6N9gn/LGg9f7h/OtarjqgXHS+01 b13OpkwYNU6xDW5+ibTZnXrjujclKxecX4lERIPLR77qXao86Ah2kSUssotBzG9uVsZw AiH711pSCEWyGvvWx07V71D1VnSZOMVx5FanQeHjsC3EEYF6Sa/Ud8OIjIfrUjMvVeH8 vlsA== X-Gm-Message-State: APjAAAWl9zOiZzN4lSUL8IAPA9S2/Kc2z6bME7/Vin0W1r9I9RDpR/47 6daNIc+5OqOmPfXkFqqkpSlZqg== X-Google-Smtp-Source: APXvYqwyIr9Hzf7MUy0r0DgFSN19tETtctZT8PEgdV9N562GI+cGiutgSkgp4ilXhVm9KOMG0sXfvw== X-Received: by 2002:aa7:928b:: with SMTP id j11mr5412125pfa.176.1579905802569; Fri, 24 Jan 2020 14:43:22 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:21 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 06/10] arm64: dts: qcom: sdm845: Add the missing clocks on the gpucc Date: Fri, 24 Jan 2020 14:42:21 -0800 Message-Id: <20200124144154.v2.6.If8596faf02408cef4bb9f52296b911eb9ba49287@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We're transitioning over to requiring the Qualcomm GPU Clock Controller to specify all the input clocks. Let's add them for sdm845. NOTE: Until the Linux driver for sdm845's gpucc is updated, these clocks will not actually be used in Linux. It will continue to use global clock names to match things up. Of course, Linux didn't use the old "xo" clock anyway. Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("arm64: dts: qcom: sdm845: Add...gpucc") new for v2. arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 01354533a61b..e624c91dbd6d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1903,8 +1903,10 @@ gpucc: clock-controller@5090000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "xo", "gpll0", "gpll0_div"; }; stm@6002000 { From patchwork Fri Jan 24 22:42:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351201 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 64CC6921 for ; Fri, 24 Jan 2020 22:43:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 42DD22071E for ; Fri, 24 Jan 2020 22:43:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="MDjGZDMX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387532AbgAXWnk (ORCPT ); Fri, 24 Jan 2020 17:43:40 -0500 Received: from mail-pl1-f194.google.com ([209.85.214.194]:43543 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387462AbgAXWnY (ORCPT ); Fri, 24 Jan 2020 17:43:24 -0500 Received: by mail-pl1-f194.google.com with SMTP id p23so1361385plq.10 for ; Fri, 24 Jan 2020 14:43:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=azOJGeenO90UDElVZnGvhTa1WOYkaMQED3kOM1E619Q=; b=MDjGZDMXlqXZUfV7OZldyntXHGM87aWp1WZpVtZvG3lp15ahEHyRkexF4mzQJ7dlAO x6rNvYucK03/VVjtUAEO2qx3vBAUWWaA+UmqKnUXMcCJCaZmqlqcLHf8XYJi6MqwO7RA Iu9IohHaGiWj+pwqnMctsCsTFYvH2hg9ofjp0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=azOJGeenO90UDElVZnGvhTa1WOYkaMQED3kOM1E619Q=; b=KC8x1X6h0eM6kKl5Xp/HC9ZI8gDGbivbhoSgwo4aF6Hq5xTSDtCAFpLwq3n4PuWKBy zupl8qWBRecLqcdMXzh+2WLA/y5nACm2obumDFJeiBouCLG6fOnBCjOe7Ifn/Jr64NyX XlzYqHTx9X4yv6u6EiEEzS4ZjiLeCCkkKWWfimhpKQPiMkbiMQQVD2pCIC+oYKTnrtup WGrCCbYHJPe3RPEJ1VxGJO3cZgGN/OEOwqcduf3MmngEt0jlLglkwoGmCJQDvTprcHGO Wh1cxc9MWK+y7ApFYQv7/uFxtEr1HRXGB7sP5ae0PBk7jUBwDliUtgiUv3Rp30WnE5EL f/XQ== X-Gm-Message-State: APjAAAXYhNOa2LMFWZGkZwyCkTjvtcvJRdeYe1gXwVQDvG2hwfvm1Ejv WnBvNT7kDZXqH7sD8jW7L9vewQ== X-Google-Smtp-Source: APXvYqxYRZKxhf678NfYnON6C+bRqFB77arOwAg3WMS1KXZ4+qWQqA43m9A0cMWuZMS04lt6xPrTBQ== X-Received: by 2002:a17:902:7009:: with SMTP id y9mr6022788plk.254.1579905803606; Fri, 24 Jan 2020 14:43:23 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:23 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v2 07/10] clk: qcom: Fix sc7180 gpucc parent data Date: Fri, 24 Jan 2020 14:42:22 -0800 Message-Id: <20200124144154.v2.7.I3bf44e33f4dc7ecca10a50dbccb7dc082894fa59@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The bindings file (qcom,gpucc.yaml) does not agree with the names we use for input clocks. Fix us. This takes into account the changes in the recent patch ("dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998"), but even without that patch the names in the driver were still not right. Since we didn't add the "test" clock to the bindings (apparently it's never used), kill it from the driver. If someone has a use for it we should add it to the bindings and bring it back. Instead of updating the size of the array now that the test clock is gone, switch to using the less error-prone ARRAY_SIZE. Not sure why it didn't always use that. Fixes: 745ff069a49c ("clk: qcom: Add graphics clock controller driver for SC7180") Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("clk: qcom: Fix sc7180 gpucc parent data") new for v2. drivers/clk/qcom/gpucc-sc7180.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c index ec61194cceaf..da56506036e2 100644 --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c @@ -47,7 +47,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = { .hw.init = &(struct clk_init_data){ .name = "gpu_cc_pll1", .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", + .fw_name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, @@ -64,11 +64,10 @@ static const struct parent_map gpu_cc_parent_map_0[] = { }; static const struct clk_parent_data gpu_cc_parent_data_0[] = { - { .fw_name = "bi_tcxo" }, + { .fw_name = "xo" }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .fw_name = "gcc_gpu_gpll0_clk_src" }, - { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "gpll0" }, + { .fw_name = "gpll0_div" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { @@ -86,7 +85,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .parent_data = gpu_cc_parent_data_0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, From patchwork Fri Jan 24 22:42:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351193 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6DEC3921 for ; Fri, 24 Jan 2020 22:43:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4B4212071E for ; Fri, 24 Jan 2020 22:43:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="GAuRxrEU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387486AbgAXWn1 (ORCPT ); Fri, 24 Jan 2020 17:43:27 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:39383 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387470AbgAXWnZ (ORCPT ); Fri, 24 Jan 2020 17:43:25 -0500 Received: by mail-pl1-f195.google.com with SMTP id g6so1364323plp.6 for ; Fri, 24 Jan 2020 14:43:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KgDJnseYnz4OU4RUOTS2EdiEuy4zgbQiW3cvu5KP3Bs=; b=GAuRxrEUmOh1B/lYq8pdQNa2Ca4EhT9saJERWCzXtmnE8VntcFpUki5UHOAstOSmkP i3VSpJxMwUeIIc7K/XYK2OAzVhsmxra6igc8yt7Vhaank8vcIRJ707V1CsdHroQBquV5 JeoMA39mKgXUxpl9qyig7L7KuxfJoMVrluNXs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KgDJnseYnz4OU4RUOTS2EdiEuy4zgbQiW3cvu5KP3Bs=; b=TOo61Qn9KuAHW8dSN8QK+gjoenu2Jg44cl17pvE5HDmlaHRJ/GxTxCnwC5d6aTbAKj FpMMqyjW5gwOtlZ8fbCWqlEGgaiUIY2Vh+MF0VYzyeCuJu4iPoQfUFOnsLh5LUrU62YS fkLyA8TR7P/h4BI/JXV1G3elGhYhzOr2voQc+LBAzN+8uTs36i5P12SVdgLZ+5A9GbVN M6Zk2UmTFwd3ulPnaXm+L7Zd2b22I+4r7TxYAE57eVOQpdpelTGdbB5gc6oJQ7SXxmrZ A53UXeLDp44F3tvLVqMpvDFGEeWlfGzM6ur/E4v7lgZwApJhLFpyHT/7diXvswDktvC7 ROXA== X-Gm-Message-State: APjAAAWyzsIb0nILxNZmJ9htZ1j3VJSfOqyEt8iqbjS6h3bHKgiKJERn JrKe9x7jA0v24mL3pJp08qyCMw== X-Google-Smtp-Source: APXvYqxPaY2TkvBXDFF6hVUkaUSUdjm0Pk7pvufJGy0X/2Yc03N2ElivrqXa01QJ+81P7T4JRLsCFA== X-Received: by 2002:a17:902:aa45:: with SMTP id c5mr5882411plr.305.1579905804708; Fri, 24 Jan 2020 14:43:24 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:24 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 08/10] dt-bindings: clock: Cleanup qcom,videocc bindings for sdm845/sc7180 Date: Fri, 24 Jan 2020 14:42:23 -0800 Message-Id: <20200124144154.v2.8.I27bbd90045f38cd3218c259526409d52a48efb35@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This makes the qcom,videocc bindings match the recent changes to the dispcc and gpucc. Unlike the recent changes to those files, this one doesn't really have any functional change. It: 1. Adds a description for the XO clock. Not terribly important but nice if it cleanly matches its cousins. 2. Updates the example to use the symbolic name for the RPMH clock and also show that the real devices are currently using 2 address cells / size cells and fixes the spacing on the closing brace. Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("dt-bindings: clock: Cleanup qcom,videocc") new for v2. .../devicetree/bindings/clock/qcom,videocc.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 43cfc893a8d1..745928dc0fcb 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -20,7 +20,8 @@ properties: - qcom,sdm845-videocc clocks: - maxItems: 1 + items: + - description: Board XO source clock-names: items: @@ -50,13 +51,14 @@ required: examples: # Example of VIDEOCC with clock node properties for SDM845: - | + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; - reg = <0xab00000 0x10000>; - clocks = <&rpmhcc 0>; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - }; + }; ... From patchwork Fri Jan 24 22:42:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A62CA921 for ; Fri, 24 Jan 2020 22:43:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 860E7208C4 for ; Fri, 24 Jan 2020 22:43:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="nJUnCZVZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387488AbgAXWnj (ORCPT ); Fri, 24 Jan 2020 17:43:39 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:44980 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387480AbgAXWn0 (ORCPT ); Fri, 24 Jan 2020 17:43:26 -0500 Received: by mail-pf1-f193.google.com with SMTP id 62so1783067pfu.11 for ; Fri, 24 Jan 2020 14:43:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bui28Vv12xUmXWYpC+BbDFYgTGPFUNN9TS7e8X83ptU=; b=nJUnCZVZFNjMZvgzvmEPCuW8bMgT93sV0s2dZgIYVCytFK0KhhjowkK2AosMIsSyay KmsdEYHy/oKz+S9r2Kkijver4P7gSJN8tLFftGYIKJ/WG2/GJaPtQiiz5n4FA8uhSKE1 yjW6QAW2ZhSfO7AVaFhdvXiXxzrTqDyFmvByI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bui28Vv12xUmXWYpC+BbDFYgTGPFUNN9TS7e8X83ptU=; b=nnmuYIu81HUIhPAfUfHxklQ+t+YHuiiRKCtYVcyOsismfdGkZdgARmK85MiJvDfELW Kkiu8kiatf4sI4wNjjsUe7izBLkArPQZjBaGzFLO1f58Zt1CyDlxs2BkWS9LZ3dLskAt RVqqyZXmAgsO0IPA7xA4BVptxd+BYp5RnJXUQx2si6WiY3JwXKvDvC0tO4iF8/YA8ZQp CQkjZDQ0XFxa1wcalVjTNyndMMJhKwAyO9lAJXkNfOEaq92c8iha6suXjMwi09q0+6dQ 0UhApgzPxK2Xny62+ZlhLuHvQ4Egl0WJVz4sKmiX+xCqria7lCBOgqylCyWRAceNbsdR X04Q== X-Gm-Message-State: APjAAAXQiDXBPTFibxb46+zph506J67BpQvVysAvCranLIIpNoeIn3nr uzgYsCDFuHwIWpd/470zn5LC2A== X-Google-Smtp-Source: APXvYqzS9tPcZFwCykAq9Smp2Jxt5RR3eG4xljjcnI1eH/vNH2TY407AdxHLUd4cuuKsTLeq6urYLw== X-Received: by 2002:a62:ddd0:: with SMTP id w199mr5272391pff.1.1579905805722; Fri, 24 Jan 2020 14:43:25 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:25 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 09/10] arm64: dts: qcom: sdm845: Add the missing clock on the videocc Date: Fri, 24 Jan 2020 14:42:24 -0800 Message-Id: <20200124144154.v2.9.Id0599319487f075808baba7cba02c4c3c486dc80@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We're transitioning over to requiring the Qualcomm Video Clock Controller to specify all the input clocks. Let's add the one input clock for the videocc for sdm845. NOTE: Until the Linux driver for sdm845's video is updated, this clock will not actually be used in Linux. It will continue to use global clock names to match things up. Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("arm64: dts: qcom: sdm845: Add...videocc") new for v2. arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e624c91dbd6d..8c41e25bd4a8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2605,6 +2605,8 @@ video-core1 { videocc: clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; From patchwork Fri Jan 24 22:42:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351191 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 44CD11398 for ; Fri, 24 Jan 2020 22:43:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2594521569 for ; Fri, 24 Jan 2020 22:43:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="jgjD9Xxy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387516AbgAXWnc (ORCPT ); Fri, 24 Jan 2020 17:43:32 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:38966 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387491AbgAXWn1 (ORCPT ); Fri, 24 Jan 2020 17:43:27 -0500 Received: by mail-pf1-f195.google.com with SMTP id q10so1799083pfs.6 for ; Fri, 24 Jan 2020 14:43:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W9Q9a9KTrafykk7sSvwstO8MsMaSjnD9xam7szWjZDw=; b=jgjD9Xxy4nlsaa7hkNYnuT4CcmzwgvwlFgpRuwAPR3fdSGa7W9GTwmxt/bvF513wuw Z1C0VQpRrsrKWTSMCQhlr/vinxMWl+ODRosOtXxAcvpaj4/Pt2tvxVpsi1JI8pLt4WjW eOgUHMcY/25hhzXZcsr7VEYgR7Z/pVuxz1tis= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W9Q9a9KTrafykk7sSvwstO8MsMaSjnD9xam7szWjZDw=; b=LzorTe7sOv7Ns64O/sw1OGlT9IeyzK7aSN4MQYQqtTxTYJPiDtMHSjime4PhVJAJn7 0SyMyebdMByAlJnqGJ1xur1PEaNVpMAZd89a8Ye7SThhuqH9cFWfGhNq2Ibd8eJsu0Ey ImJ11WkCVPtdatiR4Ct66VFDuiUWez4Qb3PqgYDgoq7T5BoisimmxLVaAiWV/jRgQmI1 TbEO3tsMDZjOkjlyJF8+8wg+6bGp+b45AIyKve//N5TqzW5LaX1CoJnQvFk9fHIwviSv DaMdzMzGiGwysF3gxOcCGVxxpbmqs6TwFbkhHd5cVVZaZP0rpdob0rXeL8dgQV/ol0Nk shEQ== X-Gm-Message-State: APjAAAUnHDl6s2DtuQ+yekoHu4ZhOJb/7LEqRiIBObdKKeRWnisB9jvq iteq5W9XVGfYjKxmwm/z/HvcKQ== X-Google-Smtp-Source: APXvYqyvlxXWuURQFVjahxnKg8HiiJD1ty6z3PYW5nbOmdrvu0Ae1oXPHdhdKlHv1P1ziyQGUdj1Vg== X-Received: by 2002:aa7:8006:: with SMTP id j6mr5297976pfi.185.1579905806866; Fri, 24 Jan 2020 14:43:26 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:26 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 10/10] arm64: dts: sc7180: Add clock controller nodes Date: Fri, 24 Jan 2020 14:42:25 -0800 Message-Id: <20200124144154.v2.10.I1a4b93fb005791e29a9dcf288fc8bd459a555a59@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Taniya Das Add the display, video & graphics clock controller nodes supported on SC7180. NOTE: the dispcc needs input clocks from various PHYs that aren't in the device tree yet. For now we'll leave these stubbed out with <0>, which is apparently the magic way to do this. These clocks aren't really "optional" and this stubbing out method is apparently the best way to handle it. Signed-off-by: Taniya Das Signed-off-by: Douglas Anderson --- Changes in v2: - Added includes - Changed various parent names to match bindings / driver arch/arm64/boot/dts/qcom/sc7180.dtsi | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8011c5fe2a31..ee3b4bade66b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -5,7 +5,9 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#include #include +#include #include #include #include @@ -1039,6 +1041,18 @@ pinmux { }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "xo", "gpll0", "gpll0_div"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -1151,6 +1165,33 @@ usb_1_dwc3: dwc3@a600000 { }; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,sc7180-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc7180-dispcc"; + reg = <0 0x0af00000 0 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <0>, + <0>, + <0>, + <0>; + clock-names = "xo", "gpll0", + "dsi_phy_pll_byte", "dsi_phy_pll_pixel", + "dp_phy_pll_link", "dp_phy_pll_vco_div"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;