From patchwork Wed Sep 26 18:18:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 10616541 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6A96313A4 for ; Wed, 26 Sep 2018 18:41:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D0D92B356 for ; Wed, 26 Sep 2018 18:41:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 510DB2B35D; Wed, 26 Sep 2018 18:41:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA5762B356 for ; Wed, 26 Sep 2018 18:41:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726354AbeI0A4E (ORCPT ); Wed, 26 Sep 2018 20:56:04 -0400 Received: from aserp2120.oracle.com ([141.146.126.78]:48188 "EHLO aserp2120.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725733AbeI0A4E (ORCPT ); Wed, 26 Sep 2018 20:56:04 -0400 Received: from pps.filterd (aserp2120.oracle.com [127.0.0.1]) by aserp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w8QIcmue142973; Wed, 26 Sep 2018 18:41:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2018-07-02; bh=LteFcJ5cZijGO2reVx4UXRMx+07dQrssTmJzWLJv+2Y=; b=pMm0vVhH+yAwJcyKkQH0NxKEQtV59QXo26RI+nYlM8CxBBNgagBKLotm2ZOaDmQj2bjS RhtUavV5VLBC8SDCNkSlKPUFI29c/w9rmHOfF91K2HlnX8aybmWYaTsG+k7x58AAhZkq tynlbIKaCILK4v9ppEMbKP1W9JVUznfoT2g0U43F/+TW83Ba0vce+F87S6ADzthipgVK FAkoz8g4hivHV8t7ll2epRKzRiNGKiHf1UnuVM2KUwBQ7WyJori0E+g26JAUfDpm7F4Z egnPPge3lpqlGewvXAlXrYoyGF9kFHqXqUa4ts+ZZt6Qse2lae+orsOTe6q8lgasAZSK tA== Received: from aserv0022.oracle.com (aserv0022.oracle.com [141.146.126.234]) by aserp2120.oracle.com with ESMTP id 2mndppmepk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 26 Sep 2018 18:41:41 +0000 Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w8QIfejc028936 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 26 Sep 2018 18:41:40 GMT Received: from abhmp0011.oracle.com (abhmp0011.oracle.com [141.146.116.17]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w8QIfesd003904; Wed, 26 Sep 2018 18:41:40 GMT Received: from ban25x6uut29.us.oracle.com (/10.153.73.29) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 26 Sep 2018 11:41:40 -0700 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, rkrcmar@redhat.com, jmattson@google.com Subject: [PATCH 1/2][KVM] nVMX x86: Add a check for reserved bits [11:0] of PML address Date: Wed, 26 Sep 2018 14:18:11 -0400 Message-Id: <20180926181812.30679-2-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180926181812.30679-1-krish.sadhukhan@oracle.com> References: <20180926181812.30679-1-krish.sadhukhan@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=9028 signatures=668707 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=591 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809260173 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to section "Checks on VMX Controls" in Intel SDM vol 3C, bits 11:0 of the PML address must be 0. Signed-off-by: Krish Sadhukhan Reviewed-by: Mark Kanda --- arch/x86/include/asm/vmx.h | 2 ++ arch/x86/kvm/vmx.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 9527ba5..2c118ad 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -339,6 +339,8 @@ enum vmcs_field { HOST_RIP = 0x00006c16, }; +#define PML_ADDRESS_RESV_BITS 0xfff + /* * Interruption-information format */ diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 533a327..49e707d 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -11712,7 +11712,8 @@ static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) { if (!nested_cpu_has_ept(vmcs12) || !IS_ALIGNED(address, 4096) || - address >> maxphyaddr) + address >> maxphyaddr || + address & PML_ADDRESS_RESV_BITS) return -EINVAL; } From patchwork Wed Sep 26 18:18:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 10616543 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 892AC112B for ; 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Wed, 26 Sep 2018 18:41:41 +0000 Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by userv0021.oracle.com (8.14.4/8.14.4) with ESMTP id w8QIffru003316 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 26 Sep 2018 18:41:41 GMT Received: from abhmp0011.oracle.com (abhmp0011.oracle.com [141.146.116.17]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id w8QIff0t022691; Wed, 26 Sep 2018 18:41:41 GMT Received: from ban25x6uut29.us.oracle.com (/10.153.73.29) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 26 Sep 2018 11:41:40 -0700 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, rkrcmar@redhat.com, jmattson@google.com Subject: [PATCH 2/2][kvm-unit-test] nVMX x86: Check PML and EPT on vmentry of L2 guests Date: Wed, 26 Sep 2018 14:18:12 -0400 Message-Id: <20180926181812.30679-3-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180926181812.30679-1-krish.sadhukhan@oracle.com> References: <20180926181812.30679-1-krish.sadhukhan@oracle.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=9028 signatures=668707 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=917 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809260173 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to section "Checks on VMX Controls" in Intel SDM vol 3C, the following check needs to be enforced on vmentry of L2 guests: If the "enable PML" VM-execution control is 1, the "enable EPT" VM-execution control must also be 1. In addition, the PML address must satisfy the following checks: — Bits 11:0 of the address must be 0. — The address should not set any bits beyond the processor’s physical-address width. Signed-off-by: Krish Sadhukhan Reviewed-by: Mark Kanda --- x86/vmx.h | 3 ++ x86/vmx_tests.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 91 insertions(+), 11 deletions(-) diff --git a/x86/vmx.h b/x86/vmx.h index 22b2892..78a786e 100644 --- a/x86/vmx.h +++ b/x86/vmx.h @@ -448,6 +448,9 @@ enum Intr_type { #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ #define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */ + +#define PMLADDR_RESV_BITS 0xfff + /* * VM-instruction error numbers */ diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index 0e9d900..37db793 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -3452,14 +3452,18 @@ static void test_vmcs_page_addr(const char *name, static void test_vmcs_page_values(const char *name, enum Encoding encoding, bool ignored, - bool xfail_beyond_mapped_ram) + bool xfail_beyond_mapped_ram, + u64 resv_bits) { unsigned i; u64 orig_val = vmcs_read(encoding); - for (i = 0; i < 64; i++) + for (i = 0; i < 64; i++) { + if (i & resv_bits) + continue; test_vmcs_page_addr(name, encoding, ignored, xfail_beyond_mapped_ram, 1ul << i); + } test_vmcs_page_addr(name, encoding, ignored, xfail_beyond_mapped_ram, PAGE_SIZE - 1); @@ -3483,7 +3487,7 @@ static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, const char *field_name, const char *control_name, bool xfail_beyond_mapped_ram, - bool control_primary) + bool control_primary, u64 resv_bits) { u32 primary = vmcs_read(CPU_EXEC_CTRL0); u32 secondary = vmcs_read(CPU_EXEC_CTRL1); @@ -3506,7 +3510,8 @@ static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); } - test_vmcs_page_values(field_name, field, false, xfail_beyond_mapped_ram); + test_vmcs_page_values(field_name, field, false, + xfail_beyond_mapped_ram, resv_bits); report_prefix_pop(); report_prefix_pushf("%s disabled", control_name); @@ -3516,7 +3521,7 @@ static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); } - test_vmcs_page_values(field_name, field, true, false); + test_vmcs_page_values(field_name, field, true, false, resv_bits); report_prefix_pop(); vmcs_write(field, page_addr); @@ -3533,10 +3538,10 @@ static void test_io_bitmaps(void) { test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_A, "I/O bitmap A", "Use I/O bitmaps", false, - true); + true, 0); test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_B, "I/O bitmap B", "Use I/O bitmaps", false, - true); + true, 0); } /* @@ -3549,7 +3554,7 @@ static void test_msr_bitmap(void) { test_vmcs_page_reference(CPU_MSR_BITMAP, MSR_BITMAP, "MSR bitmap", "Use MSR bitmaps", false, - true); + true, 0); } /* @@ -3564,7 +3569,7 @@ static void test_apic_virt_addr(void) { test_vmcs_page_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, "virtual-APIC address", "Use TPR shadow", - true, true); + true, true, 0); } /* @@ -3583,7 +3588,7 @@ static void test_apic_access_addr(void) test_vmcs_page_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, "APIC-access address", - "virtualize APIC-accesses", false, false); + "virtualize APIC-accesses", false, false, 0); } static bool set_bit_pattern(u8 mask, u32 *secondary) @@ -3869,7 +3874,8 @@ static void test_posted_intr(void) test_pi_desc_addr(0x00, true); test_pi_desc_addr(0xc000, true); - test_vmcs_page_values("process-posted interrupts", POSTED_INTR_DESC_ADDR, false, false); + test_vmcs_page_values("process-posted interrupts", + POSTED_INTR_DESC_ADDR, false, false, 0); vmcs_write(CPU_EXEC_CTRL0, saved_primary); vmcs_write(CPU_EXEC_CTRL1, saved_secondary); @@ -4408,6 +4414,76 @@ done: vmcs_write(PIN_CONTROLS, pin_ctrls); } +/* + * If the “enable PML” VM-execution control is 1, the “enable EPT” + * VM-execution control must also be 1. In addition, the PML address + * must satisfy the following checks: + * + * — Bits 11:0 of the address must be 0. + * — The address should not set any bits beyond the processor’s + * physical-address width. + + * [Intel SDM] + */ +static void test_pml(void) +{ + u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); + u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); + u32 primary = primary_saved; + u32 secondary = secondary_saved; + u64 pml_addr; + int i; + + if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && + (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { + test_skip("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !"); + return; + } + + primary |= CPU_SECONDARY; + vmcs_write(CPU_EXEC_CTRL0, primary); + secondary &= ~(CPU_PML | CPU_EPT); + vmcs_write(CPU_EXEC_CTRL1, secondary); + report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); + test_vmx_controls(true, false); + report_prefix_pop(); + + secondary |= CPU_PML; + vmcs_write(CPU_EXEC_CTRL1, secondary); + report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); + test_vmx_controls(false, false); + report_prefix_pop(); + + secondary |= CPU_EPT; + vmcs_write(CPU_EXEC_CTRL1, secondary); + report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); + test_vmx_controls(true, false); + report_prefix_pop(); + + secondary &= ~CPU_PML; + vmcs_write(CPU_EXEC_CTRL1, secondary); + report_prefix_pushf("enable-PML disabled, enable EPT enabled"); + test_vmx_controls(true, false); + report_prefix_pop(); + + secondary |= CPU_PML; + vmcs_write(CPU_EXEC_CTRL1, secondary); + + pml_addr = (u64) phys_to_virt(vmcs_read(PMLADDR)); + for (i = 0; i < 12; i++) { + pml_addr |= 1ull << i; + vmcs_write(PMLADDR, virt_to_phys((void *) pml_addr)); + report_prefix_pushf("PML address 0x%lx", pml_addr); + test_vmx_controls(false, false); + report_prefix_pop(); + } + + test_vmcs_page_reference(CPU_PML, PMLADDR, "PML address", + "PML", false, false, PMLADDR_RESV_BITS); + + vmcs_write(CPU_EXEC_CTRL0, primary_saved); + vmcs_write(CPU_EXEC_CTRL1, secondary_saved); +} /* * Check that the virtual CPU checks all of the VMX controls as @@ -4431,6 +4507,7 @@ static void vmx_controls_test(void) test_apic_ctls(); test_tpr_threshold(); test_nmi_ctrls(); + test_pml(); test_invalid_event_injection(); }