From patchwork Thu Jan 30 21:12:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358689 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B1730139A for ; Thu, 30 Jan 2020 21:12:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9069F214DB for ; Thu, 30 Jan 2020 21:12:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="NQMw82GE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727515AbgA3VMu (ORCPT ); Thu, 30 Jan 2020 16:12:50 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:42187 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727089AbgA3VMu (ORCPT ); Thu, 30 Jan 2020 16:12:50 -0500 Received: by mail-pg1-f195.google.com with SMTP id s64so2278721pgb.9 for ; Thu, 30 Jan 2020 13:12:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qiYgMeeUC0YBpAKelC+4dn+CN5ICnSUf2MkjMCbgL5c=; b=NQMw82GEkZ6PCiwjiH4rDlQHZWp89OEeOFi1fTtGIJyi/seUYDg2GVNuf+3iQS0Fiu /eWZAkdKHkVeg51jDe0fQTGXbsqxftfBFdoE3DR4sZN3MTn3L6mbGeWlkrJj4jC+W2eK 2B8kfMWCHQ2xh4NPd/FxrnPp2i9YH3BXJyFbc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qiYgMeeUC0YBpAKelC+4dn+CN5ICnSUf2MkjMCbgL5c=; b=iAvCt+J5UrewaiFngkuHB+5g86nk88o4HApZ8R2b3lnrYgJAaKH2+NJ3tsA9VBxFPY CwbHvlwxEvwUbqCuHi3mTQjt4jlRAgxREcT5J96haG7UmAJpsIFK7Ls8hPNN6uezbWmF /IZg3Ea+rCVVBoIR8RjC0X9yPEsPhom+GVnnRL1bfslMQtfSVuIJbZM68rRteAtPCpN7 VfdoYA+6hQK9zHT/N8PJG/ia1/JicTTwvilEmBMwyvb+wXz7WKxNYzAMBAr131zIhnt1 jU7LGCL+fP7g/k7S/rfQ7NF3KjcDdtv5DqQUWBH2zEPSMTJRe7LIf0tt+pUoat3abXEg FOeQ== X-Gm-Message-State: APjAAAXodiXM53lQl0pmY9Qr5W1gptOh3yvcH/fSPafFd8c3yYWip9Yh pbzO0nF9EBCV6y8Imgy/G0orHA== X-Google-Smtp-Source: APXvYqxtcrlprtA94Pt11rgDOHvAhaLPmxrkPcj2drtGice8emH1/TtSR99Y/5dZQDkssXFxNGMyOQ== X-Received: by 2002:a65:4242:: with SMTP id d2mr6728403pgq.166.1580418769626; Thu, 30 Jan 2020 13:12:49 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:12:49 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v3 01/15] clk: qcom: rcg2: Don't crash if our parent can't be found; return an error Date: Thu, 30 Jan 2020 13:12:17 -0800 Message-Id: <20200130131220.v3.1.I7487325fe8e701a68a07d3be8a6a4b571eca9cfa@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When I got my clock parenting slightly wrong I ended up with a crash that looked like this: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 ... pc : clk_hw_get_rate+0x14/0x44 ... Call trace: clk_hw_get_rate+0x14/0x44 _freq_tbl_determine_rate+0x94/0xfc clk_rcg2_determine_rate+0x2c/0x38 clk_core_determine_round_nolock+0x4c/0x88 clk_core_round_rate_nolock+0x6c/0xa8 clk_core_round_rate_nolock+0x9c/0xa8 clk_core_set_rate_nolock+0x70/0x180 clk_set_rate+0x3c/0x6c of_clk_set_defaults+0x254/0x360 platform_drv_probe+0x28/0xb0 really_probe+0x120/0x2dc driver_probe_device+0x64/0xfc device_driver_attach+0x4c/0x6c __driver_attach+0xac/0xc0 bus_for_each_dev+0x84/0xcc driver_attach+0x2c/0x38 bus_add_driver+0xfc/0x1d0 driver_register+0x64/0xf8 __platform_driver_register+0x4c/0x58 msm_drm_register+0x5c/0x60 ... It turned out that clk_hw_get_parent_by_index() was returning NULL and we weren't checking. Let's check it so that we don't crash. Fixes: ac269395cdd8 ("clk: qcom: Convert to clk_hw based provider APIs") Signed-off-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke --- I haven't gone back and tried to reproduce this same crash on older kernels, but I'll put the blame on commit ac269395cdd8 ("clk: qcom: Convert to clk_hw based provider APIs"). Before that if we got a NULL parent back it was fine and dandy since a NULL "struct clk" is valid to use but a NULL "struct clk_hw" is not. Changes in v3: - Add Matthias tag. Changes in v2: - Patch ("clk: qcom: rcg2: Don't crash...") new for v2. drivers/clk/qcom/clk-rcg2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index da045b200def..9098001ac805 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -218,6 +218,9 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, clk_flags = clk_hw_get_flags(hw); p = clk_hw_get_parent_by_index(hw, index); + if (!p) + return -EINVAL; + if (clk_flags & CLK_SET_RATE_PARENT) { rate = f->freq; if (f->pre_div) { From patchwork Thu Jan 30 21:12:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358747 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8326214D5 for ; Thu, 30 Jan 2020 21:13:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 60B8C217BA for ; Thu, 30 Jan 2020 21:13:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="mvlLQg25" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727911AbgA3VNz (ORCPT ); Thu, 30 Jan 2020 16:13:55 -0500 Received: from mail-pj1-f65.google.com ([209.85.216.65]:55225 "EHLO mail-pj1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727753AbgA3VMv (ORCPT ); Thu, 30 Jan 2020 16:12:51 -0500 Received: by mail-pj1-f65.google.com with SMTP id dw13so1870529pjb.4 for ; Thu, 30 Jan 2020 13:12:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TLRLFIcc4LIDPB9YigEhydFs/8ZzkV4XRdQLFB2ep6Q=; b=mvlLQg25kRWGKBllUT9LNWpMct+Ba9NKWhZdoJX9+F9VAred9+dS/mDDCVnUjMykB6 JGnUnzTVq3MReXN52FJHvEOjso6Eo4DYGGCKemrWLVfzm13MY7EJwthSidsm5ZTA2WNN CbsWG08fig8R1vdNkLtPz/Qr8aV/mkk5CBygY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TLRLFIcc4LIDPB9YigEhydFs/8ZzkV4XRdQLFB2ep6Q=; b=bD4QJwIqR5bdPrrNfw+904Ly8uMW9Tp8858NOlp6dUktNM/e4ZVucGDjq+Du0mlqRF 9FQV6wK6ij5ltc00AJ3MSKQan2keI13QsQesus3vbJ/TwhQOf5JopOGekPiBQdVw9TEf D38rOfU4TN5KNgXRlvotNucZKj+f32WxdiMZxLBelfRb30/Kkbs1KWI55CiaqaNONjwE YNNLJhB3M4BWz9FWYaxnUt0gGqlaV1EX8J+TOsxxxf7GHeOtfY1br0OAImZEG2fh3FDe TrHcHdbm4B8cJY4X9NdH/1vR9cgp99KRM/bXJVZ7MwzgV4B6/cJq2hPB450AfTX4F9jJ yihQ== X-Gm-Message-State: APjAAAX2qt+Gmqm6rJ2EmCpNWsIVn7/x2ckBoiIy/QVcu3pBDuCUDTjB IxAyHr6Ml87mfmty+pnINju6Vw== X-Google-Smtp-Source: APXvYqynqQ+EaQq3PdE2MU+3FgfT6u0H42mDI9WEvEDzLZl9MDS9Vjmi62wBJhNJvvoukgiX+YZr8A== X-Received: by 2002:a17:90a:db0b:: with SMTP id g11mr7870236pjv.140.1580418770963; Thu, 30 Jan 2020 13:12:50 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:12:50 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 02/15] dt-bindings: clock: Fix qcom,dispcc bindings for sdm845/sc7180 Date: Thu, 30 Jan 2020 13:12:18 -0800 Message-Id: <20200130131220.v3.2.I0c4bbb0f75a0880cd4bd90d8b267271e2375e0d0@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The qcom,dispcc bindings had a few problems with them: 1. They didn't specify all the clocks that dispcc is a client of. Specifically on sc7180 there are two clocks from the DSI PHY and two from the DP PHY. On sdm845 there are actually two DSI PHYs (each of which has two clocks) and an extra clock from the gcc. These all need to be specified. 2. The sdm845.dtsi has existed for quite some time without specifying the clocks. The Linux driver was relying on global names to match things up. While we should transition things, it should be noted in the bindings. 3. The names used the bindings for "xo" and "gpll0" didn't match the names that QC used for these clocks internally and this was causing confusion / difficulty with their code generation tools. Switched to the internal names to simplify everyone's lives. It's not quite as clean in a purist sense but it should avoid headaches. This officially changes the binding, but that seems OK in this case. Also note that I updated the example. Fixes: 5d28e44ba630 ("dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings") Signed-off-by: Douglas Anderson Reviewed-by: Rob Herring --- Changes in v3: - Added include file to description. - Discovered / added new gcc input clock on sdm845. - Split sc7180 and sdm845 into two files. - Switched names to internal QC names rather than logical ones. - Updated commit description. Changes in v2: - Patch ("dt-bindings: clock: Fix qcom,dispcc...") new for v2. .../bindings/clock/qcom,dispcc.yaml | 67 ------------- .../bindings/clock/qcom,sc7180-dispcc.yaml | 84 ++++++++++++++++ .../bindings/clock/qcom,sdm845-dispcc.yaml | 99 +++++++++++++++++++ 3 files changed, 183 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml deleted file mode 100644 index 9c58e02a1de1..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml +++ /dev/null @@ -1,67 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/bindings/clock/qcom,dispcc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Display Clock & Reset Controller Binding - -maintainers: - - Taniya Das - -description: | - Qualcomm display clock control module which supports the clocks, resets and - power domains. - -properties: - compatible: - enum: - - qcom,sc7180-dispcc - - qcom,sdm845-dispcc - - clocks: - minItems: 1 - maxItems: 2 - items: - - description: Board XO source - - description: GPLL0 source from GCC - - clock-names: - items: - - const: xo - - const: gpll0 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - -required: - - compatible - - reg - - clocks - - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - -examples: - # Example of DISPCC with clock node properties for SDM845: - - | - clock-controller@af00000 { - compatible = "qcom,sdm845-dispcc"; - reg = <0xaf00000 0x10000>; - clocks = <&rpmhcc 0>, <&gcc 24>; - clock-names = "xo", "gpll0"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; -... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml new file mode 100644 index 000000000000..35315011fc37 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,sc7180-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller Binding for SC7180 + +maintainers: + - Taniya Das + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains on SC7180. + + See also dt-bindings/clock/qcom,dispcc-sc7180.h. + +properties: + compatible: + const: qcom,sc7180-dispcc + + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: bi_tcxo + - const: gcc_disp_gpll0_clk_src + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dp_phy_pll_link_clk + - const: dp_phy_pll_vco_div_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include + #include + clock-controller@af00000 { + compatible = "qcom,sc7180-dispcc"; + reg = <0 0x0af00000 0 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&dsi_phy 0>, + <&dsi_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml new file mode 100644 index 000000000000..aed2387dc4a6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,sdm845-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller Binding for SDM845 + +maintainers: + - Taniya Das + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains on SDM845. + + See also dt-bindings/clock/qcom,dispcc-sdm845.h. + +properties: + compatible: + const: qcom,sdm845-dispcc + + # NOTE: sdm845.dtsi existed for quite some time and specified no clocks. + # The code had to use hardcoded mechanisms to find the input clocks. + # New dts files should have these clocks. + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: GPLL0 div source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: bi_tcxo + - const: gcc_disp_gpll0_clk_src + - const: gcc_disp_gpll0_div_clk_src + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dsi1_phy_pll_out_byteclk + - const: dsi1_phy_pll_out_dsiclk + - const: dp_link_clk_divsel_ten + - const: dp_vco_divided_clk_src_mux + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include + #include + clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... From patchwork Thu Jan 30 21:12:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358735 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D4EA5139A for ; Thu, 30 Jan 2020 21:13:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD5A42173E for ; Thu, 30 Jan 2020 21:13:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="lIJoBPTf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727821AbgA3VMy (ORCPT ); Thu, 30 Jan 2020 16:12:54 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:43851 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727810AbgA3VMy (ORCPT ); Thu, 30 Jan 2020 16:12:54 -0500 Received: by mail-pf1-f195.google.com with SMTP id s1so2116353pfh.10 for ; Thu, 30 Jan 2020 13:12:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ksW7l4fWNLieSdrD5EsRsMEIiSgG7sjjBAvxsINRjjI=; b=lIJoBPTf3duj1eGQFhz8YZ62Df5Wff7+ob6LqqpeugT+H1yud6k/Zqa6NEla/2kNxa XhvZHWFcApCtUzFq+g3sI+fNNpM7vtTTuAe7F0FoHjweGDvnvcLVehSj5wp/nMORMZKr s7PJGCe+AhcIao2G8L5JmqjVFlzfmralDLnc0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ksW7l4fWNLieSdrD5EsRsMEIiSgG7sjjBAvxsINRjjI=; b=PELD6QTEaN81kD5xAzos6zUqfld/4UnylHSMbiGsaaFAi8f1S3cgJAQgMQ2MD4xrsE EtiWMrayTNmn69NcBzg1hqTJ2AnEiSQL/T4SrbiE1NiDgz9oJ5XZVxvdkRVXVBxBjrid p8U7DLIo4Zk+q+aR8aRZCpLadakIFaShqvb251hgXi/Qi+VLBHkvVD3S66oeE7uYNg9T vBrHTRURsDtxCXiL1vfAcbOaUBlan/Ra52/LwUAVxBEa3I70j6TClYMuFYlosT0oVWUv Ag+PSZpvTRtYDRaRPwMnQylQUflM9nfBT3yPA7hDqmNBDbzSns0WKHzZZ9XSL3olpeWP bi1A== X-Gm-Message-State: APjAAAXC/c2xx7dmRKOhZtUvYmM+Jha2YgEBxWOS6uszJri/NXBMnKn+ 8SIEk5/yHnbSL5Y0qODo3H8PmQ== X-Google-Smtp-Source: APXvYqxLqyb7vvP/CmhMs7YyJCKrP+csYoKAiXN3h5NKS0788VFJpZYxoKMMWiN7TlkQ4j8Te7RKKw== X-Received: by 2002:a63:6602:: with SMTP id a2mr6293262pgc.403.1580418772289; Thu, 30 Jan 2020 13:12:52 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:12:51 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 03/15] arm64: dts: qcom: sdm845: Add the missing clocks on the dispcc Date: Thu, 30 Jan 2020 13:12:19 -0800 Message-Id: <20200130131220.v3.3.Ie80fa74e1774f4317d80d70d30ef4b78f16cc8df@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We're transitioning over to requiring the Qualcomm Display Clock Controller to specify all the input clocks. Let's add them for sdm845. NOTES: - Until the Linux driver for sdm845's dispcc is updated, these clocks will not actually be used in Linux. It will continue to use global clock names to match things up. - Although the clocks from the DP PHY are required, the DP PHY isn't represented in the dts yet. Apparently the magic for this is just to use <0>. Signed-off-by: Douglas Anderson --- Changes in v3: - Newly discovered gcc_disp_gpll0_div_clk_src added. - Unlike in v2, use internal name instead of purist name. Changes in v2: - Patch ("arm64: dts: qcom: sdm845: Add...dispcc") new for v2. arch/arm64/boot/dts/qcom/sdm845.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d42302b8889b..0985813fee50 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2933,6 +2933,24 @@ opp-200000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Thu Jan 30 21:12:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358739 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97BDA14D5 for ; Thu, 30 Jan 2020 21:13:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 76DEA217BA for ; Thu, 30 Jan 2020 21:13:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="jMU9zGKg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727803AbgA3VNv (ORCPT ); Thu, 30 Jan 2020 16:13:51 -0500 Received: from mail-pl1-f193.google.com ([209.85.214.193]:40564 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727809AbgA3VMy (ORCPT ); Thu, 30 Jan 2020 16:12:54 -0500 Received: by mail-pl1-f193.google.com with SMTP id y1so1815190plp.7 for ; Thu, 30 Jan 2020 13:12:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K0XoSuGyqNEgB75IwM+XmimRDu75qzQuIcV/EwSuAJM=; b=jMU9zGKgBOBNllW9XZIw0g9AOLLZ5Vj2JIaOdChfocVUyNqDD4m6qBdopC/RE6PUJH fCVpq66hw6aTVQJxY86HFMSzfd/b+TUu0i75shdttFKG2Ys0VeOEacgB4bTrDt82h8kD D0cS2v0Z7/RPVbl2wz8j2u3Cg5FmGNCuxDMzc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K0XoSuGyqNEgB75IwM+XmimRDu75qzQuIcV/EwSuAJM=; b=JA2m7SviL5BKC5qZssofwsCchKIcJ6f84dSv9Fgt93FnEGWJaT889jik+2hDd8m/V0 azvj5HY66x+m9TrHmumb7baMm0AftlbQnVxamjEGkoLqNl1MXhynlmgC+dSb1r+J7EOu zvuNTWjNKkNnlqSnRyAaDCGojNEs7SK9PLeIjmeI8ShgCeo9fTGFvnqeR9mQopJnywb1 zEdK7V3OtNH6QAxMTqjDNMHmkcgxE5UjbRixlbWZ0N39X1PQO7pNbZ88xqpASN/KfOr1 hI6+0dqk/RuiG6ZCMzdJEAyv4818C7FAJQ3WHfvNWRHndFvSfFHlYLTiornINhsTKOCs z63Q== X-Gm-Message-State: APjAAAW0CHs8n9oFaSwd94qRgqTTJC3XQQX9yFIKvMhMvxHXZIk+Y1uv abBh92xjzG6IP1uToinQTEORcg== X-Google-Smtp-Source: APXvYqynCN6w21P8hmWBFQ1aqUqYCVjtZhBJEtINjT7jo1jag3FXsGA/Luh9zWpaQq2LkwWTRW6QOg== X-Received: by 2002:a17:902:9342:: with SMTP id g2mr6378449plp.339.1580418773549; Thu, 30 Jan 2020 13:12:53 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:12:53 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v3 04/15] clk: qcom: Get rid of fallback global names for dispcc-sc7180 Date: Thu, 30 Jan 2020 13:12:20 -0800 Message-Id: <20200130131220.v3.4.Ia3706a5d5add72e88dbff60fd13ec06bf7a2fd48@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In the new world input clocks should be matched by ".fw_name". sc7180 is new enough that no backward compatibility use of global names should be needed. Remove it. With a proper device tree and downstream display patches I have verified booting a sc7180 up and seeing the display after this patch. Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180") Signed-off-by: Douglas Anderson --- Changes in v3: - Patch ("clk: qcom: Get rid of fallback...dispcc-sc7180") split out for v3. - Unlike in v2, use internal name instead of purist name. Changes in v2: None drivers/clk/qcom/dispcc-sc7180.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 30c1e25d3edb..a820e1558677 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -81,7 +81,7 @@ static const struct parent_map disp_cc_parent_map_0[] = { static const struct clk_parent_data disp_cc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_1[] = { @@ -93,10 +93,9 @@ static const struct parent_map disp_cc_parent_map_1[] = { static const struct clk_parent_data disp_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" }, - { .fw_name = "dp_phy_pll_vco_div_clk", - .name = "dp_phy_pll_vco_div_clk"}, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "dp_phy_pll_link_clk" }, + { .fw_name = "dp_phy_pll_vco_div_clk" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_2[] = { @@ -107,9 +106,8 @@ static const struct parent_map disp_cc_parent_map_2[] = { static const struct clk_parent_data disp_cc_parent_data_2[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "dsi0_phy_pll_out_byteclk", - .name = "dsi0_phy_pll_out_byteclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "dsi0_phy_pll_out_byteclk" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_3[] = { @@ -125,7 +123,7 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = { { .hw = &disp_cc_pll0.clkr.hw }, { .fw_name = "gcc_disp_gpll0_clk_src" }, { .hw = &disp_cc_pll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_4[] = { @@ -137,7 +135,7 @@ static const struct parent_map disp_cc_parent_map_4[] = { static const struct clk_parent_data disp_cc_parent_data_4[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "gcc_disp_gpll0_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_5[] = { @@ -148,9 +146,8 @@ static const struct parent_map disp_cc_parent_map_5[] = { static const struct clk_parent_data disp_cc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "dsi0_phy_pll_out_dsiclk", - .name = "dsi0_phy_pll_out_dsiclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { From patchwork Thu Jan 30 21:12:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358695 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2A6D413B4 for ; Thu, 30 Jan 2020 21:12:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 08A43214DB for ; Thu, 30 Jan 2020 21:12:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="aNiL5acF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727850AbgA3VM5 (ORCPT ); Thu, 30 Jan 2020 16:12:57 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:44987 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727824AbgA3VMz (ORCPT ); Thu, 30 Jan 2020 16:12:55 -0500 Received: by mail-pl1-f196.google.com with SMTP id d9so1813918plo.11 for ; Thu, 30 Jan 2020 13:12:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kusoJ9Oev7Pj23ZWUrs+11xOFwvMD53pguR4hXEdEGM=; b=aNiL5acFWisbjjTjfzgrXPr9wjxck7dAlmTjQgrZCCM/2Ww2pKszK96bQNvTdaoXDI rKdLZiEFhEZzTrTKNTNdx8pQB8H+18Xjd1eJdZMHso7yRyUwtBMOR68F8rEnWfjW9fQt RfxldIPLgtVNSZVw1EEsSFvXkOroxIXPKQFZw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kusoJ9Oev7Pj23ZWUrs+11xOFwvMD53pguR4hXEdEGM=; b=XswGMVc3JWZWfG+q5M+CYJaEEz9xtzIncZxRKF71Q7qpqahFpprP6U/1E60Fehwgy8 jsVbBykprf7w7yNegw2o2zttwq7a1cqxy7dGMRWNTVD115cWV/R/zVieWlj66j+DcWbm 0bBQlLQlMB3usAoKugj2hA02TEZLbGzuOHobR0d5YbOtl0dkOi4lHF3kTq7V0UolqWdj /r+LdX4mIAk6VP8be5uxsMMsLm4ELM8xl9L3prvcGtqcw8bh5LiMKxmCu3G9pI6V1EvD jhT/01FMx6HXeOGTKZTERAg37m0c8gdS+YpfI/BTfGgPG9gRlKbp3I22lvrqQosu/d12 4tPA== X-Gm-Message-State: APjAAAX9hm+lkArovMcGA5BsS0lFCKInPwjXZgBYj7ELv+AkxBc5AFKI X77+it5cTyWrp91INm+V5R2HOQ== X-Google-Smtp-Source: APXvYqwe0qRkaWDidOrdKnE8oUdTw6jxlBtUuBHq5uav5aVOIgtlL/9m1Dd9HvFykYt2bddO1/EEYA== X-Received: by 2002:a17:902:b587:: with SMTP id a7mr6703883pls.82.1580418774669; Thu, 30 Jan 2020 13:12:54 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:12:54 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Stephen Boyd , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v3 05/15] clk: qcom: Get rid of the test clock for dispcc-sc7180 Date: Thu, 30 Jan 2020 13:12:21 -0800 Message-Id: <20200130131220.v3.5.I28ac8f801456f1b950f7da10ed0f74a1344d4a35@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Signed-off-by: Douglas Anderson --- Changes in v3: - Patch ("clk: qcom: Get rid of the test...dispcc-sc7180") split out for v3. Changes in v2: None drivers/clk/qcom/dispcc-sc7180.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index a820e1558677..397f5d9dafc8 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -76,38 +76,32 @@ static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = { static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_DP_PHY_PLL_LINK_CLK, 1 }, { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "dp_phy_pll_link_clk" }, { .fw_name = "dp_phy_pll_vco_div_clk" }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_2[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "dsi0_phy_pll_out_byteclk" }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_3[] = { @@ -115,7 +109,6 @@ static const struct parent_map disp_cc_parent_map_3[] = { { P_DISP_CC_PLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 4 }, { P_DISP_CC_PLL0_OUT_EVEN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_3[] = { @@ -123,31 +116,26 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = { { .hw = &disp_cc_pll0.clkr.hw }, { .fw_name = "gcc_disp_gpll0_clk_src" }, { .hw = &disp_cc_pll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 4 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_4[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "gcc_disp_gpll0_clk_src" }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "dsi0_phy_pll_out_dsiclk" }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { @@ -166,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk_src", .parent_data = disp_cc_parent_data_4, - .num_parents = 3, + .num_parents = 2, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -180,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 3, + .num_parents = 2, .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -213,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 4, + .num_parents = 3, .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -227,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 4, + .num_parents = 3, .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -241,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 4, + .num_parents = 3, .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, @@ -256,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 3, + .num_parents = 2, .ops = &clk_rcg2_ops, }, }; @@ -279,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 5, + .num_parents = 4, .ops = &clk_rcg2_shared_ops, }, }; @@ -292,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_5, - .num_parents = 3, + .num_parents = 2, .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -307,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 5, + .num_parents = 4, .ops = &clk_rcg2_shared_ops, }, }; @@ -321,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .parent_data = disp_cc_parent_data_0, - .num_parents = 2, + .num_parents = 1, .ops = &clk_rcg2_shared_ops, }, }; From patchwork Thu Jan 30 21:12:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358727 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09194139A for ; Thu, 30 Jan 2020 21:13:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D1293214AF for ; Thu, 30 Jan 2020 21:13:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Je+x7bEt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727861AbgA3VM7 (ORCPT ); Thu, 30 Jan 2020 16:12:59 -0500 Received: from mail-pj1-f66.google.com ([209.85.216.66]:34823 "EHLO mail-pj1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727858AbgA3VM6 (ORCPT ); Thu, 30 Jan 2020 16:12:58 -0500 Received: by mail-pj1-f66.google.com with SMTP id q39so1887021pjc.0 for ; Thu, 30 Jan 2020 13:12:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yu0tE7jCuc6P8Gf0TRcnvY0HOtkhehB0sRgbam9S9mw=; b=Je+x7bEtn5i3uQsAgU/yZApWLhvhZW3/2d72VMBn2q/jp4B/Lg31E1y9p+AZJL7EfP vJkGT1OPjh5E2VfxFTarfRiCAoo7+TTuacupdT7JgJeW/vLG960sIadA8IWOLcGI/J3O Wlc7wQ/fsJ/VDPQINCi0us6BZskCD94DfNoQM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yu0tE7jCuc6P8Gf0TRcnvY0HOtkhehB0sRgbam9S9mw=; b=JiEG878krQbHK5wH5Xt1SeVDhFB5R//+Y/wsv9GwT+mZnMFE2H7EIaEw7uWr9bZG6p fqZSvmJqgMZrPufJ0pZuyRZPZwEhewCZmC26CTSbU/vjffc5PFCJ3IG/f+NRXtUFWHfm HgReub52EK/SVMVl5SLHdtqfODPTsNm70OM9VHwIIYRujhxJfbijuVG97McVYWKEtiLd ceyBUP+B92FwgW3TQYJBEHCgt+YkyxL0EonMXVv+jDzznoMGnPKNdXSRCeBoaVXTZr0L /yteNgqqFYx/Zq9g20DnUzILmKzrOy/2WDN8/6/f/SvwmGkAUFUrIlGXMZ60VG6Cgb5Q kc8w== X-Gm-Message-State: APjAAAVORFw8OG6HYW25iSM2wr25VXqFU/DvEqmskVfc6s/wgoKcw3gH 0HOHknL8ZQsP8NfdOPCUpXP8Iw== X-Google-Smtp-Source: APXvYqxFB9FtjEV5zQEOPdZ7X0UoEqfIuzNb4PuQXx+lCD7gy7P89y7mtGonSJ1Mrz6R4NCRPiYM8w== X-Received: by 2002:a17:902:ab98:: with SMTP id f24mr6460428plr.338.1580418776031; Thu, 30 Jan 2020 13:12:56 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:12:55 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v3 06/15] clk: qcom: Use ARRAY_SIZE in dispcc-sc7180 for parent clocks Date: Thu, 30 Jan 2020 13:12:22 -0800 Message-Id: <20200130131220.v3.6.If590c468722d2985cea63adf60c0d2b3098f37d9@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It's nicer to use ARRAY_SIZE instead of hardcoding. Had we always been doing this it would have prevented a previous bug. See commit 74c31ff9c84a ("clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6"). Signed-off-by: Douglas Anderson --- Changes in v3: - Patch ("clk: qcom: Use ARRAY_SIZE in dispcc-sc7180...") split out for v3. Changes in v2: None drivers/clk/qcom/dispcc-sc7180.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 397f5d9dafc8..dd7af41e47eb 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -154,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk_src", .parent_data = disp_cc_parent_data_4, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -168,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -188,7 +188,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_aux_clk_src", .parent_data = disp_cc_parent_data_0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -201,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -215,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -229,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, @@ -244,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -267,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -280,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_5, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -295,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -309,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .parent_data = disp_cc_parent_data_0, - .num_parents = 1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; From patchwork Thu Jan 30 21:12:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358697 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 615BF13B4 for ; Thu, 30 Jan 2020 21:13:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 359502173E for ; Thu, 30 Jan 2020 21:13:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="H/bO6vIf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727848AbgA3VM6 (ORCPT ); Thu, 30 Jan 2020 16:12:58 -0500 Received: from mail-pj1-f68.google.com ([209.85.216.68]:52943 "EHLO mail-pj1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727861AbgA3VM6 (ORCPT ); Thu, 30 Jan 2020 16:12:58 -0500 Received: by mail-pj1-f68.google.com with SMTP id ep11so1873898pjb.2 for ; Thu, 30 Jan 2020 13:12:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bnJgc/FH2tRmwo9j7Hkq0b5BbPKm+LlMQmLAnIUjm2Q=; b=H/bO6vIffifBCudP9N200bY/Or2g+Y0IAecMhq+gG+YskF1CgYruXGZCoxipwhmNL0 fnmwVNYAOifYRGjm9XPsrrxf6IHe8sALyko1GFBUNiN7PPpjWUbYIu1W/YVULiKo3nnw Ql5ygIIgf74z3ULv78uLeVlOfnRNavpKGS2OI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bnJgc/FH2tRmwo9j7Hkq0b5BbPKm+LlMQmLAnIUjm2Q=; b=Twn4tcnOyiZCg7Mg8Zm//TNVu0q7J5Ugp0oLpjAmEDj7JHj3wdDbcz9tEHlIZW3Xt/ 48exvVhLqpacwIBgSmmDaZ/X0yXDzognTeAY6vYpVnWE67aoj7ug1fxbgQpKyiGgeRu3 Y3xmfLsp8DRZ7gwEzqW96ySyO03j23hZZws00bWCU7mV2eEr0uzvBuUUxXEU2dOjfmOM QwMusU50Cdjhe28babTTQ+nIri6eEkX4y645IhIpk64j0EKU4FydTFU/SDhIwS3pMTTq gZNNO8aNgpHzzwDIYdx8IUFWWoR3L/ypqXkg+eWArEy7JJ/ZSZxeSKwTopZ7WXLZMgnF q9Rg== X-Gm-Message-State: APjAAAX030UFnEztzyzqtnUhInIMTqs5+fregifmkVYR7Tb4PjrFNsQH qdmdtMiEsnI9ouqT4SJTJ3wkwQ== X-Google-Smtp-Source: APXvYqzcHZRVmyzQ6OSKrv5hz1WJBF6SZ2evMlAMWrcWJZ/3hsfsysDQs40yaynaK29f7TbrGlz5Kg== X-Received: by 2002:a17:90a:21c7:: with SMTP id q65mr8265137pjc.8.1580418777338; Thu, 30 Jan 2020 13:12:57 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:12:56 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 07/15] dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998 Date: Thu, 30 Jan 2020 13:12:23 -0800 Message-Id: <20200130131220.v3.7.I513cd73b16665065ae6c22cf594d8b543745e28c@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The qcom,gpucc bindings had a few problems with them: 1. When things were converted to yaml the name of the "gpll0 main" clock got changed from "gpll0" to "gpll0_main". Change it back for msm8998. 2. Apparently there is a push not to use purist aliases for clocks but instead to just use the internal Qualcomm names. For sdm845 and sc7180 (where the drivers haven't already been changed) move in this direction. Things were also getting complicated harder to deal with by jamming several SoCs into one file. Splitting simplifies things. Fixes: 5c6f3a36b913 ("dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings") Signed-off-by: Douglas Anderson --- Changes in v3: - Added pointer to inlude file in description. - Everyone but msm8998 now uses internal QC names. - Fixed typo grpahics => graphics - Split bindings into 3 files. Changes in v2: - Patch ("dt-bindings: clock: Fix qcom,gpucc...") new for v2. .../devicetree/bindings/clock/qcom,gpucc.yaml | 72 ------------------- .../bindings/clock/qcom,msm8998-gpucc.yaml | 66 +++++++++++++++++ .../bindings/clock/qcom,sc7180-gpucc.yaml | 72 +++++++++++++++++++ .../bindings/clock/qcom,sdm845-gpucc.yaml | 72 +++++++++++++++++++ 4 files changed, 210 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml deleted file mode 100644 index 622845aa643f..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ /dev/null @@ -1,72 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Graphics Clock & Reset Controller Binding - -maintainers: - - Taniya Das - -description: | - Qualcomm grpahics clock control module which supports the clocks, resets and - power domains. - -properties: - compatible: - enum: - - qcom,msm8998-gpucc - - qcom,sc7180-gpucc - - qcom,sdm845-gpucc - - clocks: - minItems: 1 - maxItems: 3 - items: - - description: Board XO source - - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src) - - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src) - - clock-names: - minItems: 1 - maxItems: 3 - items: - - const: xo - - const: gpll0_main - - const: gpll0_div - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - -required: - - compatible - - reg - - clocks - - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - -examples: - # Example of GPUCC with clock node properties for SDM845: - - | - clock-controller@5090000 { - compatible = "qcom,sdm845-gpucc"; - reg = <0x5090000 0x9000>; - clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>; - clock-names = "xo", "gpll0_main", "gpll0_div"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; -... diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml new file mode 100644 index 000000000000..482e36b74cea --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,msm8998-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998 + +maintainers: + - Taniya Das + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on MSM8998. + + See also dt-bindings/clock/qcom,gpucc-msm8998.h. + +properties: + compatible: + const: qcom,msm8998-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src) + + clock-names: + items: + - const: xo + - const: gpll0 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include + #include + clock-controller@5065000 { + compatible = "qcom,msm8998-gpucc"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x05065000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>; + clock-names = "xo", "gpll0"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml new file mode 100644 index 000000000000..de42d68162d9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,sc7180-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding for SC7180 + +maintainers: + - Taniya Das + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on SC7180. + + See also dt-bindings/clock/qcom,gpucc-sc7180.h. + +properties: + compatible: + const: qcom,sc7180-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + clock-names: + items: + - const: bi_tcxo + - const: gcc_gpu_gpll0_clk_src + - const: gcc_gpu_gpll0_div_clk_src + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include + #include + clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml new file mode 100644 index 000000000000..45fb7eb2dc34 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,sdm845-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding for SDM845 + +maintainers: + - Taniya Das + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on SDM845. + + See also dt-bindings/clock/qcom,gpucc-sdm845.h. + +properties: + compatible: + const: qcom,sdm845-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + clock-names: + items: + - const: bi_tcxo + - const: gcc_gpu_gpll0_clk_src + - const: gcc_gpu_gpll0_div_clk_src + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include + #include + clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... From patchwork Thu Jan 30 21:12:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358699 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C01913B4 for ; Thu, 30 Jan 2020 21:13:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1A47A214D8 for ; Thu, 30 Jan 2020 21:13:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="dy/9ETdz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727878AbgA3VNB (ORCPT ); Thu, 30 Jan 2020 16:13:01 -0500 Received: from mail-pl1-f193.google.com ([209.85.214.193]:43172 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727874AbgA3VNA (ORCPT ); Thu, 30 Jan 2020 16:13:00 -0500 Received: by mail-pl1-f193.google.com with SMTP id p11so1816821plq.10 for ; Thu, 30 Jan 2020 13:12:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hdWC3RQmqbqeEYneGWU8AA2fWnLGYvTK7uGX6EESI4I=; b=dy/9ETdzg2IbK5MHT6jzlfGoU65H981Bgza6oumaV2dvTW7WTD77C+7h450M+iIWG1 frkj33KT7yrQ36Ltw7P3SKdZOsWRKWFowFU/X5e7C9Lk3ymX/hw31CTNdHl3u+JD80Kk fq/0dG4QyBkNXq4+c3RN+kXkwoIZhHvdlRtSA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hdWC3RQmqbqeEYneGWU8AA2fWnLGYvTK7uGX6EESI4I=; b=QOK9iSvmTKNmbp76NtRG1pWq258/7jvFf/4sq37j1C4pI2w8jktAnonujUunqV03cv KcoWxGJIxWYQcLOkhShFMkDuScBLUNaNOCZRBzvDnE8P62D2qCRCmfq/AKvOouapXFif dsHlxSu2LaptnL4JfQn5F0iMn2Gs8KyUQYUh+SnYmZxR+4OUUkhSZPkSjIpq3rYbIMSp RoYDfonKmT2OYHENlmUkMR8KV0YRXfmF9FYzRcdWvDWYeggAsf3ZIftnTSkDw42RKBHg p6jCQEnT4yyn6qs0aGiyp7uDEvoCefOpB8Dwyxqs7KAOWTyxXprWkxBNIO+JWD/iJI3N z6Mw== X-Gm-Message-State: APjAAAU2cJvty/35cMSoex8y6otv+GnN8fxn7abw2wupjfk3hBV52ed/ mohNRmXgCXQFi3Jy42EWMyXR/w== X-Google-Smtp-Source: APXvYqzgj3qg6+ijNWRHM27hvrG2XLl3NbrODk5PrDiJH+sgQRp3aGWygTi6vlVx1xdxxUa8jCdRkA== X-Received: by 2002:a17:90a:9c1:: with SMTP id 59mr8088935pjo.65.1580418778610; Thu, 30 Jan 2020 13:12:58 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:12:58 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 08/15] arm64: dts: qcom: sdm845: Add missing clocks / fix names on the gpucc Date: Thu, 30 Jan 2020 13:12:24 -0800 Message-Id: <20200130131220.v3.8.If8596faf02408cef4bb9f52296b911eb9ba49287@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We're transitioning over to requiring the Qualcomm GPU Clock Controller to specify all the input clocks. Let's add them for sdm845. As part of this we've decided that the xo clock should be referred to in the bindings as "bi_tcxo". Change the dts. NOTE: Until the Linux driver for sdm845's gpucc is updated, these clocks will not actually be used in Linux. It will continue to use global clock names to match things up. Of course, Linux didn't use the old "xo" clock anyway. Signed-off-by: Douglas Anderson --- Changes in v3: - Unlike in v2, use internal name instead of purist name. Changes in v2: - Patch ("arm64: dts: qcom: sdm845: Add...gpucc") new for v2. arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0985813fee50..35d7fcbda43c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1903,8 +1903,12 @@ gpucc: clock-controller@5090000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; }; stm@6002000 { From patchwork Thu Jan 30 21:12:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358729 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 668F114D5 for ; Thu, 30 Jan 2020 21:13:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 45039214D8 for ; Thu, 30 Jan 2020 21:13:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="klIlRQrE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727860AbgA3VNj (ORCPT ); Thu, 30 Jan 2020 16:13:39 -0500 Received: from mail-pl1-f194.google.com ([209.85.214.194]:35204 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727869AbgA3VNA (ORCPT ); Thu, 30 Jan 2020 16:13:00 -0500 Received: by mail-pl1-f194.google.com with SMTP id g6so1829476plt.2 for ; Thu, 30 Jan 2020 13:13:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u0d18Tiuc91wq0r+MI9js+qIt5jAuoFT35gTcYK6AC4=; b=klIlRQrEupGrGJaAibFlNRXGEU7pN3PEjN1xY78etxsnqd1dBV7gc6YiaviQykxEdF ysJqNmaWiu1wXQhyiujlYkHDnH51ZWAE6MF1vFwS3I0V+VUEzXFv7rtUBjewDYfHKU1h 1TeVPKXD8wMWBFYZSy2SlgTdHFsDDjZzzmp3Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u0d18Tiuc91wq0r+MI9js+qIt5jAuoFT35gTcYK6AC4=; b=KFYq9dNwaNU5v4h2kxACkEfZSx4yzUAjXBGpM5bUn/2imVaqay/YU69z7JB/xxKqcB KKAaVe1Jezf/ZsvLpMWzsc3x+RYvZYy8nJm09Phht5xvlx3xwsmGFc435fV7FVY1EH9m XzoZ9o/a455okbDmHUEykcAr+3XrXKdFs1Kn2ZH7Tv1Zb83Cpw6sCVJZRNy+t2cWL4OD fnkQN2d4fUYZ4Y+36wt6GoCa0VeBjR9eibdwcKqTzZ9mBy8Fu+knLGsMcEZTcD957MB7 gnA7GJIMtORZno6adX3qwZuk8IBoVDoyCQ8rZotNwfbC73TQQZ+6uxmKaPUkqb5Mig5C dL1Q== X-Gm-Message-State: APjAAAV/vvPyoLbBRB0ja+VNHYrxWWAUX9uIcAtXNSmjOFkx4uwqOyov N9TD7BV7ndJqV0d7HnTLrT2N9Q== X-Google-Smtp-Source: APXvYqygb69oTlZosR/4ds61je0W4fNhc+VglR47ec88QD802ZBNusUvY9xwHsgh2q0Dk9KdFc80dA== X-Received: by 2002:a17:90a:3a86:: with SMTP id b6mr8102846pjc.96.1580418779627; Thu, 30 Jan 2020 13:12:59 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:12:59 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Stephen Boyd , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v3 09/15] clk: qcom: Get rid of the test clock for gpucc-sc7180 Date: Thu, 30 Jan 2020 13:12:25 -0800 Message-Id: <20200130131220.v3.9.I6d5276b768f6593053be036a3e70cce298d39f0c@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Signed-off-by: Douglas Anderson --- Changes in v3: - Patch ("clk: qcom: Get rid of the test...gpucc-sc7180") split out for v3. Changes in v2: None drivers/clk/qcom/gpucc-sc7180.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c index ec61194cceaf..c88f00125775 100644 --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c @@ -60,7 +60,6 @@ static const struct parent_map gpu_cc_parent_map_0[] = { { P_GPU_CC_PLL1_OUT_MAIN, 3 }, { P_GPLL0_OUT_MAIN, 5 }, { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gpu_cc_parent_data_0[] = { @@ -68,7 +67,6 @@ static const struct clk_parent_data gpu_cc_parent_data_0[] = { { .hw = &gpu_cc_pll1.clkr.hw }, { .fw_name = "gcc_gpu_gpll0_clk_src" }, { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { @@ -86,7 +84,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .parent_data = gpu_cc_parent_data_0, - .num_parents = 5, + .num_parents = 4, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, From patchwork Thu Jan 30 21:12:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358723 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F028414D5 for ; Thu, 30 Jan 2020 21:13:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CDE48217BA for ; Thu, 30 Jan 2020 21:13:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="YACiuw3I" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727881AbgA3VNe (ORCPT ); Thu, 30 Jan 2020 16:13:34 -0500 Received: from mail-pj1-f66.google.com ([209.85.216.66]:34826 "EHLO mail-pj1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727874AbgA3VNB (ORCPT ); Thu, 30 Jan 2020 16:13:01 -0500 Received: by mail-pj1-f66.google.com with SMTP id q39so1887097pjc.0 for ; Thu, 30 Jan 2020 13:13:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EhLkjJnc7Tvg6c+D+i1atdDK7ul7OoMcFLbEV57smwA=; b=YACiuw3I6aQW0okCZOZkbpI2LnSUUT86cYe3PTxGtY1G13lrknoeNOR2rW5w5eOray ZZ2JTVB/LmgPEBfvXGBqo39b8Qkg6WJIwUB+a9Yube+JSCvieaBgBoPpPfRoshZiJ6Xt Z7qK51vcg20SjzF2Bx9aXYpj5/suCssdR4bZ4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EhLkjJnc7Tvg6c+D+i1atdDK7ul7OoMcFLbEV57smwA=; b=OwUhB/2JHFAVN4m2Ytdek87ufv2531K7ydGFuSni4xyzuZLwNK1TOd1VmLdmztQk81 MND48iLICgyn1cCItpdoFtfhzdTLqk4cpyQzvDnwGSB+LsSQ/D79JgRDSaGvEUkGW1px zRZCCW63hWk78NT2xj/88D7aem+zMx7R9NcOschDj6lruHtdNIHRoinzf5wp+bN6t/kp aI8TmLHv9y+dYQW/wgJNsliF20C0GwIoai3/u4tcVGCkTt1yl/SxCFYbW28fXkv7ksvw +XK9u8NSrQNBivRovijLsjb3V7zLuSXwOXEOYgSFVM1Ok+Hm9sMVXqSRARexBVuT4McL gEBA== X-Gm-Message-State: APjAAAWLeOPc0dxoLlDfgJU0aYNo+r4APiRMxIOsrnKXWpv0OMl4cY6d GMjDQGTUL6ZnN0mFLgYEJbT2IA== X-Google-Smtp-Source: APXvYqyNswtUeRfxu8pkGT+lb94+9OrthlA8QLayMFGUxze8/lozqOfD3iWfnthyHmjjkmKqN5OnLQ== X-Received: by 2002:a17:90a:8915:: with SMTP id u21mr8226951pjn.87.1580418780837; Thu, 30 Jan 2020 13:13:00 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:13:00 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v3 10/15] clk: qcom: Use ARRAY_SIZE in gpucc-sc7180 for parent clocks Date: Thu, 30 Jan 2020 13:12:26 -0800 Message-Id: <20200130131220.v3.10.I3bf44e33f4dc7ecca10a50dbccb7dc082894fa59@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It's nicer to use ARRAY_SIZE instead of hardcoding. Had we always been doing this it would have prevented a previous bug. See commit 74c31ff9c84a ("clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6"). Signed-off-by: Douglas Anderson --- Changes in v3: - Patch ("clk: qcom: Use ARRAY_SIZE in gpucc-sc7180...") split out for v3. Changes in v2: None drivers/clk/qcom/gpucc-sc7180.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c index c88f00125775..a96c0b945de2 100644 --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c @@ -84,7 +84,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .parent_data = gpu_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, From patchwork Thu Jan 30 21:12:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358719 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0349139A for ; Thu, 30 Jan 2020 21:13:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 748D5214DB for ; Thu, 30 Jan 2020 21:13:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="NbNW2kLh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727988AbgA3VNW (ORCPT ); Thu, 30 Jan 2020 16:13:22 -0500 Received: from mail-pl1-f193.google.com ([209.85.214.193]:40570 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727895AbgA3VNC (ORCPT ); Thu, 30 Jan 2020 16:13:02 -0500 Received: by mail-pl1-f193.google.com with SMTP id y1so1815322plp.7 for ; Thu, 30 Jan 2020 13:13:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Fol0JJk4IblLpT4hiUDWb+r71DYlQYGNjU+sPWvrVtI=; b=NbNW2kLhoU4SqcB8NO5LF/J1dTq+k84S1Xp8/bVNLPdrYCRbW/z2dE1bCXWiDJCT+n e4ZDPQH601UTR7Z8wKk0aukfftdiMMVtl5MnOaEvYHxL0LUlBI2oHGBD78X0hf6FgEJ2 +dWdI+cN6qTj7z3WF5T8+bF9+BN8T+hIlaNrQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Fol0JJk4IblLpT4hiUDWb+r71DYlQYGNjU+sPWvrVtI=; b=Ve0vBz93ba4JymB+PPqQswjleRxmggIya2QRXDoMJKJkWQ3FTzknHq792sVie9Tbc5 Lttgyb+ibsQzUGZc5fZnzkWEJGbD5cBe1t3H4nNIBGIxYAbR5hhR6D5yZZMEPg9fNyyd 9zFrtpz6Jro501ztpxbQue0J4UKvhfi/qYpvu3vlbAgG1Cdxfx9KVIQrVHF8YC4Pk8iw aQsBpiJbH3UDWxO0mSuXyHwP7n/+AESvKyz4YcesaWHx2KyvZp/O88JX7HZgoNKf3Lev q3JQO/s3MhNJSctNxOgpzOOHJ2t07Opw8yWhTMjiqYRDExjxv1c9i31GmbMojlX8++5S pR8g== X-Gm-Message-State: APjAAAWOTqTeIrxPYsr04Cs2U/aixHVFXIrtbkZdTOOGJdr7tsHaAP4o oXjpFjxFlx4JjlNrNhqGmizW+w== X-Google-Smtp-Source: APXvYqy2P3oKHw/5gmuRoNPGnGaALGU6i55k3M8QnYtzLdPZgM3doZOHhvvWoincZ28UWeE0iBIc7w== X-Received: by 2002:a17:90a:a60c:: with SMTP id c12mr8400886pjq.28.1580418781917; Thu, 30 Jan 2020 13:13:01 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:13:01 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 11/15] dt-bindings: clock: Cleanup qcom,videocc bindings for sdm845/sc7180 Date: Thu, 30 Jan 2020 13:12:27 -0800 Message-Id: <20200130131220.v3.11.I27bbd90045f38cd3218c259526409d52a48efb35@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This makes the qcom,videocc bindings match the recent changes to the dispcc and gpucc. 1. Switched to using "bi_tcxo" instead of "xo". 2. Adds a description for the XO clock. Not terribly important but nice if it cleanly matches its cousins. 3. Updates the example to use the symbolic name for the RPMH clock and also show that the real devices are currently using 2 address cells / size cells and fixes the spacing on the closing brace. 4. Split into 2 files. In this case they could probably share one file, but let's be consistent. Signed-off-by: Douglas Anderson Reviewed-by: Rob Herring --- Changes in v3: - Added include file to description. - Split videocc bindings into 2 files. - Unlike in v2, use internal name instead of purist name. Changes in v2: - Patch ("dt-bindings: clock: Cleanup qcom,videocc") new for v2. .../bindings/clock/qcom,sc7180-videocc.yaml | 63 +++++++++++++++++++ ...,videocc.yaml => qcom,sdm845-videocc.yaml} | 27 ++++---- 2 files changed, 77 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml rename Documentation/devicetree/bindings/clock/{qcom,videocc.yaml => qcom,sdm845-videocc.yaml} (60%) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml new file mode 100644 index 000000000000..f12ec56737e8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,sc7180-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller Binding for SC7180 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module which supports the clocks, resets and + power domains on SC7180. + + See also dt-bindings/clock/qcom,videocc-sc7180.h. + +properties: + compatible: + const: qcom,sc7180-videocc + + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: bi_tcxo + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include + clock-controller@ab00000 { + compatible = "qcom,sc7180-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml similarity index 60% rename from Documentation/devicetree/bindings/clock/qcom,videocc.yaml rename to Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml index 43cfc893a8d1..60300f5ab307 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml @@ -1,30 +1,31 @@ # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/qcom,videocc.yaml# +$id: http://devicetree.org/schemas/bindings/clock/qcom,sdm845-videocc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Video Clock & Reset Controller Binding +title: Qualcomm Video Clock & Reset Controller Binding for SDM845 maintainers: - Taniya Das description: | Qualcomm video clock control module which supports the clocks, resets and - power domains. + power domains on SDM845. + + See also dt-bindings/clock/qcom,videocc-sdm845.h. properties: compatible: - enum: - - qcom,sc7180-videocc - - qcom,sdm845-videocc + const: qcom,sdm845-videocc clocks: - maxItems: 1 + items: + - description: Board XO source clock-names: items: - - const: xo + - const: bi_tcxo '#clock-cells': const: 1 @@ -48,15 +49,15 @@ required: - '#power-domain-cells' examples: - # Example of VIDEOCC with clock node properties for SDM845: - | + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; - reg = <0xab00000 0x10000>; - clocks = <&rpmhcc 0>; - clock-names = "xo"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - }; + }; ... From patchwork Thu Jan 30 21:12:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358711 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EA03713B4 for ; Thu, 30 Jan 2020 21:13:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C7F51214D8 for ; Thu, 30 Jan 2020 21:13:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="YIqpV+Fz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727859AbgA3VNS (ORCPT ); Thu, 30 Jan 2020 16:13:18 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:44321 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727912AbgA3VNE (ORCPT ); Thu, 30 Jan 2020 16:13:04 -0500 Received: by mail-pg1-f194.google.com with SMTP id x7so2274871pgl.11 for ; Thu, 30 Jan 2020 13:13:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oJDKOmB7ZFL6XZ61wjwygv6X2jByNoioH7bgGcPY36A=; b=YIqpV+FzNGMsFaC1+rnxfdxHhv6OUiI0aoNfYn+O3ug3BwCbm+0mEJ55S3s5jZxQSG LeR4USvSFVcUSzZwJClMGn6TgSWEZDmmLjtbG2OLiwpkxREIF7FPVyyEnr1a8yk+mxAp 8j3aj4RBtb+b/hdc19rzKKWlw1AbibAd2rCgo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oJDKOmB7ZFL6XZ61wjwygv6X2jByNoioH7bgGcPY36A=; b=LDUsIeIuSzv1OG2AHe1cuEK+UdJFRRwEd6HFa2tBKRPBhWwfDrb7w2ivZPOLB77Prg 4cfjgPN20yj9p0LLVbmhCvxIpadWYgmjC02nxhe1XyfEUsJGlR2RmQ17cR1J9SKyUTt4 PE3M7TQad0fC1w6x806WnQu9fB50xkTLjtHGLrx7yhwTA5EBWqpSQvoeXvW0t19rIupj 7YKepGO6Oyw2FjJefxm77WLYveLlrV6TGCA5Agjnv48leQWD3Sfo2CO8sqBqeMkTtemI qxcaYPh5nfXMNhQlhNXwrN1sBUykNiB5sb8aqcTuJqFvpUjSd77boycyaNNYrSKak310 Z/qQ== X-Gm-Message-State: APjAAAVyjbMEl1Z/GluqibzKd8tzNzsuM1I8e5pb43vpkNUPzP27dUrs 4VSa6PuT2ofiDRcMm7Z+gGJh0Q== X-Google-Smtp-Source: APXvYqz7AldunlhVmPPd9oO5+HsNHM8r55oT4X3X2YZ/8kxsmZsDSvIeJwiLAumLcuW3X/3gWvFGrA== X-Received: by 2002:a63:1f0c:: with SMTP id f12mr6850351pgf.247.1580418782948; Thu, 30 Jan 2020 13:13:02 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:13:02 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Stephen Boyd , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v3 12/15] clk: qcom: Get rid of the test clock for videocc-sc7180 Date: Thu, 30 Jan 2020 13:12:28 -0800 Message-Id: <20200130131220.v3.12.Ifd19a2701a102ec9f04e61a09345198383a9e937@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Signed-off-by: Douglas Anderson --- Changes in v3: - Patch ("clk: qcom: Get rid of the test...videocc-sc7180") new for v3. Changes in v2: None drivers/clk/qcom/videocc-sc7180.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c index 76add30024aa..653fc4e6bb6f 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -50,13 +50,11 @@ static struct clk_alpha_pll video_pll0 = { static const struct parent_map video_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_VIDEO_PLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data video_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, { .hw = &video_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { @@ -78,7 +76,7 @@ static struct clk_rcg2 video_cc_venus_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "video_cc_venus_clk_src", .parent_data = video_cc_parent_data_1, - .num_parents = 3, + .num_parents = 2, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, From patchwork Thu Jan 30 21:12:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358713 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8EE8213B4 for ; Thu, 30 Jan 2020 21:13:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6B8A8214D8 for ; Thu, 30 Jan 2020 21:13:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="MYxAB1ed" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727975AbgA3VNR (ORCPT ); Thu, 30 Jan 2020 16:13:17 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:45487 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727909AbgA3VNE (ORCPT ); Thu, 30 Jan 2020 16:13:04 -0500 Received: by mail-pg1-f193.google.com with SMTP id b9so2273438pgk.12 for ; Thu, 30 Jan 2020 13:13:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ff1yK3ORakl74BFXMoZy6txxvHuVUK88xYRXUF98dsA=; b=MYxAB1edcjlV6r/3BRKpapRWzUXehQ29kOd29k5MBGHzND9GlxROrJQyIw5k5YFgF6 B7IaftbP1+NpMz7JGzE9cl/pb+g7t3+X+0TQQLBVsjavJtf3nn+Zo7kxntoKd54vMw20 S8UFTnVFKywHQ4kUI+2pKV242C4MwnqMEu2PU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ff1yK3ORakl74BFXMoZy6txxvHuVUK88xYRXUF98dsA=; b=hbVh2TZ/3QzkTwwaynhR0Ef0oMC2Kv7GJRDY0OqY7Na4SbIn7r/9pdEp0y9HMj3iWe Q10ugbij3nIjrMNMsp0bPKJ13zf7FZHVW2m4Xoez0ChYxJ3jO0f0/7w4+5EXifGW2nM5 jlXMb4aSbbMsbjfhj7wlHXXV64ym+MtLpJ4jvGQfvGEjlTYnORTSF9e/JUMMC4URKw/R TAfc7L5Lwk0EvzbV0uOXW1u4yJJln/t4CnzTHWGTcJXY6gDZD0NJoF57r4xT3mJNf66f kZWAt9rX36n8ysKA2SYoAaFhM1eXQkQoUh/g1AjlCJmDujJFPxTkXoVj3o1s00j52IFX qOlA== X-Gm-Message-State: APjAAAX9QCmgFcXQDLMWvrBz3kR+7TvGJGCU/XTYjxYmi7XwDZfp2BxA HALHq7Wfrrv7pzwcs3XYH3tMlg== X-Google-Smtp-Source: APXvYqyPIzl14PPWapV9S3IqahdjaaFm9DzOevoItp7H+rnGagyA7gSPikF2rQBRt3T+MZi3CIWMTw== X-Received: by 2002:a63:5fce:: with SMTP id t197mr6742454pgb.173.1580418784027; Thu, 30 Jan 2020 13:13:04 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.13.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:13:03 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v3 13/15] clk: qcom: Use ARRAY_SIZE in videocc-sc7180 for parent clocks Date: Thu, 30 Jan 2020 13:12:29 -0800 Message-Id: <20200130131220.v3.13.If37e4b1b5553ac9db5ea51e84a6eec286cdf209e@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It's nicer to use ARRAY_SIZE instead of hardcoding. Had we always been doing this it would have prevented a previous bug. See commit 74c31ff9c84a ("clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6"). Signed-off-by: Douglas Anderson --- Changes in v3: - Patch ("clk: qcom: Use ARRAY_SIZE in videocc-sc7180...") new for v3. Changes in v2: None drivers/clk/qcom/videocc-sc7180.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c index 653fc4e6bb6f..c363c3cc544e 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -76,7 +76,7 @@ static struct clk_rcg2 video_cc_venus_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "video_cc_venus_clk_src", .parent_data = video_cc_parent_data_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(video_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, From patchwork Thu Jan 30 21:12:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358707 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67D93139A for ; Thu, 30 Jan 2020 21:13:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46771214D8 for ; Thu, 30 Jan 2020 21:13:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="bymF+xNl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727913AbgA3VNG (ORCPT ); Thu, 30 Jan 2020 16:13:06 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:33138 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727920AbgA3VNF (ORCPT ); Thu, 30 Jan 2020 16:13:05 -0500 Received: by mail-pg1-f196.google.com with SMTP id 6so2310785pgk.0 for ; Thu, 30 Jan 2020 13:13:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x+d19VC5GqGDrwah0h0bGrXkFmaAY9eB/iS9cICScuo=; b=bymF+xNlsIGFO5AVvycBkMmLMDI0N9JxG/Bf9e+DUzdYKaTxQCQn6cCxkA2xlU1MGQ jL3Ocqww4UXSqXcwOpEf4YhwjhY9GQoCIffmfnD0X+Hl0RDO8Cd9rWzI/I6lKgK9KgYt di04A74nfJkQ3bC6mWJji/hSv5fOrYlVaKmNA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x+d19VC5GqGDrwah0h0bGrXkFmaAY9eB/iS9cICScuo=; b=MnOGjSOO9ffG1rGzxVLEQpyJqUI54jakR8EKnA+eBxLTS0LlI4W6q1O0f6yQib6vQI BfCNLaw3H5avE3dmT2v0VsWr0VbzNwiYpEKi5CMwrnZsXU4gQ9/9IriN/gWV2py39r+n TpDyyWqU5f0u7BpIlLmIGt+La3mTyETdKy3XeSMo2fR8r/J/85HQTwtKC79KYIEcrjLL EnnRFQ6Ug9hjbucPOY3mnBAFcR4uJ+YssuBJy08+dbaAymtIywFG/CxeKEnCjBjvPxCK 1Tg5hVnCSGd5mspSmActYK6HlxW9sVWKTzIa59Ka5ueho44GC+jMBCHO8wI3mO+irAcc OmQA== X-Gm-Message-State: APjAAAWUv2W9d37hXc662ENt25GXOb775S2p99Yd1yGNir3N205trZVy rPIiZUV/Ck09hjZQsMJzsEVCgg== X-Google-Smtp-Source: APXvYqyT/IU+WqiG933tteXMVt0zK6C+GD/fPoh8GuJLGi5bjbnMq8BTFHzIssXi/t0dghRGHOgoYw== X-Received: by 2002:a63:3c08:: with SMTP id j8mr6664743pga.223.1580418785098; Thu, 30 Jan 2020 13:13:05 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:13:04 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 14/15] arm64: dts: qcom: sdm845: Add the missing clock on the videocc Date: Thu, 30 Jan 2020 13:12:30 -0800 Message-Id: <20200130131220.v3.14.Id0599319487f075808baba7cba02c4c3c486dc80@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We're transitioning over to requiring the Qualcomm Video Clock Controller to specify all the input clocks. Let's add the one input clock for the videocc for sdm845. NOTE: Until the Linux driver for sdm845's video is updated, this clock will not actually be used in Linux. It will continue to use global clock names to match things up. Signed-off-by: Douglas Anderson --- Changes in v3: - Unlike in v2, use internal name instead of purist name. Changes in v2: - Patch ("arm64: dts: qcom: sdm845: Add...videocc") new for v2. arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 35d7fcbda43c..3ad08d9deb54 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2607,6 +2607,8 @@ video-core1 { videocc: clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; From patchwork Thu Jan 30 21:12:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11358703 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BF03D139A for ; Thu, 30 Jan 2020 21:13:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 92A1E214D8 for ; Thu, 30 Jan 2020 21:13:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="YztztHo+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727929AbgA3VNO (ORCPT ); Thu, 30 Jan 2020 16:13:14 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:36221 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727935AbgA3VNI (ORCPT ); Thu, 30 Jan 2020 16:13:08 -0500 Received: by mail-pf1-f196.google.com with SMTP id 185so2136605pfv.3 for ; Thu, 30 Jan 2020 13:13:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Oa49p/xGTn6NCKmNAd8eGM0hUYKRobdCqjFRXtL8/kA=; b=YztztHo+5GQxLT621C7Rqngv72wMhREmQYp/vsbj0VtWWHVT1+KSLTkNKq3nPnnT77 u96ZJxht7JRHvwCE695YNRG5Uha2O2igcMyHdsHpf0hmrv3tbv/L2mWXHlqFgY431VFB sFrWLJFUmpQYg22ekzG2C7G5D1oa04m585Vtc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Oa49p/xGTn6NCKmNAd8eGM0hUYKRobdCqjFRXtL8/kA=; b=gD2W1I1EZl7XBIqMBsWok+lLStpoK3m1fuLCtFQTToX25/MwAalUoTQp1JNQ7m4b7q CdY+vTSrhqNSEm5DBAKnAS08X0h2F0v+wX5Qtzvrsdwx9Rr2M6yoRnxuHpznYQhXSavw Gyy9hQjFeOTnHKuIGlYP4nPzW8ZVVeeG4n/a54mZZsPlrNiJzQ1PSGvnAIalpdtvLvVB eNHdNgncB2xKLRp3Z0YqbK6RitCsOxHdg9XatVjJ42X7Atrl8Oqhza/yOO53guMNp279 SfSrIx8SoysY12FNtt0KzqNmmyE2WH3nFC77iFuDaACaLvmMDChDWaW1xeqiHdU94BE7 drnA== X-Gm-Message-State: APjAAAUI0B3XtFk+EFC7L6AYqxt4EnJ8ZWJ6lTYBj64KjyfXchC3jlvS 5sjBvmEAgSf1pcqDgGH/g+90FQ== X-Google-Smtp-Source: APXvYqzzw2CG5kff+mpG3Nv7sadrfFm8uoc1EhB2TT6G2I2DqhJX1YdC+8eq25u2MR3IrmdXmtro/w== X-Received: by 2002:a62:1d07:: with SMTP id d7mr6747690pfd.159.1580418786161; Thu, 30 Jan 2020 13:13:06 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:13:05 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 15/15] arm64: dts: sc7180: Add clock controller nodes Date: Thu, 30 Jan 2020 13:12:31 -0800 Message-Id: <20200130131220.v3.15.I1a4b93fb005791e29a9dcf288fc8bd459a555a59@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Taniya Das Add the display, video & graphics clock controller nodes supported on SC7180. NOTE: the dispcc needs input clocks from various PHYs that aren't in the device tree yet. For now we'll leave these stubbed out with <0>, which is apparently the magic way to do this. These clocks aren't really "optional" and this stubbing out method is apparently the best way to handle it. Signed-off-by: Taniya Das Signed-off-by: Douglas Anderson --- Changes in v3: - Added videocc include file. - Unlike in v2, use internal name instead of purist name. Changes in v2: - Added includes - Changed various parent names to match bindings / driver arch/arm64/boot/dts/qcom/sc7180.dtsi | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8011c5fe2a31..57ff5e0f7ae6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -5,8 +5,11 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#include #include +#include #include +#include #include #include #include @@ -1039,6 +1042,20 @@ pinmux { }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -1151,6 +1168,36 @@ usb_1_dwc3: dwc3@a600000 { }; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,sc7180-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc7180-dispcc"; + reg = <0 0x0af00000 0 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;