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Fri, 31 Jan 2020 01:09:49 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 1/2] !fixup "hw/misc: Add limited support for AVR power device" Date: Fri, 31 Jan 2020 02:09:40 +0100 Message-Id: <20200131010941.10636-2-philmd@redhat.com> In-Reply-To: <20200131010941.10636-1-philmd@redhat.com> References: <1580428993-4767-1-git-send-email-aleksandar.markovic@rt-rk.com> <20200131010941.10636-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: qLjYAn62PW2n-jiAxeKJoA-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aleksandar Markovic , Michael Rolnik , Aleksandar Markovic , =?utf-8?q?Alex_Benn=C3=A9e?= , Aleksandar Markovic Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" - convert DB_PRINT() to trace-events - fix style/indentation Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- hw/misc/avr_power.c | 17 +++++++++-------- hw/misc/trace-events | 4 ++++ 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/hw/misc/avr_power.c b/hw/misc/avr_power.c index 598bc7279c..65ff7c4405 100644 --- a/hw/misc/avr_power.c +++ b/hw/misc/avr_power.c @@ -27,9 +27,7 @@ #include "qemu/log.h" #include "hw/qdev-properties.h" #include "hw/irq.h" - -#define DB_PRINT(fmt, args...) /* Nothing */ -/*#define DB_PRINT(fmt, args...) printf("%s: " fmt "\n", __func__, ## args)*/ +#include "trace.h" static void avr_mask_reset(DeviceState *dev) { @@ -48,19 +46,20 @@ static uint64_t avr_mask_read(void *opaque, hwaddr offset, unsigned size) assert(offset == 0); AVRMaskState *s = opaque; + trace_avr_power_read(s->val); + return (uint64_t)s->val; } static void avr_mask_write(void *opaque, hwaddr offset, - uint64_t val64, unsigned size) + uint64_t val64, unsigned size) { assert(size == 1); assert(offset == 0); AVRMaskState *s = opaque; uint8_t val8 = val64; - DB_PRINT("write %d to offset %d", val8, (uint8_t)offset); - + trace_avr_power_write(val8); s->val = val8; for (int i = 0; i < 8; i++) { qemu_set_irq(s->irq[i], (val8 & (1 << i)) != 0); @@ -71,7 +70,9 @@ static const MemoryRegionOps avr_mask_ops = { .read = avr_mask_read, .write = avr_mask_write, .endianness = DEVICE_NATIVE_ENDIAN, - .impl = {.max_access_size = 1} + .impl = { + .max_access_size = 1, + }, }; static void avr_mask_init(Object *dev) @@ -80,7 +81,7 @@ static void avr_mask_init(Object *dev) SysBusDevice *busdev = SYS_BUS_DEVICE(dev); memory_region_init_io(&s->iomem, dev, &avr_mask_ops, s, TYPE_AVR_MASK, - 0x01); + 0x01); sysbus_init_mmio(busdev, &s->iomem); for (int i = 0; i < 8; i++) { diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 7f0f5dff3a..f716881bb1 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -179,3 +179,7 @@ via1_rtc_cmd_pram_read(int addr, int value) "addr=%u value=0x%02x" via1_rtc_cmd_pram_write(int addr, int value) "addr=%u value=0x%02x" via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=%d value=0x%02x" via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=%d value=0x%02x" + +# avr_power.c +avr_power_read(uint8_t value) "power_reduc read value:%u" +avr_power_write(uint8_t value) "power_reduc write value:%u" From patchwork Fri Jan 31 01:09:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11358993 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2781F921 for ; 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Thu, 30 Jan 2020 20:09:55 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7DBF2182B8EB; Fri, 31 Jan 2020 01:09:54 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-34.brq.redhat.com [10.40.204.34]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 558725DA75; Fri, 31 Jan 2020 01:09:52 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 2/2] !fixup "hw/timer: Add limited support for AVR 16-bit timer peripheral" Date: Fri, 31 Jan 2020 02:09:41 +0100 Message-Id: <20200131010941.10636-3-philmd@redhat.com> In-Reply-To: <20200131010941.10636-1-philmd@redhat.com> References: <1580428993-4767-1-git-send-email-aleksandar.markovic@rt-rk.com> <20200131010941.10636-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: X3UfZ4b6McqnUKOeMJY1cQ-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sarah Harris , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aleksandar Markovic , Michael Rolnik , Aleksandar Markovic , =?utf-8?q?Alex_Benn=C3=A9e?= , Aleksandar Markovic Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Convert DB_PRINT() to trace events. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/avr_timer16.c | 25 +++++++++++++++---------- hw/timer/trace-events | 12 ++++++++++++ 2 files changed, 27 insertions(+), 10 deletions(-) diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c index 4e16afc61c..073f36aa76 100644 --- a/hw/timer/avr_timer16.c +++ b/hw/timer/avr_timer16.c @@ -36,6 +36,7 @@ #include "qemu/log.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "trace.h" /* Register offsets */ #define T16_CRA 0x0 @@ -104,7 +105,6 @@ /* Helper macros */ #define VAL16(l, h) ((h << 8) | l) #define DB_PRINT(fmt, args...) /* Nothing */ -/*#define DB_PRINT(fmt, args...) printf("%s: " fmt "\n", __func__, ## args)*/ static inline int64_t avr_timer16_ns_to_ticks(AVRTimer16State *t16, int64_t t) { @@ -168,8 +168,8 @@ static void avr_timer16_clksrc_update(AVRTimer16State *t16) if (divider) { t16->freq_hz = t16->cpu_freq_hz / divider; t16->period_ns = NANOSECONDS_PER_SECOND / t16->freq_hz; - DB_PRINT("Timer frequency %" PRIu64 " hz, period %" PRIu64 " ns (%f s)", - t16->freq_hz, t16->period_ns, 1 / (double)t16->freq_hz); + trace_avr_timer16_clksrc_update(t16->freq_hz, t16->period_ns, + (uint64_t)(1e6 / t16->freq_hz)); } } @@ -235,8 +235,7 @@ static void avr_timer16_set_alarm(AVRTimer16State *t16) t16->reset_time_ns + ((CNT(t16) + alarm_offset) * t16->period_ns); timer_mod(t16->timer, alarm_ns); - DB_PRINT("next alarm %" PRIu64 " ns from now", - alarm_offset * t16->period_ns); + trace_avr_timer16_next_alarm(alarm_offset * t16->period_ns); } static void avr_timer16_interrupt(void *opaque) @@ -253,11 +252,11 @@ static void avr_timer16_interrupt(void *opaque) return; } - DB_PRINT("interrupt, cnt = %d", CNT(t16)); + trace_avr_timer16_interrupt_count(CNT(t16)); /* Counter overflow */ if (t16->next_interrupt == OVERFLOW) { - DB_PRINT("0xffff overflow"); + trace_avr_timer16_interrupt_overflow("counter 0xffff"); avr_timer16_clock_reset(t16); if (t16->imsk & T16_INT_TOV) { t16->ifr |= T16_INT_TOV; @@ -266,12 +265,12 @@ static void avr_timer16_interrupt(void *opaque) } /* Check for ocra overflow in CTC mode */ if (mode == T16_MODE_CTC_OCRA && t16->next_interrupt == COMPA) { - DB_PRINT("CTC OCRA overflow"); + trace_avr_timer16_interrupt_overflow("CTC OCRA"); avr_timer16_clock_reset(t16); } /* Check for icr overflow in CTC mode */ if (mode == T16_MODE_CTC_ICR && t16->next_interrupt == CAPT) { - DB_PRINT("CTC ICR overflow"); + trace_avr_timer16_interrupt_overflow("CTC ICR"); avr_timer16_clock_reset(t16); if (t16->imsk & T16_INT_IC) { t16->ifr |= T16_INT_IC; @@ -367,6 +366,8 @@ static uint64_t avr_timer16_read(void *opaque, hwaddr offset, unsigned size) default: break; } + trace_avr_timer16_read(offset, retval); + return (uint64_t)retval; } @@ -378,7 +379,7 @@ static void avr_timer16_write(void *opaque, hwaddr offset, uint8_t val8 = (uint8_t)val64; uint8_t prev_clk_src = CLKSRC(t16); - DB_PRINT("write %d to offset %d", val8, (uint8_t)offset); + trace_avr_timer16_write(offset, val8); switch (offset) { case T16_CRA: @@ -475,6 +476,7 @@ static uint64_t avr_timer16_imsk_read(void *opaque, { assert(size == 1); AVRTimer16State *t16 = opaque; + trace_avr_timer16_read_imsk(offset ? 0 : t16->imsk); if (offset != 0) { return 0; } @@ -486,6 +488,7 @@ static void avr_timer16_imsk_write(void *opaque, hwaddr offset, { assert(size == 1); AVRTimer16State *t16 = opaque; + trace_avr_timer16_write_imsk(val64); if (offset != 0) { return; } @@ -498,6 +501,7 @@ static uint64_t avr_timer16_ifr_read(void *opaque, { assert(size == 1); AVRTimer16State *t16 = opaque; + trace_avr_timer16_read_ifr(offset ? 0 : t16->ifr); if (offset != 0) { return 0; } @@ -509,6 +513,7 @@ static void avr_timer16_ifr_write(void *opaque, hwaddr offset, { assert(size == 1); AVRTimer16State *t16 = opaque; + trace_avr_timer16_write_imsk(val64); if (offset != 0) { return; } diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 29fda7870e..5d9f4c93fb 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -74,3 +74,15 @@ nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" bcm2835_systmr_irq(bool enable) "timer irq state %u" bcm2835_systmr_read(uint64_t offset, uint64_t data) "timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 bcm2835_systmr_write(uint64_t offset, uint64_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 + +# avr_timer16.c +avr_timer16_read(uint8_t addr, uint8_t value) "timer16 read addr:%u value:%u" +avr_timer16_read_ifr(uint8_t value) "timer16 read addr:ifr value:%u" +avr_timer16_read_imsk(uint8_t value) "timer16 read addr:imsk value:%u" +avr_timer16_write(uint8_t addr, uint8_t value) "timer16 write addr:%u value:%u" +avr_timer16_write_ifr(uint8_t value) "timer16 write addr:ifr value:%u" +avr_timer16_write_imsk(uint8_t value) "timer16 write addr:imsk value:%u" +avr_timer16_interrupt_count(uint8_t cnt) "count: %u" +avr_timer16_interrupt_overflow(const char *reason) "overflow: %s" +avr_timer16_next_alarm(uint64_t delay_ns) "next alarm: %" PRIu64 " ns from now" +avr_timer16_clksrc_update(uint64_t freq_hz, uint64_t period_ns, uint64_t delay_s) "timer frequency: %" PRIu64 " Hz, period: %" PRIu64 " ns (%" PRId64 " us)"