From patchwork Thu Sep 27 08:59:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10617667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09336180E for ; Thu, 27 Sep 2018 09:02:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC2A62A490 for ; Thu, 27 Sep 2018 09:02:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DFB652ABC1; Thu, 27 Sep 2018 09:02:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1CA702A490 for ; Thu, 27 Sep 2018 09:02:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6oJuxn2KuCKPYocPH0jEGpkIBCVpVUDskpxHc1hCCZs=; b=G2ZbmwQgDK2Kon 6Gp53mjy3QCWf59ZbQ4goPKn2yXS3uEkA7gCZpOO92tKZARjOKxdSbvshgRUToAZfoMJL2FQua9Oi /WgGI3DXyDxDVPfDPpNLHL6QYTif90Bk0b8MTk/6UovIpfiuP4MjQGYPh/H20EqBScGpMzxT/d5Sk m+aRrZi7+nwy5e9vRMRCVVVtkztP5gf1BaHgA2nSAP7IXQDoPOAAPaVDwE6vp2K5HQWLt9zxqQ38P 3P0gLFzMJA2rbhZ7h2yw7KSvf1J8mPAVPTEmjgSdbU8G8sD/ADX5NBP7TzoifJzci0AmW4B9So88N wj8nirWjhLPJ/Wq5pgkQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g5SC2-0005OT-3D; Thu, 27 Sep 2018 09:02:42 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g5S9N-0003Va-K4 for linux-amlogic@lists.infradead.org; Thu, 27 Sep 2018 09:00:01 +0000 Received: by mail-wr1-x443.google.com with SMTP id o16so1713811wrx.2 for ; Thu, 27 Sep 2018 01:59:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LsAQ20Ytal1H8b2qr/FeCPXMRXdwE7xaiy6eZ+rHsB0=; b=VmmgG6ZbPLoQ1dAWNjqqPa8APcuni4jw6SoYy0VpvpfcQYYoEWTjy+LfoqX2zO5PQe ogbzgSq5jPX8XQiUaHXdLDeAnc4dcYOiWToaqP53/qT60u2spM/oBUDFPmwy1N7+Vmg+ 8w3SnfsReMDV83p0vd3nh5Yg07WcTwirP5AxbzbTID+0wYuchmc2VX5jNh0VXNOIXuyB nv6znipoMw0Maynt8F0G9nMcEvd6q0UxMFxyBHjor7eO4+cOxJOq7KncXQMpqsnWtXk/ xocv4IdhVyzWx9Ce4HevtTJdTGLUim3vWWZLBlGLHTTWGSjUFcOPExoRkyHbsY0Ayrn+ VgzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LsAQ20Ytal1H8b2qr/FeCPXMRXdwE7xaiy6eZ+rHsB0=; b=VjMwylnlF4i4SoLFQdEKMuXNt6e4jH83C8695S1QHBuHhoUvWIaJbIQHlEweSvgtQP N+I3mD51vXglVOs5RARVfflUWvHBwaOuVk3bCBHDhrdCS4HGvjv5Ihzx7HAdDMGVtH4u mmthCrjKVfTwhByE2l67/QvX6gNfaGRhUsdKlT3JchQncNlzQrLcDP8cGiNkjkhiynqx nWpKupkedtfq4KuT8J2CVv/oyX2l+N+GCYK1pmjvwkKo3ArivsrS05CDoj1PILtf2ZG4 OsG3dfhhSdPjOJl6lORgnjwiPyzQk2NoHiq8LGicKS1DtF6n6pKGlpYuE21ZrHTC/VGr nrgQ== X-Gm-Message-State: ABuFfoha59YV+Fvvjoi22odzACbyCRwVpw7i8+GIFQxB/nQks9VTKevM o57drapZzfZHgR0fXzb8lqmrMEAM X-Google-Smtp-Source: ACcGV634OYYoVfBfsEGWAF2EJ+9TR9nwRI8+0ZidpiL3LNMrVJ7bfgmQZQD/2DyiA9dRE9mR0zREwg== X-Received: by 2002:a5d:5002:: with SMTP id e2-v6mr4908992wrt.210.1538038772675; Thu, 27 Sep 2018 01:59:32 -0700 (PDT) Received: from blackbox.darklights.net (p200300DCD716E000F8F1A759B0FAA67F.dip0.t-ipconnect.de. [2003:dc:d716:e000:f8f1:a759:b0fa:a67f]) by smtp.googlemail.com with ESMTPSA id p64-v6sm1776483wrc.97.2018.09.27.01.59.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Sep 2018 01:59:31 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com Subject: [PATCH 1/2] clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table Date: Thu, 27 Sep 2018 10:59:20 +0200 Message-Id: <20180927085921.24627-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180927085921.24627-1-martin.blumenstingl@googlemail.com> References: <20180927085921.24627-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180927_015957_703833_485F07C4 X-CRM114-Status: GOOD ( 21.58 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, Martin Blumenstingl , linux-clk@vger.kernel.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The public S805 datasheet only mentions that HHI_SYS_CPU_CLK_CNTL1[20:29] contains a divider called "cpu_scale_div". Unfortunately it does not mention how to use the register contents. The Amlogic 3.10 GPL kernel sources are using the following code to calculate the CPU clock based on that register (taken from arch/arm/mach-meson8/clock.c in the 3.10 Amlogic kernel, shortened to make it easier to read): N = (aml_read_reg32(P_HHI_SYS_CPU_CLK_CNTL1) >> 20) & 0x3FF; if (sel == 3) /* use cpu_scale_div */ div = 2 * N; else div = ... /* not relevant for this example */ cpu_clk = parent_clk / div; This suggests that the formula is: parent_rate / 2 * register_value However, running perf (which can measure the CPU clock rate thanks to the ARM PMU) shows that this formula is not correct. This can be reproduced with the following steps: 1. boot into u-boot 2. let the CPU clock run off the XTAL clock: mw.l 0xC110419C 0x30 1 3. set the cpu_scale_div register: to value 0x1: mw.l 0xC110415C 0x801016A2 1 to value 0x2: mw.l 0xC110415C 0x802016A2 1 to value 0x5: mw.l 0xC110415C 0x805016A2 1 4. let the CPU clock run off cpu_scale_div: mw.l 0xC110419C 0xbd 1 5. boot Linux 6. run: perf stat -aB stress --cpu 4 --timeout 10 7. check the "cycles" value I get the following results depending on the cpu_scale_div value: - (cpu_in_sel - this is the input clock for cpu_scale_div - runs at 1.2GHz) - 0x1 = 300MHz - 0x2 = 200MHz - 0x5 = 100MHz This means that the actual formula to calculate the output of the cpu_scale_div clock is: parent_rate / 2 * (register value + 1). The register value 0x0 is reserved. When letting the CPU clock run off the cpu_scale_div while the value is 0x0 the whole board hangs (even in u-boot). I also verified this with the TWD timer: when adding this to the .dts without specifying it's clock it will auto-detect the PERIPH (which is the input clock of the TWD) clock rate (and the result is shown in the kernel log). On Meson8, Meson8b and Meson8m2 the PERIPH clock is CPUCLK divided by 4. This also matched for all three test-cases from above (in all cases the TWD timer clock rate was approx. one fourth of the CPU clock rate). A small note regarding the "fixes" tag: the original issue seems to exist virtually since forever. Even commit 28b9fcd016126e ("clk: meson8b: Add support for Meson8b clocks") seems to handle this wrong. I still decided to use commit 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock") because this is the first commit which gets the CPU hiearchy correct and thus it's the first commit where the cpu_scale_div register is used correctly (apart from the bug in the cpu_scale_table). Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock") Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index e7fe66f61d7b..d3f4e11d106d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -579,13 +579,14 @@ static struct clk_fixed_factor meson8b_cpu_div3 = { }; static const struct clk_div_table cpu_scale_table[] = { - { .val = 2, .div = 4 }, - { .val = 3, .div = 6 }, - { .val = 4, .div = 8 }, - { .val = 5, .div = 10 }, - { .val = 6, .div = 12 }, - { .val = 7, .div = 14 }, - { .val = 8, .div = 16 }, + { .val = 1, .div = 4 }, + { .val = 2, .div = 6 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 10 }, + { .val = 5, .div = 12 }, + { .val = 6, .div = 14 }, + { .val = 7, .div = 16 }, + { .val = 8, .div = 18 }, { /* sentinel */ }, }; From patchwork Thu Sep 27 08:59:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10617669 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 780A7913 for ; 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[2003:dc:d716:e000:f8f1:a759:b0fa:a67f]) by smtp.googlemail.com with ESMTPSA id p64-v6sm1776483wrc.97.2018.09.27.01.59.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Sep 2018 01:59:33 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com Subject: [PATCH 2/2] clk: meson: meson8b: fix the width of the cpu_scale_div clock Date: Thu, 27 Sep 2018 10:59:21 +0200 Message-Id: <20180927085921.24627-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180927085921.24627-1-martin.blumenstingl@googlemail.com> References: <20180927085921.24627-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180927_015956_658833_1F07C10D X-CRM114-Status: GOOD ( 16.01 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, Martin Blumenstingl , linux-clk@vger.kernel.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP According to the public S805 datasheet HHI_SYS_CPU_CLK_CNTL1[29:20] is the register for the CPU scale_div clock. This matches the code in Amlogic's 3.10 GPL kernel sources: N = (aml_read_reg32(P_HHI_SYS_CPU_CLK_CNTL1) >> 20) & 0x3FF; This means that the divider register is 10 bit wide instead of 9 bits. So far this is not a problem since all u-boot versions I have seen are not using the cpu_scale_div clock at all (instead they are configuring the CPU clock to run off cpu_in_sel directly). The fixes tag points to the latest rework of the CPU clocks. However, even before the rework it was wrong. Commit 7a29a869434e8b ("clk: meson: Add support for Meson clock controller") defines MESON_N_WIDTH as 9 (in drivers/clk/meson/clk-cpu.c). But since the old clk-cpu implementation this only carries the fixes tag for the CPU clock rewordk. Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock") Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index d3f4e11d106d..8658a662b10e 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -594,7 +594,7 @@ static struct clk_regmap meson8b_cpu_scale_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .shift = 20, - .width = 9, + .width = 10, .table = cpu_scale_table, .flags = CLK_DIVIDER_ALLOW_ZERO, },