From patchwork Fri Feb 7 07:03:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11369847 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0646112B for ; Fri, 7 Feb 2020 07:04:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CF37E22464 for ; Fri, 7 Feb 2020 07:04:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="X6N5ujWE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726860AbgBGHEG (ORCPT ); Fri, 7 Feb 2020 02:04:06 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:52391 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726451AbgBGHEG (ORCPT ); Fri, 7 Feb 2020 02:04:06 -0500 X-UUID: de04c1f7046b4281ab8515025981eabc-20200207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5HvzdlfZTx72XjylW/wDM1/cgbzDal8HbcC73gtLS5I=; b=X6N5ujWEQJWf8eWPMF//rRdl4bdWz1lRYuIW3PjErtA21bDWt0ztIzIj7Wmq1tWClRmEjyQxn+1agU8mQuAHPF5+yxYc05/D/8QuCz8cfxsMp1TobP+laKszf+aNdygbBUUlAmYWK5MersZ+7ALuQYLKtrAEREA5Cz5caTZ4JP4=; X-UUID: de04c1f7046b4281ab8515025981eabc-20200207 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 219011743; Fri, 07 Feb 2020 15:04:00 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 7 Feb 2020 15:02:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 7 Feb 2020 15:04:28 +0800 From: Stanley Chu To: , , , , , CC: , , , , , , , , , , , Stanley Chu Subject: [PATCH v1 1/2] scsi: ufs: ufs-mediatek: fix TX LCC disabling timing Date: Fri, 7 Feb 2020 15:03:56 +0800 Message-ID: <20200207070357.17169-2-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200207070357.17169-1-stanley.chu@mediatek.com> References: <20200207070357.17169-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: CCF22BD2D5023F448DCF45E9C134A9B5F693F4DF05BCEC3FF893F596DE7ED9352000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org MediaTek UFS host requires TX LCC to be disabled in both host and device sides. This can be done by disabling host's local TX LCC before link startup. Correct TX LCC disabling timing in MediaTek UFS driver. Signed-off-by: Stanley Chu Reviewed-by: Avri Altman --- drivers/scsi/ufs/ufs-mediatek.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 0ce08872d671..8f73c860f423 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -313,6 +313,15 @@ static int ufs_mtk_pre_link(struct ufs_hba *hba) ufs_mtk_unipro_powerdown(hba, 0); + /* + * Setting PA_Local_TX_LCC_Enable to 0 before link startup + * to make sure that both host and device TX LCC are disabled + * once link startup is completed. + */ + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); + if (ret) + return ret; + /* disable deep stall */ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp); if (ret) @@ -344,9 +353,6 @@ static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) static int ufs_mtk_post_link(struct ufs_hba *hba) { - /* disable device LCC */ - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); - /* enable unipro clock gating feature */ ufs_mtk_cfg_unipro_cg(hba, true); From patchwork Fri Feb 7 07:03:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11369845 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AA3E5112B for ; Fri, 7 Feb 2020 07:04:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 737FA222C2 for ; Fri, 7 Feb 2020 07:04:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IDDf/v7q" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726935AbgBGHEH (ORCPT ); Fri, 7 Feb 2020 02:04:07 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:56362 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726573AbgBGHEG (ORCPT ); Fri, 7 Feb 2020 02:04:06 -0500 X-UUID: 68390ea84fc14b07aa96cce384b45442-20200207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6jM/oR06razYnFBu9+gewGY3eZHYhaG1HA0jqsKM5V0=; b=IDDf/v7qRZ49wRCyJyBLD3I7xIp+7uXiIecE3zVt8vnkCZwYZILvjE8S/1gqiUr1V3kKHCpfNTDY4+wbwY2PvtiCEi5xcs0uENPZRlOm6rl2PVW3IL5aYR8Wn4FLNjr7aOy0hIeCE4tDrzMMHu97XEU9uJrZ36aUBRZqmv1HNfc=; X-UUID: 68390ea84fc14b07aa96cce384b45442-20200207 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1088173936; Fri, 07 Feb 2020 15:03:59 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 7 Feb 2020 15:02:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 7 Feb 2020 15:04:28 +0800 From: Stanley Chu To: , , , , , CC: , , , , , , , , , , , Stanley Chu Subject: [PATCH v1 2/2] scsi: ufs: introduce common function to disable host TX LCC Date: Fri, 7 Feb 2020 15:03:57 +0800 Message-ID: <20200207070357.17169-3-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200207070357.17169-1-stanley.chu@mediatek.com> References: <20200207070357.17169-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Many vendors would like to disable host TX LCC during initialization flow. Introduce a common function for all users to make drivers easier to read and maintained. This patch does not change any functionality. Signed-off-by: Stanley Chu Reviewed-by: Can Guo Reviewed-by: Avri Altman Reviewed-by: Asutosh Das Reviewed-by: Avri Altman --- drivers/scsi/ufs/cdns-pltfrm.c | 2 +- drivers/scsi/ufs/ufs-hisi.c | 2 +- drivers/scsi/ufs/ufs-mediatek.c | 2 +- drivers/scsi/ufs/ufs-qcom.c | 4 +--- drivers/scsi/ufs/ufshcd-pci.c | 2 +- drivers/scsi/ufs/ufshcd.h | 5 +++++ 6 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/scsi/ufs/cdns-pltfrm.c b/drivers/scsi/ufs/cdns-pltfrm.c index 56a6a1ed5ec2..da065a259f6e 100644 --- a/drivers/scsi/ufs/cdns-pltfrm.c +++ b/drivers/scsi/ufs/cdns-pltfrm.c @@ -192,7 +192,7 @@ static int cdns_ufs_link_startup_notify(struct ufs_hba *hba, * and device TX LCC are disabled once link startup is * completed. */ - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); + ufshcd_disable_host_tx_lcc(hba); /* * Disabling Autohibern8 feature in cadence UFS diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c index 5d6487350a6c..074a6a055a4c 100644 --- a/drivers/scsi/ufs/ufs-hisi.c +++ b/drivers/scsi/ufs/ufs-hisi.c @@ -235,7 +235,7 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba) ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); /* Unipro PA_Local_TX_LCC_Enable */ - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x155E, 0x0), 0x0); + ufshcd_disable_host_tx_lcc(hba); /* close Unipro VS_Mk2ExtnSupport */ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0); ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value); diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 8f73c860f423..9d05962feb15 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -318,7 +318,7 @@ static int ufs_mtk_pre_link(struct ufs_hba *hba) * to make sure that both host and device TX LCC are disabled * once link startup is completed. */ - ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); + ret = ufshcd_disable_host_tx_lcc(hba); if (ret) return ret; diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index c69c29a1ceb9..c2e703d58f63 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -554,9 +554,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, * completed. */ if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) - err = ufshcd_dme_set(hba, - UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), - 0); + err = ufshcd_disable_host_tx_lcc(hba); break; case POST_CHANGE: diff --git a/drivers/scsi/ufs/ufshcd-pci.c b/drivers/scsi/ufs/ufshcd-pci.c index 3b19de3ae9a3..8f78a8151499 100644 --- a/drivers/scsi/ufs/ufshcd-pci.c +++ b/drivers/scsi/ufs/ufshcd-pci.c @@ -44,7 +44,7 @@ static int ufs_intel_disable_lcc(struct ufs_hba *hba) ufshcd_dme_get(hba, attr, &lcc_enable); if (lcc_enable) - ufshcd_dme_set(hba, attr, 0); + ufshcd_disable_host_tx_lcc(hba); return 0; } diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index 81c71a3e3474..8f516b205c32 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -914,6 +914,11 @@ static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) pwr_info->pwr_tx == FASTAUTO_MODE); } +static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) +{ + return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); +} + /* Expose Query-Request API */ int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,