From patchwork Wed Feb 12 23:45:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379421 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 89EF11395 for ; Wed, 12 Feb 2020 23:47:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 56167206DB for ; Wed, 12 Feb 2020 23:47:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nNu3rbbz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729302AbgBLXqe (ORCPT ); Wed, 12 Feb 2020 18:46:34 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:40430 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729132AbgBLXqd (ORCPT ); Wed, 12 Feb 2020 18:46:33 -0500 Received: by mail-lj1-f194.google.com with SMTP id n18so4416092ljo.7; Wed, 12 Feb 2020 15:46:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=asV4gL+YsfNPLapkas09h6qgYAxvmOzGpvVowKzGjNI=; b=nNu3rbbzn0gb1FUgJUvYHi3ItgCG3HkiepSBJTDSuAm3pR5b+xSfKnKOWiMqu343wk +PNtCNQB8y9n/jZMNg142IQXWPFo0jhSG7gEri0Ense4bgvM5HtlrEfVwJdZk/KrnbGn wSvk4GNzrw+o6hIJUM46N3PeFJc4wbxjqye5vNmPpYo8zrddidoT2nN3lLimWSWuaDgw n7DiMXEgxRrYLOAk3jK56L7yEXfeP3sGMKG9ASaPGL4nK78SbR/f2eLlAR2eyxqPcYuI Qt4b50cP33dQvedMEwQ+yCYO8rXbiFqppkPRAkWcwhHBQR/2Jl3efNrClLDGwK3Ousbp RPLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=asV4gL+YsfNPLapkas09h6qgYAxvmOzGpvVowKzGjNI=; b=V2O1OQupOWMWe0uEVWK7Al0vMJPqVhMRh1fO5eO8fKdnmxITjjYia2tfJvu9UfaGow HAhZTWyCpOyBA1vJMYWXEESA+c4oZK9IM2so8gONyoVOL9H2wnlN1zbpQeS+V4YhYEVc koidFzZwlB6E8ePHdKSMZMIqHlsxSatj4/Dok5nShM0o/R17MZYt1pRDiwGazFgVqFVz 4YehEB5JiroXgMs66Lnt1il1aJMHMR/9hs2BLlrHxnF3Pe3OKRLZ8w/PjMlrixiZ8l8v b+j855n0x14tQEnKw9AZrUpHqohp/YsKLUkoBTik3k2+8jfYICtUWf6jqEmYyVVds05E wxPQ== X-Gm-Message-State: APjAAAV9/Y2trNtmkAF3mFowDqqOAHEhEIqRyxYuS094iubZdfUDpNpa dnP8CutZtxtdZyklBsx7dOQ= X-Google-Smtp-Source: APXvYqxobdw2OZAtVWnOPi/VrXCgsk1Fb4iKfiQnDWWZpg8tiHi3WR8kmv1V4jPgsZIGLabWCzzx2Q== X-Received: by 2002:a05:651c:d4:: with SMTP id 20mr8974374ljr.269.1581551190349; Wed, 12 Feb 2020 15:46:30 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:29 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 01/12] clk: tegra: Add custom CCLK implementation Date: Thu, 13 Feb 2020 02:45:56 +0300 Message-Id: <20200212234607.11521-2-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK. This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver. Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-tegra-super-cclk.c | 178 +++++++++++++++++++++++ drivers/clk/tegra/clk.h | 11 +- 3 files changed, 188 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index df966ca06788..f04b490f5416 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -14,6 +14,7 @@ obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o obj-y += clk-tegra-pmc.o obj-y += clk-tegra-fixed.o +obj-y += clk-tegra-super-cclk.o obj-y += clk-tegra-super-gen4.o obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c new file mode 100644 index 000000000000..7bcb9e8d0860 --- /dev/null +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on clk-super.c + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Based on older tegra20-cpufreq driver by Colin Cross + * Copyright (C) 2010 Google, Inc. + * + * Author: Dmitry Osipenko + * Copyright (C) 2019 GRATE-DRIVER project + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define PLLP_INDEX 4 +#define PLLX_INDEX 8 + +#define SUPER_CDIV_ENB BIT(31) + +static u8 cclk_super_get_parent(struct clk_hw *hw) +{ + return tegra_clk_super_ops.get_parent(hw); +} + +static int cclk_super_set_parent(struct clk_hw *hw, u8 index) +{ + return tegra_clk_super_ops.set_parent(hw, index); +} + +static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); +} + +static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + if (cclk_super_get_parent(hw) == PLLX_INDEX) + return parent_rate; + + return tegra_clk_super_ops.recalc_rate(hw, parent_rate); +} + +static int cclk_super_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *pllp_hw = clk_hw_get_parent_by_index(hw, PLLP_INDEX); + struct clk_hw *pllx_hw = clk_hw_get_parent_by_index(hw, PLLX_INDEX); + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + unsigned long pllp_rate; + long rate = req->rate; + + if (WARN_ON_ONCE(!pllp_hw || !pllx_hw)) + return -EINVAL; + + /* + * Switch parent to PLLP for all CCLK rates that are suitable for PLLP. + * PLLX will be disabled in this case, saving some power. + */ + pllp_rate = clk_hw_get_rate(pllp_hw); + + if (rate <= pllp_rate) { + if (super->flags & TEGRA20_SUPER_CLK) + rate = pllp_rate; + else + rate = tegra_clk_super_ops.round_rate(hw, rate, + &pllp_rate); + + req->best_parent_rate = pllp_rate; + req->best_parent_hw = pllp_hw; + req->rate = rate; + } else { + rate = clk_hw_round_rate(pllx_hw, rate); + req->best_parent_rate = rate; + req->best_parent_hw = pllx_hw; + req->rate = rate; + } + + if (WARN_ON_ONCE(rate <= 0)) + return -EINVAL; + + return 0; +} + +static const struct clk_ops tegra_cclk_super_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .set_rate = cclk_super_set_rate, + .recalc_rate = cclk_super_recalc_rate, + .determine_rate = cclk_super_determine_rate, +}; + +static const struct clk_ops tegra_cclk_super_mux_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .determine_rate = cclk_super_determine_rate, +}; + +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock) +{ + struct tegra_clk_super_mux *super; + struct clk *clk; + struct clk_init_data init; + u32 val; + + super = kzalloc(sizeof(*super), GFP_KERNEL); + if (!super) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.parent_names = parent_names; + init.num_parents = num_parents; + + super->reg = reg; + super->lock = lock; + super->width = 4; + super->flags = clk_super_flags; + super->hw.init = &init; + + if (super->flags & TEGRA20_SUPER_CLK) { + init.ops = &tegra_cclk_super_mux_ops; + } else { + init.ops = &tegra_cclk_super_ops; + + super->frac_div.reg = reg + 4; + super->frac_div.shift = 16; + super->frac_div.width = 8; + super->frac_div.frac_width = 1; + super->frac_div.lock = lock; + super->div_ops = &tegra_clk_frac_div_ops; + } + + /* + * Tegra30+ has the following CPUG clock topology: + * + * +---+ +-------+ +-+ +-+ +-+ + * PLLP+->+ +->+DIVIDER+->+0| +-------->+0| ------------->+0| + * | | +-------+ | | | +---+ | | | | | + * PLLC+->+MUX| | +->+ | S | | +->+ | +->+CPU + * ... | | | | | | K | | | | +-------+ | | + * PLLX+->+-->+------------>+1| +->+ I +->+1| +->+ DIV2 +->+1| + * +---+ +++ | P | +++ |SKIPPER| +++ + * ^ | P | ^ +-------+ ^ + * | | E | | | + * PLLX_SEL+--+ | R | | OVERHEAT+--+ + * +---+ | + * | + * SUPER_CDIV_ENB+--+ + * + * Tegra20 is similar, but simpler. It doesn't have the divider and + * thermal DIV2 skipper. + * + * At least for now we're not going to use clock-skipper, hence let's + * ensure that it is disabled. + */ + val = readl_relaxed(reg + 4); + val &= ~SUPER_CDIV_ENB; + writel_relaxed(val, reg + 4); + + clk = clk_register(NULL, &super->hw); + if (IS_ERR(clk)) + kfree(super); + + return clk; +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 416a6b09f6a3..ee35a847df08 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -729,8 +729,10 @@ struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates * that this is LP cluster clock. * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5 - * super mux parent using PLLP branches. To use PLLP branches to CPU, need - * to configure additional bit PLLP_OUT_CPU in the clock registers. + * super mux parent using PLLP branches. To use PLLP branches to CPU, need + * to configure additional bit PLLP_OUT_CPU in the clock registers. + * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super + * clocks, it only has a clock-skipper. */ struct tegra_clk_super_mux { struct clk_hw hw; @@ -748,6 +750,7 @@ struct tegra_clk_super_mux { #define TEGRA_DIVIDER_2 BIT(0) #define TEGRA210_CPU_CLK BIT(1) +#define TEGRA20_SUPER_CLK BIT(2) extern const struct clk_ops tegra_clk_super_ops; struct clk *tegra_clk_register_super_mux(const char *name, @@ -758,6 +761,10 @@ struct clk *tegra_clk_register_super_clk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Wed Feb 12 23:45:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B1AA4109A for ; Wed, 12 Feb 2020 23:47:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9131E21734 for ; Wed, 12 Feb 2020 23:47:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gdgui55y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729331AbgBLXqf (ORCPT ); Wed, 12 Feb 2020 18:46:35 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:43400 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727117AbgBLXqe (ORCPT ); Wed, 12 Feb 2020 18:46:34 -0500 Received: by mail-lj1-f194.google.com with SMTP id a13so4415647ljm.10; Wed, 12 Feb 2020 15:46:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N3LGfCdeQzU8y6RcjHLOzc6mRQN8kt3++oI0IAl5DEA=; b=gdgui55y/mzCpuABmTSECaxVGZCS/Ry59fPpo5gc3iXc4MItPuzmJ6e7l3PSS0zN63 Rv70sxOVUVbFtNPi+yO/jhOXZ3TGDIUqvgKt9KUKDguujDXPycvNpT/XTvxOiZjaP2y5 J3AqDPyu6r3LJjT409xgK/B/Ffl197IFUUjeMxod1sgi2O+qv/xCwycHFs9+dUi1YGmb lyGvk2iACbJQULwqNqaGbo3eNAXlAgRIJwaH4SEHDZgYrw2Pryx3nLv7zN+xwxYGQy93 xoksDbGsZSW3oVlHqU8pm+nrrtIviYnAhpAg2k0/2kV4wSgnQiw9nhEgfiBNS+PPBImV K+6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N3LGfCdeQzU8y6RcjHLOzc6mRQN8kt3++oI0IAl5DEA=; b=itGQvqqYlwyPNWSIyEoHV3CMDMWcszqufvgUdR9Zz6p9oWlrMupHyThEIZBthMxZz6 0Bbs5WMZsUPxmlNjajVIxUGr7CxnJE825ipFGeIh6rrnpY5QCICqxu9Vz6aHj88sWtOi T4dKYehNo8AwyMWIe5Psn2TrhqFhF3+w+YFFaf76k+LbITR7QJsvJ0uTQFRm5ksPnDTP XfQbgrDwIvdzGNo244zXmJdj3e40LyLwSN940WH01z1w2VS3BTJEpw4hVaBR8F9+4MA9 +aXp4tfNv+WwgRLTRVbHg/dltPs/i6GHnw577tad/zRJNPc9z4GjtGz39H8DglGjFrXs +ymg== X-Gm-Message-State: APjAAAV52J3Kyv1idpZaDVARRWvr9G4D7pH5zrcESj7BeYnBUbml6yuO pLY6t+NCXCWQS8hMfGup3SM= X-Google-Smtp-Source: APXvYqymM4rtJj9oCW+XjmAVdHkZXe/KOV/sVe3NJqg6FidgyPAaJW3+93NUUdVz5Z3+gSl0xN+fxw== X-Received: by 2002:a2e:6f19:: with SMTP id k25mr9272533ljc.84.1581551191583; Wed, 12 Feb 2020 15:46:31 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:31 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 02/12] clk: tegra: pll: Add pre/post rate-change hooks Date: Thu, 13 Feb 2020 02:45:57 +0300 Message-Id: <20200212234607.11521-3-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org There is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-pll.c | 12 +++++++++++- drivers/clk/tegra/clk.h | 6 ++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 531c2b3d814e..0b212cf2e794 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -744,13 +744,19 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, state = clk_pll_is_enabled(hw); + if (state && pll->params->pre_rate_change) { + ret = pll->params->pre_rate_change(); + if (WARN_ON(ret)) + return ret; + } + _get_pll_mnp(pll, &old_cfg); if (state && pll->params->defaults_set && pll->params->dyn_ramp && (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { ret = pll->params->dyn_ramp(pll, cfg); if (!ret) - return 0; + goto done; } if (state) { @@ -772,6 +778,10 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, pll_clk_start_ss(pll); } +done: + if (state && pll->params->post_rate_change) + pll->params->post_rate_change(); + return ret; } diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index ee35a847df08..fa18bef914af 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -266,6 +266,10 @@ struct tegra_clk_pll; * disabled. * @dyn_ramp: Callback which can be used to define a custom * dynamic ramp function for a given PLL. + * @pre_rate_change: Callback which is invoked just before changing + * PLL's rate. + * @post_rate_change: Callback which is invoked right after changing + * PLL's rate. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -342,6 +346,8 @@ struct tegra_clk_pll_params { void (*set_defaults)(struct tegra_clk_pll *pll); int (*dyn_ramp)(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg); + int (*pre_rate_change)(void); + void (*post_rate_change)(void); }; #define TEGRA_PLL_USE_LOCK BIT(0) From patchwork Wed Feb 12 23:45:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379415 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F29EC109A for ; Wed, 12 Feb 2020 23:47:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C9813217F4 for ; Wed, 12 Feb 2020 23:47:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eTkALLQ3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729360AbgBLXrN (ORCPT ); Wed, 12 Feb 2020 18:47:13 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:36295 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729287AbgBLXqf (ORCPT ); Wed, 12 Feb 2020 18:46:35 -0500 Received: by mail-lj1-f195.google.com with SMTP id r19so4436205ljg.3; Wed, 12 Feb 2020 15:46:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jy56CF/Sf3+uwtcC22JB0l4dVspO7RMlTf9CHzOik90=; b=eTkALLQ3hUb7OazlEVmx7iXWbaEUtHgwSE9rOlYHjXOsItzOn+EdnYGCU0YpALRZ/8 407RdA32aWzUcSjqIBiTLj4LuaP2/jNXpZNcLnKgp1yQcAs6djW0b/9wkJNoRT/89QhG CzfOOPOY8ApGDh3y8dkuAyApvNuL8eay5B3CsayjjkP0F2dsgY5c31pRFwompKpnlUPp 2Qy5GVmgL/Gm7/NdASyDWeQXKWUk11EvmwRVWPkMKBrZyqIP1pQGhEoadDvZmlHXbPyd 05gA44dS95/2ux0Xpitso5DvpoEOFDVhkxfWSmnnM58SaFHKHPTJVSfyOQ5WW64Ci2R8 eqoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jy56CF/Sf3+uwtcC22JB0l4dVspO7RMlTf9CHzOik90=; b=BseYG39QoQSN2lsMEKyjv0amZkHZn2JJGUktSINMSICes65RdS7QPSWMTGNk87A2jb KujZK20x9kNcXik+/QDI9iR7Ujh5NbOKBb0TPWLBbZ0smpwcCngdYluudxCYFgwxGqgW t3tLfsX1EBtucfwGF40UyPifIKI8N7E+/+K1SIjfBZISUigdUIGdPqirNt5OIAy5KUuV kkSkx6PpwjoUMK8VvZM6LXkt1p3PKLibRjuWi+5Zdu2V+auMq7iS2+uK/ArK8QOHWAn8 Igz19w5uyg7kx5Z5GvBsmNmOSmaoXKcwr5bQ1sMy8TnKij6kKHLIRALswmPAaR1gPN3K Ns2w== X-Gm-Message-State: APjAAAWatgAry6WTchtSOpoIZeaMWFX8aPN7BTXIHq7SEAAOfndUwQAq b3TGxz+XlX1JyXiYKbXU4Vw= X-Google-Smtp-Source: APXvYqz4JyU+3wNqJIDiJjOpdF5KcYIIaNgf8sK9D5jbCPw0IUrx7/8sJGeO8DR6YJsMfBDPOAWRGw== X-Received: by 2002:a2e:3e13:: with SMTP id l19mr9013337lja.11.1581551192796; Wed, 12 Feb 2020 15:46:32 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:32 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 03/12] clk: tegra: cclk: Add helpers for handling PLLX rate changes Date: Thu, 13 Feb 2020 02:45:58 +0300 Message-Id: <20200212234607.11521-4-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index 7bcb9e8d0860..a03119c30456 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -25,6 +25,9 @@ #define SUPER_CDIV_ENB BIT(31) +static struct tegra_clk_super_mux *cclk_super; +static bool cclk_on_pllx; + static u8 cclk_super_get_parent(struct clk_hw *hw) { return tegra_clk_super_ops.get_parent(hw); @@ -115,6 +118,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name, struct clk_init_data init; u32 val; + if (WARN_ON(cclk_super)) + return ERR_PTR(-EBUSY); + super = kzalloc(sizeof(*super), GFP_KERNEL); if (!super) return ERR_PTR(-ENOMEM); @@ -173,6 +179,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name, clk = clk_register(NULL, &super->hw); if (IS_ERR(clk)) kfree(super); + else + cclk_super = super; return clk; } + +int tegra_cclk_pre_pllx_rate_change(void) +{ + if (IS_ERR_OR_NULL(cclk_super)) + return -EINVAL; + + if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX) + cclk_on_pllx = true; + else + cclk_on_pllx = false; + + /* + * CPU needs to be temporarily re-parented away from PLLX if PLLX + * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs. + */ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX); + + return 0; +} + +void tegra_cclk_post_pllx_rate_change(void) +{ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX); +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index fa18bef914af..0afe28f4372b 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -771,6 +771,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +int tegra_cclk_pre_pllx_rate_change(void); +void tegra_cclk_post_pllx_rate_change(void); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Wed Feb 12 23:45:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379409 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7199C1395 for ; Wed, 12 Feb 2020 23:47:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5180224680 for ; Wed, 12 Feb 2020 23:47:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SlyAu0hY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729376AbgBLXqi (ORCPT ); Wed, 12 Feb 2020 18:46:38 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:40437 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727117AbgBLXqh (ORCPT ); Wed, 12 Feb 2020 18:46:37 -0500 Received: by mail-lj1-f193.google.com with SMTP id n18so4416279ljo.7; Wed, 12 Feb 2020 15:46:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1vsbqTcsPyW7zXr+f9YIopAxvpsx05GcKaLZaiIxhNY=; b=SlyAu0hYm0T01pumhDVu9+DQtPnOXBztlyGQqZCqi7EDWDKpJf3iUBK0TOgpebMWrc euQsx6gyLszzo/AlujdMxysnEkOoB7+TVtLzhmkSfQlB1UBZ9+3YUz0uQOzW/ESWk5J6 T7FP5jwwokxPxVsjui+cpmH1YB8dVq5wB17jnOQdi2i3pIwo+twX6lVaDSx2xSHGCoC4 FW7srSfDvCCWbYdg8yRY/q/r8GUPay9iaYrE0s4Yn5ZCWkmrRLKQ94VsIukewKbTUj3w lZ2mZ9c4Uv/O4Jl9PXmsfSJdpS7+6huysl5rQdOUtnY9iLJ3jADFMwigWERYChYtLe2C a44A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1vsbqTcsPyW7zXr+f9YIopAxvpsx05GcKaLZaiIxhNY=; b=YwjpDQ03amxW4oK4P6zLHKLbW8F1C+tADANjnCZav3Ra0NcCrvr2l2cLV13ttFhBqv ERGJEBSjKHEMZG4Ghdl4WVhqc5fAlElLb1RpbYkR54qPFe4piSQpdBczD1+6AlNr8gej kR+IBPcFMPedo67TjJIMHjTkqUwHtYkrzUBncoTj14hDihHWvq3KeKSPMsmAWp2a8yTs 0yrWkf5jCdTtp3CdxIPGEozhxcJS8lFkTxs90GmbP0BIoVMWir15GQyvAih7JLU+hIZN SbEpxlrtoq3UqDptgWLdbv9uqRB/Ybk9yqRT06e8p8dBRJUP3I6WT+R9n0cBfzppt5p4 7tSg== X-Gm-Message-State: APjAAAWyMUeFN7oHA8ZW/GiPZ6vxYoc+H7Z6mRkzZvrpJiR0Y3L5XpCm V4bjXWQvhh0pdNQQT3zo3+M= X-Google-Smtp-Source: APXvYqxeHGA6dJTm+f2ddhlIBD4sce3z/PMqWS0gUaJFELwLmQu3UUdPHbhphRVko1TJpRmjwc7rDQ== X-Received: by 2002:a2e:2e11:: with SMTP id u17mr8992845lju.117.1581551194026; Wed, 12 Feb 2020 15:46:34 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:33 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 04/12] clk: tegra20: Use custom CCLK implementation Date: Thu, 13 Feb 2020 02:45:59 +0300 Message-Id: <20200212234607.11521-5-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index fff5cba87637..abc6a2bc828a 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -391,6 +391,8 @@ static struct tegra_clk_pll_params pll_x_params = { .lock_delay = 300, .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params = { @@ -704,9 +706,10 @@ static void tegra20_super_clk_init(void) struct clk *clk; /* CCLK */ - clk = tegra_clk_register_super_mux("cclk", cclk_parents, + clk = tegra_clk_register_super_cclk("cclk", cclk_parents, ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, - clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); + clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK, + NULL); clks[TEGRA20_CLK_CCLK] = clk; /* SCLK */ From patchwork Wed Feb 12 23:46:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7BA401395 for ; Wed, 12 Feb 2020 23:47:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5AD002173E for ; Wed, 12 Feb 2020 23:47:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jawM+Rmo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729362AbgBLXqi (ORCPT ); Wed, 12 Feb 2020 18:46:38 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:46003 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729359AbgBLXqi (ORCPT ); Wed, 12 Feb 2020 18:46:38 -0500 Received: by mail-lf1-f65.google.com with SMTP id 203so2841806lfa.12; Wed, 12 Feb 2020 15:46:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+/51PDCaWOltwmr5vyW/UVNRobdC9/cI7Y/jAoA9zHs=; b=jawM+Rmo3xtHsycsN0jG9t83LBJfVgXgey4lQsjVqGr5aBUVFzj5PJy/Hy6H245LN4 6X+OP9IjVTiiyPudTWWCy/Ls28zfDv3Li6f7QVj7Hh6ltA9YwdPAWZ+K+plv7gYq3uso mfVKe1RNQDZFmQxGJCgA473gN+HCu3U0aptuJRKFfQYmmAZluz3TEmcXUIDAMXGlnO9k 79LVreL6PqqRZrGfcTeDcO6O19twlSWSJx2LtCq7+Ue4SsKOVrU+mvCuRxETKbr/qcWB 4FxgBRiXd1i9GvXUIavkHgEy8eJLjLKhvPQR68bkNdgD8NsOoEBKfGUGhYAJlvnzWqTJ MRRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+/51PDCaWOltwmr5vyW/UVNRobdC9/cI7Y/jAoA9zHs=; b=hKCVMl1Ns+wjSudel9+agIn6xUFRDn/LGt+DfT2XwfyXNM0wFcfdtLveGEpwXJrniC Xg3sJTEvf80Jl3dMEdkjGmj8r9hmGYYecYgkCcoUVqLQBRUBWvMW7SgsAg5wB1XYKVzR pGJetyYAkd8kuixZlSn17EawIc8TLNFF1Ka8qobHpNkz//Y/I6a6dLvBt7MWUD7PwtvD OLuGnC/jYEiLN7Lq+FANMdaHn5fBH0UIHMxACempBkKDcKftYNk9tSaXucI//xjPrUcr anUYcbK1AWGqMAKr9qZ8mJVdLABG3m8m+gu1cJRsn1yfXqb8gcMXO3FTyDRvKMqP1vOe JIGw== X-Gm-Message-State: APjAAAXJth+byE+OAjIacVDbOpBhK2S6qfvqaVL0gDH53I34Vl7kYR7f x3GqbDmm+e59In7HbkPTAFQ= X-Google-Smtp-Source: APXvYqznlFtDiSzk3yrjYIYXsjLWL2Qw28OUTHgwSxbKXUIDaPhiSu0z3hTLEUgSrUYP1pCZjKtccw== X-Received: by 2002:a19:5504:: with SMTP id n4mr7347333lfe.25.1581551195198; Wed, 12 Feb 2020 15:46:35 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:34 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 05/12] clk: tegra30: Use custom CCLK implementation Date: Thu, 13 Feb 2020 02:46:00 +0300 Message-Id: <20200212234607.11521-6-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra30 SoCs to use that implementation. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra30.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index b20891489e11..43b94175ff33 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = { .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params __ro_after_init = { @@ -932,11 +934,11 @@ static void __init tegra30_super_clk_init(void) clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); /* CCLKG */ - clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, + clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), CLK_SET_RATE_PARENT, clk_base + CCLKG_BURST_POLICY, - 0, 4, 0, 0, NULL); + 0, NULL); clks[TEGRA30_CLK_CCLK_G] = clk; /* From patchwork Wed Feb 12 23:46:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379405 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E9CA1820 for ; Wed, 12 Feb 2020 23:47:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0CD9824680 for ; Wed, 12 Feb 2020 23:47:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HMEGN5A6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729363AbgBLXrG (ORCPT ); Wed, 12 Feb 2020 18:47:06 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:40442 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729360AbgBLXqj (ORCPT ); Wed, 12 Feb 2020 18:46:39 -0500 Received: by mail-lj1-f196.google.com with SMTP id n18so4416367ljo.7; Wed, 12 Feb 2020 15:46:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yt7iB+8N46yIzqprXkevBuhRmPkO5WOPeg5Oq7Gq+OM=; b=HMEGN5A6ibF/Y9VvdzkVvGQD+ATNO1Lu6sIpUbl2kcoZnNQ1KV45gT8jtLtwkEIUz5 94CiiGM0Wh4bLIU8A0Vho0F/EgrBfP/+rby6+EycMAZqvRjblDIjNIdWI0c7xtZOwzLB 0W5flISWtH5EgrtFXtWYurRKGNtDDW2fgXmYgtUF0g6B2IUO8XWL2GSQ4Jb923YtY8H2 Dpswkvk7+tXUU0tC5+ovgh7TKVuXiYZB/BoiU0q07TCn6hDwPhTS1IaIbYAswH30v3tw +cqpeP540xdTjA/vLeINy8/TxaJko0TrIuPaoAI1J2Y82LLrRrDHqy93r3/4rJ8oxTRE sCkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yt7iB+8N46yIzqprXkevBuhRmPkO5WOPeg5Oq7Gq+OM=; b=JFMb+Te3/TTX0zNuYQBn96rou5iyjgJ90b/oFb9gF0OMFo0Lv1Q1jbd6YjOAY4pYo9 VIyK12VovYzoxSgz3oMJFnB9KK5P9+ueL7wuLTKlMi5eNMBaorOhbmLOj242eveBiDK0 b2CToZGQwo497iYig3/2K5wIfnpnaPT0PjByqNGdDSbMiOj+MBzymYlJVjW730rbql5R XilgUAIzqLQLqqBI+W5PUPuxcMgElz2m4jWF+24NSNSmztd1oq2Ld2XKQQFrx9NovSV4 2PTe7k23uvNsSffQZds0qAQeRk3DaaEbAsRNF+4/4gNgDarnnZITxlRGHBIOExg5qwyQ NCxA== X-Gm-Message-State: APjAAAVcp7jp3wyeXXtjSrojfbNhChwRGpTaBYviNiGzscHKMFGSZ7AH BqrUodhcx7PXd49Qr6rQYxA= X-Google-Smtp-Source: APXvYqwUmr00KiHe7WEgw6vme2JIMo+4Umi9uwQlS1cHQXb9a+2UzVKMYPCdxXb+KiXHxE35+4H5rg== X-Received: by 2002:a2e:814e:: with SMTP id t14mr9246918ljg.149.1581551196359; Wed, 12 Feb 2020 15:46:36 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:35 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 06/12] ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124 Date: Thu, 13 Feb 2020 02:46:01 +0300 Message-Id: <20200212234607.11521-7-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The early-resume code shall not switch CPU to PLLX because PLLX configuration could be unstable or PLLX should be simply disabled if CPU enters into suspend running off some other PLL (the case if CPUFREQ driver is active). The actual burst policy is restored by the clock drivers. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/sleep-tegra30.S | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 02cc6ff96f30..b897d4a433b3 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -398,11 +398,8 @@ _pll_m_c_x_done: ldr r4, [r5, #0x1C] @ restore SCLK_BURST str r4, [r0, #CLK_RESET_SCLK_BURST] - cmp r10, #TEGRA30 - movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX - movteq r4, #:upper16:((1 << 28) | (0x8)) - movwne r4, #:lower16:((1 << 28) | (0xe)) - movtne r4, #:upper16:((1 << 28) | (0xe)) + movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP + movt r4, #:upper16:((1 << 28) | (0x4)) str r4, [r0, #CLK_RESET_CCLK_BURST] /* Restore pad power state to normal */ From patchwork Wed Feb 12 23:46:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379399 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 838CC1395 for ; Wed, 12 Feb 2020 23:47:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 62785206B6 for ; Wed, 12 Feb 2020 23:47:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="conaQ3BW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729400AbgBLXqk (ORCPT ); Wed, 12 Feb 2020 18:46:40 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:35605 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729361AbgBLXqj (ORCPT ); Wed, 12 Feb 2020 18:46:39 -0500 Received: by mail-lj1-f194.google.com with SMTP id q8so4438423ljb.2; Wed, 12 Feb 2020 15:46:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kFoQr2efsDjC1sgE/IqBkGYRFbsY8VGMPosKnRKz7po=; b=conaQ3BWIMB1ZG7AlRiS1MwjCKJcLg9S4sW2ZuB6T1kOcyBMB2333AktT036+IHECS fNipirXJVzaRaHGreYYCzN5v6lYakEnF92nTZGO976MqcXFWAOSr3fb0JT2BC752X+tI Tc2MNec/SKHMWmbQ0g9SrWrwaasEN+k2bgFKsoLtJEVQcDtMAtivnTZfJijyi+NwzHnN xHXDsUpkq9nMI8Hil+kBGMOgv8u4uv8UAaqUA5bGITna2WrOUY3eWDxrPsVPDXjxW1X7 u05qxPDmiGoVqg9/NGZtaXdSNZ8TH7c3OjKyNXhtBMz1DFAzlttZcxg9nn0m5k/1yT1P w+zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kFoQr2efsDjC1sgE/IqBkGYRFbsY8VGMPosKnRKz7po=; b=JHpYsDhZLx61BUxGpCWC3PvUxkYtCTae0cjRAVpkajA35KOjHjs28nwIIApIFnNjpU X33fKWpafOYemr+XFSt0VrMgyEM13OUnaCm2b5SD/pZqiqVSDPGLIJ1HVQm1idkS8s08 2YSNAyFKgywGtrXhV2z6AxP5XN5iBPCssHnaSVmZl5L3pLTHCaZVw0qLnaT+32cqaOiM bhfY55B3WrnyiJTGLvn1h3KB5rGozsYozdukggavLs/n7XHpNQqkoxIuSol+NREdLlSy 01vrJy1mqvxUGDVO/pz1L82zSFCAnX0ybMP9+gZgu/MOEMFz6ChfV5Pc1D/gLYjb5o7L sjNA== X-Gm-Message-State: APjAAAVgYaURLp70N+l71w/nzspJrsBnjxDo6oQIP6RrFy4hLHO8veNj WdqQ10rptnBH+YuXd0xwFUs= X-Google-Smtp-Source: APXvYqwkhcXK2XXZFAxC2fq9VgZuSYsR3hMfRl/0FMfAm26yJD4kGM3Ir5AnFGCVNQM/uiqGQTGs9g== X-Received: by 2002:a2e:b610:: with SMTP id r16mr9598528ljn.33.1581551197531; Wed, 12 Feb 2020 15:46:37 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:37 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 07/12] ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30 Date: Thu, 13 Feb 2020 02:46:02 +0300 Message-Id: <20200212234607.11521-8-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org PLLX may be kept disabled if cpufreq driver selects some other clock for CPU. In that case PLLX will be disabled later in the resume path by the CLK driver, which also can enable PLLX if necessary by itself. Thus there is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do not manage PLLX on resume and thus they are left untouched by this patch. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/sleep-tegra30.S | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index b897d4a433b3..c3946dbd0240 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -361,7 +361,6 @@ _no_pll_iddq_exit: pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC - pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC _pll_m_c_x_done: pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC @@ -371,12 +370,18 @@ _pll_m_c_x_done: pll_locked r1, r0, CLK_RESET_PLLP_BASE pll_locked r1, r0, CLK_RESET_PLLA_BASE pll_locked r1, r0, CLK_RESET_PLLC_BASE - pll_locked r1, r0, CLK_RESET_PLLX_BASE + /* + * CPUFreq driver could select other PLL for CPU. PLLX will be + * enabled by the Tegra30 CLK driver on an as-needed basis, see + * tegra30_cpu_clock_resume(). + */ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 cmp r1, #TEGRA30 beq 1f + pll_locked r1, r0, CLK_RESET_PLLX_BASE + ldr r1, [r0, #CLK_RESET_PLLP_BASE] bic r1, r1, #(1<<31) @ disable PllP bypass str r1, [r0, #CLK_RESET_PLLP_BASE] From patchwork Wed Feb 12 23:46:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379397 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11BB4109A for ; Wed, 12 Feb 2020 23:47:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E45FA206B6 for ; Wed, 12 Feb 2020 23:47:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lrCUuLV+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729421AbgBLXqm (ORCPT ); Wed, 12 Feb 2020 18:46:42 -0500 Received: from mail-lf1-f67.google.com ([209.85.167.67]:39693 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727117AbgBLXql (ORCPT ); Wed, 12 Feb 2020 18:46:41 -0500 Received: by mail-lf1-f67.google.com with SMTP id t23so2865096lfk.6; Wed, 12 Feb 2020 15:46:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Eq2aT2KbyFm5O0Maq2+OCMfbsMjQLSKCyn1ZBpg4cFA=; b=lrCUuLV+5a/t9tyxNLyOQ8tiN18sXz2EqWNiMib4wkF9GFW+IExcU0u3GChLU3lp5t OJ2K+zNUFchLN6xx85oN3/c2rUbWFtW+F3SDnCodkZ70ECYuYD4CruthYFlabE5+mZxE 5sZ3yVwwhZAO0b0YsAxHEJ6HxBypSsNN/J4Oq+I++6vb1siE7Lc+voPYxspwNgd6rH4W ugWoyKpaDtg5A7eMAjzeSTesf+GXhCkIjT86Tpk0VRyOnSQZDJgeuSzdH1NEiK8y9bE/ KKLCjjE9kExnW/RAIevDYDWWx2mqj+9U9dNawcSzbNI3tUwekVWOyrUeqfYTwCK5BM90 ptnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Eq2aT2KbyFm5O0Maq2+OCMfbsMjQLSKCyn1ZBpg4cFA=; b=Iz+28dT995kJS2sP/Yzup2/M3oEDwFtNFSA7wuAfPAPw7iy5Suzfn0IzoYskxb8dg1 2Tsz8PWfSUCw2sXS5GKTnJ/bZtI7HQL8SPbQFqMRvHSJvdG74+L7aMisJnB2IX+zdSg5 nvPkYd3qKw5hykiasD+rRU+yuSAq7lgbdkRXunhj5veyN3vUmVFtK8pGmQS02GHtdfg1 KXBpcYCaY8D1UiKhhxTuQPwoTLWMZYFXyAQCLgQFXON4x9SHRjENJIFfaXtqtPVL+ng7 N7dRrqw2Umh7gH6AJbowzkK8xOeaffTwBV8HsBMlo+JNLO8Xn2qELTDQaH1mU5Nvwbsg 1uQA== X-Gm-Message-State: APjAAAXtaileKsBz7XIxlrMqz+Q3UfnYXuNPrHv6ZTCuS5FNytWbD9qp LBA47K2kg1+Vzu1WwcFlef0c1xk7 X-Google-Smtp-Source: APXvYqxr9CrLjDlEfOSYVeO0n/+bT17NYlRg9gYEeeiKtzWWHfOBHJN0VkvlTQ6oziEol52ljnOMKw== X-Received: by 2002:a19:f811:: with SMTP id a17mr7795071lff.182.1581551198795; Wed, 12 Feb 2020 15:46:38 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:38 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 08/12] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Date: Thu, 13 Feb 2020 02:46:03 +0300 Message-Id: <20200212234607.11521-9-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs. Acked-by: Viresh Kumar Reviewed-by: Rob Herring Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- .../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file mode 100644 index 000000000000..daeca6ae6b76 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt @@ -0,0 +1,56 @@ +Binding for NVIDIA Tegra20 CPUFreq +================================== + +Required properties: +- clocks: Must contain an entry for the CPU clock. + See ../clocks/clock-bindings.txt for details. +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + On Tegra20: + 1. CPU process ID mask + 2. SoC speedo ID mask + + On Tegra30: + 1. CPU process ID mask + 2. CPU speedo ID mask + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +- opp-microvolt: CPU voltage triplet. + +Optional properties: +- cpu-supply: Phandle to the CPU power supply. + +Example: + regulators { + cpu_reg: regulator0 { + regulator-name = "vdd_cpu"; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@456000000 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + ... + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&cpu_reg>; + #cooling-cells = <2>; + }; + }; From patchwork Wed Feb 12 23:46:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379393 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0271D1395 for ; Wed, 12 Feb 2020 23:47:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C29C5206B6 for ; Wed, 12 Feb 2020 23:47:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RaLLdbYw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729428AbgBLXq4 (ORCPT ); Wed, 12 Feb 2020 18:46:56 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:40445 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729413AbgBLXqn (ORCPT ); Wed, 12 Feb 2020 18:46:43 -0500 Received: by mail-lj1-f194.google.com with SMTP id n18so4416477ljo.7; Wed, 12 Feb 2020 15:46:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BSRAsOKuqQhMydbct7QTcwSg8DIaGNSw+gtONS8N1tw=; b=RaLLdbYwzteB50FRysnibMp2y7/ykcvBSJDk4UMxqEE4tGXov9VNeOAnUa6nfcbp2p AF9JAt6OGkpGsU2P699qGBczEIK7mjikuq2iXrqWrVdblGabhWav8qPa8pU+Pc0A3QQm 6bXc4gqUDKVVuQRrF1IIhrZLNdeoLgjKq6/KPh+OmtU03PdAQCPoNvZGpHJgNBHnrNHJ 6hvBoezrp9dPpEKrrFAIgZWecv027zEgqE9t8b5iT08UE7MMfMsBiX7vsS/oZEkuotFH SRBgdxNty4wnBHd4nfmDzcd4MeGJ8j2qoLr4YeS1TTXLdaAnAkT6zs0oA5G8k+vO3nRh VddQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BSRAsOKuqQhMydbct7QTcwSg8DIaGNSw+gtONS8N1tw=; b=CVjLcNLLAxbKK3KR/RL3LEiBD3eJv4cOftzEiEWTruQJrn1lkn82fSGePEAIop9ptU /16G929Em0w9hx6Hi92u/DLjLbcP3IPB2YalxP5ChAsQANtNCw5pdUcodlRGpnZDrUOg IFLLavOkGYcIKofz3Vy+0cG2RchIfUj+JlSbcqltnXZIFDH8uXN0Zhh78WZlbWJ2X1Xl yRBPAVq3VXz1y6lM42jUJ0adGK75TEkUosiiy2qOZjGQti7611Ih57dvQP9+ySxAsk2w wBUa33C1uWf4fqV31qjqHQN3nMBLCqFKKfg4QR1LL6/rbGGqpenkJMKmuBkYK3gQUcMn Ml5Q== X-Gm-Message-State: APjAAAUifDzDauOci0x4nVI76j5LbZTEcP6igHdlE2LVIu2JDpxHe59v gemXXRjF9RfMo/i4IIIbhT/L0UHA X-Google-Smtp-Source: APXvYqw4SLVIFOBOzz5H/Do5ps3G3u/2PhwamwmiWx5g/D2Afv8c6iHxeCfe61Bs/hyV24v/BAfXaw== X-Received: by 2002:a2e:8699:: with SMTP id l25mr8934877lji.137.1581551199967; Wed, 12 Feb 2020 15:46:39 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:39 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 09/12] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Date: Thu, 13 Feb 2020 02:46:04 +0300 Message-Id: <20200212234607.11521-10-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Re-parenting to intermediate clock is supported now by the clock driver and thus there is no need in a customized CPUFreq driver, all that code is common for both Tegra20 and Tegra30. The available CPU freqs are now specified in device-tree in a form of OPPs, all users should update their device-trees. Acked-by: Viresh Kumar Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- drivers/cpufreq/Kconfig.arm | 6 +- drivers/cpufreq/tegra20-cpufreq.c | 217 ++++++++---------------------- 2 files changed, 59 insertions(+), 164 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 3858d86cf409..92a6a5089979 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -295,11 +295,11 @@ config ARM_TANGO_CPUFREQ default y config ARM_TEGRA20_CPUFREQ - tristate "Tegra20 CPUFreq support" - depends on ARCH_TEGRA + tristate "Tegra20/30 CPUFreq support" + depends on ARCH_TEGRA && CPUFREQ_DT default y help - This adds the CPUFreq driver support for Tegra20 SOCs. + This adds the CPUFreq driver support for Tegra20/30 SOCs. config ARM_TEGRA124_CPUFREQ bool "Tegra124 CPUFreq support" diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c index f84ecd22f488..8c893043953e 100644 --- a/drivers/cpufreq/tegra20-cpufreq.c +++ b/drivers/cpufreq/tegra20-cpufreq.c @@ -7,201 +7,96 @@ * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation */ -#include -#include +#include +#include #include #include #include +#include #include +#include #include -static struct cpufreq_frequency_table freq_table[] = { - { .frequency = 216000 }, - { .frequency = 312000 }, - { .frequency = 456000 }, - { .frequency = 608000 }, - { .frequency = 760000 }, - { .frequency = 816000 }, - { .frequency = 912000 }, - { .frequency = 1000000 }, - { .frequency = CPUFREQ_TABLE_END }, -}; - -struct tegra20_cpufreq { - struct device *dev; - struct cpufreq_driver driver; - struct clk *cpu_clk; - struct clk *pll_x_clk; - struct clk *pll_p_clk; - bool pll_x_prepared; -}; +#include +#include -static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy, - unsigned int index) +static bool cpu0_node_has_opp_v2_prop(void) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - - /* - * Don't switch to intermediate freq if: - * - we are already at it, i.e. policy->cur == ifreq - * - index corresponds to ifreq - */ - if (freq_table[index].frequency == ifreq || policy->cur == ifreq) - return 0; - - return ifreq; -} + struct device_node *np = of_cpu_device_node_get(0); + bool ret = false; -static int tegra_target_intermediate(struct cpufreq_policy *policy, - unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - int ret; - - /* - * Take an extra reference to the main pll so it doesn't turn - * off when we move the cpu off of it as enabling it again while we - * switch to it from tegra_target() would take additional time. - * - * When target-freq is equal to intermediate freq we don't need to - * switch to an intermediate freq and so this routine isn't called. - * Also, we wouldn't be using pll_x anymore and must not take extra - * reference to it, as it can be disabled now to save some power. - */ - clk_prepare_enable(cpufreq->pll_x_clk); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - if (ret) - clk_disable_unprepare(cpufreq->pll_x_clk); - else - cpufreq->pll_x_prepared = true; + if (of_get_property(np, "operating-points-v2", NULL)) + ret = true; + of_node_put(np); return ret; } -static int tegra_target(struct cpufreq_policy *policy, unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned long rate = freq_table[index].frequency; - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - int ret; - - /* - * target freq == pll_p, don't need to take extra reference to pll_x_clk - * as it isn't used anymore. - */ - if (rate == ifreq) - return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - - ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000); - /* Restore to earlier frequency on error, i.e. pll_x */ - if (ret) - dev_err(cpufreq->dev, "Failed to change pll_x to %lu\n", rate); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); - /* This shouldn't fail while changing or restoring */ - WARN_ON(ret); - - /* - * Drop count to pll_x clock only if we switched to intermediate freq - * earlier while transitioning to a target frequency. - */ - if (cpufreq->pll_x_prepared) { - clk_disable_unprepare(cpufreq->pll_x_clk); - cpufreq->pll_x_prepared = false; - } - - return ret; -} - -static int tegra_cpu_init(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_prepare_enable(cpufreq->cpu_clk); - - /* FIXME: what's the actual transition time? */ - cpufreq_generic_init(policy, freq_table, 300 * 1000); - policy->clk = cpufreq->cpu_clk; - policy->suspend_freq = freq_table[0].frequency; - return 0; -} - -static int tegra_cpu_exit(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_disable_unprepare(cpufreq->cpu_clk); - return 0; -} - static int tegra20_cpufreq_probe(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq; + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; + struct device *cpu_dev; + u32 versions[2]; int err; - cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL); - if (!cpufreq) - return -ENOMEM; + if (!cpu0_node_has_opp_v2_prop()) { + dev_err(&pdev->dev, "operating points not found\n"); + dev_err(&pdev->dev, "please update your device tree\n"); + return -ENODEV; + } + + if (of_machine_is_compatible("nvidia,tegra20")) { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.soc_speedo_id); + } else { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.cpu_speedo_id); + } + + dev_info(&pdev->dev, "hardware version 0x%x 0x%x\n", + versions[0], versions[1]); - cpufreq->cpu_clk = clk_get_sys(NULL, "cclk"); - if (IS_ERR(cpufreq->cpu_clk)) - return PTR_ERR(cpufreq->cpu_clk); + cpu_dev = get_cpu_device(0); + if (WARN_ON(!cpu_dev)) + return -ENODEV; - cpufreq->pll_x_clk = clk_get_sys(NULL, "pll_x"); - if (IS_ERR(cpufreq->pll_x_clk)) { - err = PTR_ERR(cpufreq->pll_x_clk); - goto put_cpu; + opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2); + err = PTR_ERR_OR_ZERO(opp_table); + if (err) { + dev_err(&pdev->dev, "failed to set supported hw: %d\n", err); + return err; } - cpufreq->pll_p_clk = clk_get_sys(NULL, "pll_p"); - if (IS_ERR(cpufreq->pll_p_clk)) { - err = PTR_ERR(cpufreq->pll_p_clk); - goto put_pll_x; + cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0); + err = PTR_ERR_OR_ZERO(cpufreq_dt); + if (err) { + dev_err(&pdev->dev, + "failed to create cpufreq-dt device: %d\n", err); + goto err_put_supported_hw; } - cpufreq->dev = &pdev->dev; - cpufreq->driver.get = cpufreq_generic_get; - cpufreq->driver.attr = cpufreq_generic_attr; - cpufreq->driver.init = tegra_cpu_init; - cpufreq->driver.exit = tegra_cpu_exit; - cpufreq->driver.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK; - cpufreq->driver.verify = cpufreq_generic_frequency_table_verify; - cpufreq->driver.suspend = cpufreq_generic_suspend; - cpufreq->driver.driver_data = cpufreq; - cpufreq->driver.target_index = tegra_target; - cpufreq->driver.get_intermediate = tegra_get_intermediate; - cpufreq->driver.target_intermediate = tegra_target_intermediate; - snprintf(cpufreq->driver.name, CPUFREQ_NAME_LEN, "tegra"); - - err = cpufreq_register_driver(&cpufreq->driver); - if (err) - goto put_pll_p; - - platform_set_drvdata(pdev, cpufreq); + platform_set_drvdata(pdev, cpufreq_dt); return 0; -put_pll_p: - clk_put(cpufreq->pll_p_clk); -put_pll_x: - clk_put(cpufreq->pll_x_clk); -put_cpu: - clk_put(cpufreq->cpu_clk); +err_put_supported_hw: + dev_pm_opp_put_supported_hw(opp_table); return err; } static int tegra20_cpufreq_remove(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq = platform_get_drvdata(pdev); + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; - cpufreq_unregister_driver(&cpufreq->driver); + cpufreq_dt = platform_get_drvdata(pdev); + platform_device_unregister(cpufreq_dt); - clk_put(cpufreq->pll_p_clk); - clk_put(cpufreq->pll_x_clk); - clk_put(cpufreq->cpu_clk); + opp_table = dev_pm_opp_get_opp_table(get_cpu_device(0)); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_opp_table(opp_table); return 0; } From patchwork Wed Feb 12 23:46:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379385 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4EA301395 for ; Wed, 12 Feb 2020 23:46:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E0C4218AC for ; Wed, 12 Feb 2020 23:46:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BZfNMtHL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727117AbgBLXqo (ORCPT ); Wed, 12 Feb 2020 18:46:44 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:36106 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729361AbgBLXqn (ORCPT ); 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[79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:40 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 10/12] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Date: Thu, 13 Feb 2020 02:46:05 +0300 Message-Id: <20200212234607.11521-11-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully supported by that driver. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e512e606eabd..1e3b85923ca3 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -95,6 +95,10 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && + of_machine_is_compatible("nvidia,tegra30")) + platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { From patchwork Wed Feb 12 23:46:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379391 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 61E73109A for ; Wed, 12 Feb 2020 23:46:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 411BD222C2 for ; Wed, 12 Feb 2020 23:46:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PG7Udi8b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729431AbgBLXqw (ORCPT ); Wed, 12 Feb 2020 18:46:52 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:44289 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729428AbgBLXqp (ORCPT ); Wed, 12 Feb 2020 18:46:45 -0500 Received: by mail-lj1-f193.google.com with SMTP id q8so4394901ljj.11; Wed, 12 Feb 2020 15:46:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xq9tBk/6KoDVPMtQ/rhYvGgBAgv98Cu3SgI5vW4OCek=; b=PG7Udi8bcc2n1H3a05otjSOGGZCtsp6Rn9pVmskrOMGeztPARSLFX0O2ABD02/dlX4 XlBM5H9j8o9N2gKre+eTpgRf9oErS/UpIierdVRE9nPOTVWySlNP137HzqxNbYqoR3Co T6ouxcfB/eAPrkwLbT+QoUCqoe0IzrS1b9iEffsMAaRn3BYf43C59oew3KC5aZ8/Z58x hENhGeecIMAr/RGpgEPizN+rjuXfngJBxrLNotxMag5tqJkdhBK8uB/rP30SpZBv+dVM kEAEGKK12rnPYziQdpCu2ATub2fbMAN1JeknXmC2sfB4QLGrT6RIEznz8U5G9i33okcM t5dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xq9tBk/6KoDVPMtQ/rhYvGgBAgv98Cu3SgI5vW4OCek=; b=r5ruepCdM5w0FroFneNdV1/JUT+ZmQWKOj/29V+Zts5+dbVgEGaFiZNL7jKCkfZ5CC xFE69HJW99BnXmzciMZa/CHSyNJFSC4oHCviiQTXj1vnlaC9U4DqRWgA1Y2jLJUPuQY7 yA/wyqSFAqOhjtnsz/+FIuAxecO14SEX9GdqUGdk+PYxah26gwQ32wR3nkXFQUdK1fnF g2RkaZytx+bP8agCIyXCfR7JhZJ0DW3sNSxFxn9J4wWrcUi/Nu/c+NLSwW/CvpPqDu4S R6qwWjbScfBiNNutPyfoIYlyFNoYODbGzUiPN9qBf4EgpCZqYVOwZj8SrLRqvnLyxn7G /YsQ== X-Gm-Message-State: APjAAAUWeB4pQQkjitqfTQqP+76JjfMjYLCCVITWrxGCMi55YWuMychI tgTIUGArE+oofSAtRA8Exbc= X-Google-Smtp-Source: APXvYqyvFrklEk7ubbXdiW8Kd821C04G0XWZws5U+xsziFH/pjA21sNz4bQ+O/HFWS2tepUSkdm8pg== X-Received: by 2002:a2e:a0d0:: with SMTP id f16mr9166327ljm.130.1581551202375; Wed, 12 Feb 2020 15:46:42 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:41 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 11/12] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Date: Thu, 13 Feb 2020 02:46:06 +0300 Message-Id: <20200212234607.11521-12-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Set min/max voltage and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index a3b0f3555cd2..6ebb3105af9e 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1806,9 +1806,14 @@ vdd2_reg: vdd2 { vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; vio_reg: vio { @@ -1868,17 +1873,22 @@ ldo8_reg: ldo8 { }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; + + nvidia,tegra-core-regulator; }; }; From patchwork Wed Feb 12 23:46:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11379383 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 16B6B109A for ; Wed, 12 Feb 2020 23:46:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EC52A24650 for ; Wed, 12 Feb 2020 23:46:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DPJAFE4X" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729361AbgBLXqr (ORCPT ); Wed, 12 Feb 2020 18:46:47 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:38854 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729431AbgBLXqq (ORCPT ); Wed, 12 Feb 2020 18:46:46 -0500 Received: by mail-lj1-f194.google.com with SMTP id w1so4432697ljh.5; Wed, 12 Feb 2020 15:46:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tdwll2I+0UIi7XhGuE9ZdnnXdDMdxuduY/8e8BdrqG0=; b=DPJAFE4Xa0zWnM4wQBIUIw+9iy542KOe40KcuQLCRhxoMVl6zFobIkvzwIeFRTpd0z NNmpDp2C4rpRYwl5z9hq6RzpwXXJupuSzW65NTMjHUrO1U9UsuyliLiItt4GEnuljSjY ANL2x3l5c/D+xLDYZW+NGcZoXj4k5QI/Mx6KUie7HQZl9UJu4+QXDIqrd4ISmpWMpuUd w44TWa/ctADXqby1JOlga4Hdnk8QCe3Mrzd1XPlnnvzHdI4hJ+7K4itvOVW3oYNxg1aR +6N0yuF0a57AFRH0xk1hx40nE3SmJ13xJEAV7rWlLB/M+iGZGFU0W/VrS/oMhzBaaMvo cD+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tdwll2I+0UIi7XhGuE9ZdnnXdDMdxuduY/8e8BdrqG0=; b=OSvHqD50wigET06TYzG8lV6QSJSss3FzZAy0BtwrXkseZW0dBPpcTj9VgqUJGWx8Ij An5xWBr6r5TNJs7ddnHukTM02efn6Ma8cK2f/OsI/yMoGoDY77ZNp4UsKmJXUlJXWDBS znzVwKnRgUSuJNwhJRK4jsl2VzidJk/KEwudXSasBwbbXhNLqKJrDIOoooK5S8W5mdTQ daWm92mrnnm145HsW2VFffoxdgix7I/QyI3+L8kqTe70526v0iSbtVxmfhBwOLt1VVta mL2pOfkauTLTRb5Wy/2+FZYGSe0keCD8tEqi0mwiW1fMPl8I3bnrHK3uoI9Lbjmo787P 5EXA== X-Gm-Message-State: APjAAAVbKLqGaHD2xTCkDVRwQOtiEVdsqS6W1zoh/m08WJTx0U2q71Jj FfrcdB3PYxUF9xVj2z25QGQ= X-Google-Smtp-Source: APXvYqyzrEP3eOlPkO2+R7iNd00URCRT1RLgY23Okr2hcs4KDOBHef8XQdAAXw/pMjkkAafdhVyj5Q== X-Received: by 2002:a2e:90f:: with SMTP id 15mr8787275ljj.120.1581551203538; Wed, 12 Feb 2020 15:46:43 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id u15sm234453lfl.87.2020.02.12.15.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:46:43 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 12/12] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Date: Thu, 13 Feb 2020 02:46:07 +0300 Message-Id: <20200212234607.11521-13-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212234607.11521-1-digetx@gmail.com> References: <20200212234607.11521-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 6ebb3105af9e..86556622be25 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" / { model = "NVIDIA Tegra30 Beaver evaluation board"; @@ -2124,4 +2126,26 @@ sound { <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };