From patchwork Sun Feb 16 19:20:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11384637 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C21817F0 for ; Sun, 16 Feb 2020 19:21:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E101424676 for ; Sun, 16 Feb 2020 19:21:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="s8KRaf6N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726701AbgBPTVb (ORCPT ); Sun, 16 Feb 2020 14:21:31 -0500 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.81]:12710 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725989AbgBPTVJ (ORCPT ); Sun, 16 Feb 2020 14:21:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1581880865; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=ZWD/ywS/oI+HLIcOn+2Tq95XFdQI8KmNFnFWbSMeLFw=; b=s8KRaf6Na34RYa2slD+nrGEZhHLGcCwb/JNLW/V5FwUhbqrNQopi4Gj1Cyu6oexSDT aCPZC/vJE1Ltj020skAIWO8PTAanqKwmiTzp2mHCVbKFSh8O+L1/v8AmZ3x2DsFgny1W 9RK2UyDvbQo3iVFnA1rUY6SvUMFR4HnL3eU+MOtcfG2RyuIVtcMPnM4HKQE4sjHAQGqs FxMjKsxWkDy6tgxT6CtVrFtforD5wZsapZ/K9o0TsBgw4HER96M7B/TKgFWnISw7HMkP LtQXeApJL/yOWDhGMokEqIm9xdRru8EqxgtLuUYiuQtf0zc6N+ES0tODbBMky4DDJi5u cg2A== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1OAA2UNf2M0OoPPevMB" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1GJKsJlY (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 16 Feb 2020 20:20:54 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [RFC v3 1/9] nvmem: add driver for JZ4780 efuse Date: Sun, 16 Feb 2020 20:20:43 +0100 Message-Id: <40134efb901b83bb1b6bc64af0b312756459c31c.1581880851.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre Signed-off-by: H. Nikolaus Schaller (Signed-off-by: Paul Cercueil ) --- drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 249 +++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+) create mode 100644 drivers/nvmem/jz4780-efuse.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 35efab1ba8d9..10f8e08f5e31 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -55,6 +55,16 @@ config NVMEM_IMX_OCOTP_SCU This is a driver for the SCU On-Chip OTP Controller (OCOTP) available on i.MX8 SoCs. +config JZ4780_EFUSE + tristate "JZ4780 EFUSE Memory Support" + depends on MACH_JZ4780 || COMPILE_TEST + depends on HAS_IOMEM + help + Say Y here to include support for JZ4780 efuse memory found on + all JZ4780 SoC based devices. + To compile this driver as a module, choose M here: the module + will be called nvmem_jz4780_efuse. + config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6b466cd1427b..65a268d17807 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +nvmem_jz4780_efuse-y := jz4780-efuse.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c new file mode 100644 index 000000000000..ac03e1900ef9 --- /dev/null +++ b/drivers/nvmem/jz4780-efuse.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * JZ4780 EFUSE Memory Support driver + * + * Copyright (c) 2017 PrasannaKumar Muralidharan + * Copyright (c) 2020 H. Nikolaus Schaller + */ + +/* + * Currently supports JZ4780 efuse which has 8K programmable bit. + * Efuse is separated into seven segments as below: + * + * ----------------------------------------------------------------------- + * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit | + * ----------------------------------------------------------------------- + * + * The rom itself is accessed using a 9 bit address line and an 8 word wide bus + * which reads/writes based on strobes. The strobe is configured in the config + * register and is based on number of cycles of the bus clock. + * + * Driver supports read only as the writes are done in the Factory. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define JZ_EFUCTRL (0x0) /* Control Register */ +#define JZ_EFUCFG (0x4) /* Configure Register*/ +#define JZ_EFUSTATE (0x8) /* Status Register */ +#define JZ_EFUDATA(n) (0xC + (n)*4) + +#define JZ_EFUSE_START_ADDR 0x200 + +#define JZ_EFUSE_EFUCTRL_CS BIT(30) +#define JZ_EFUSE_EFUCTRL_ADDR_MASK 0x1FF +#define JZ_EFUSE_EFUCTRL_ADDR_SHIFT 21 +#define JZ_EFUSE_EFUCTRL_LEN_MASK 0x1F +#define JZ_EFUSE_EFUCTRL_LEN_SHIFT 16 +#define JZ_EFUSE_EFUCTRL_PG_EN BIT(15) +#define JZ_EFUSE_EFUCTRL_WR_EN BIT(1) +#define JZ_EFUSE_EFUCTRL_RD_EN BIT(0) + +#define JZ_EFUSE_EFUCFG_INT_EN BIT(31) +#define JZ_EFUSE_EFUCFG_RD_ADJ_MASK 0xF +#define JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT 20 +#define JZ_EFUSE_EFUCFG_RD_STR_MASK 0xF +#define JZ_EFUSE_EFUCFG_RD_STR_SHIFT 16 +#define JZ_EFUSE_EFUCFG_WR_ADJ_MASK 0xF +#define JZ_EFUSE_EFUCFG_WR_ADJ_SHIFT 12 +#define JZ_EFUSE_EFUCFG_WR_STR_MASK 0xFFF +#define JZ_EFUSE_EFUCFG_WR_STR_SHIFT 0 + +#define JZ_EFUSE_EFUSTATE_WR_DONE BIT(1) +#define JZ_EFUSE_EFUSTATE_RD_DONE BIT(0) + +struct jz4780_efuse { + struct device *dev; + void __iomem *iomem; + struct clk *clk; + unsigned int rd_adj; + unsigned int rd_strobe; +}; + +/* We read 32 byte chunks to avoid complexity in the driver. */ +static int jz4780_efuse_read_32bytes(struct jz4780_efuse *efuse, char *buf, + unsigned int addr) +{ + unsigned int tmp = 0; + int i = 0; + int timeout = 1000; + int size = 32; + + /* 1. Set config register */ + tmp = readl(efuse->iomem + JZ_EFUCFG); + tmp &= ~((JZ_EFUSE_EFUCFG_RD_ADJ_MASK << JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT) + | (JZ_EFUSE_EFUCFG_RD_STR_MASK << JZ_EFUSE_EFUCFG_RD_STR_SHIFT)); + tmp |= (efuse->rd_adj << JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT) + | (efuse->rd_strobe << JZ_EFUSE_EFUCFG_RD_STR_SHIFT); + writel(tmp, efuse->iomem + JZ_EFUCFG); + + /* + * 2. Set control register to indicate what to read data address, + * read data numbers and read enable. + */ + tmp = readl(efuse->iomem + JZ_EFUCTRL); + tmp &= ~(JZ_EFUSE_EFUCFG_RD_STR_SHIFT + | (JZ_EFUSE_EFUCTRL_ADDR_MASK << JZ_EFUSE_EFUCTRL_ADDR_SHIFT) + | JZ_EFUSE_EFUCTRL_PG_EN | JZ_EFUSE_EFUCTRL_WR_EN + | JZ_EFUSE_EFUCTRL_WR_EN); + + /* Need to select CS bit if address accesses upper 4Kbits memory */ + if (addr >= (JZ_EFUSE_START_ADDR + 512)) + tmp |= JZ_EFUSE_EFUCTRL_CS; + + tmp |= (addr << JZ_EFUSE_EFUCTRL_ADDR_SHIFT) + | ((size - 1) << JZ_EFUSE_EFUCTRL_LEN_SHIFT) + | JZ_EFUSE_EFUCTRL_RD_EN; + writel(tmp, efuse->iomem + JZ_EFUCTRL); + + /* + * 3. Wait status register RD_DONE set to 1 or EFUSE interrupted, + * software can read EFUSE data buffer 0 - 8 registers. + */ + do { + tmp = readl(efuse->iomem + JZ_EFUSTATE); + usleep_range(1000, 2000); + if (timeout--) + break; + } while (!(tmp & JZ_EFUSE_EFUSTATE_RD_DONE)); + + if (timeout <= 0) { + dev_err(efuse->dev, "Timed out while reading\n"); + return -EAGAIN; + } + + for (i = 0; i < (size / 4); i++) + *((unsigned int *)(buf + i * 4)) + = readl(efuse->iomem + JZ_EFUDATA(i)); + + return 0; +} + +/* main entry point */ +static int jz4780_efuse_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct jz4780_efuse *efuse = context; + int ret; + + while (bytes > 0) { + unsigned int start = offset & ~(32 - 1); + unsigned chunk = min(bytes, (start + 32 - offset)); + + if (start == offset && chunk == 32) { + ret = jz4780_efuse_read_32bytes(efuse, val, start); + if (ret < 0) + return ret; + + } else { + char buf[32]; + ret = jz4780_efuse_read_32bytes(efuse, buf, start); + if (ret < 0) + return ret; + + memcpy(val, &buf[offset - start], chunk); + } + + val += chunk; + offset += chunk; + bytes -= chunk; + } + + return 0; +} + +static struct nvmem_config jz4780_efuse_nvmem_config = { + .name = "jz4780-efuse", + .read_only = true, + .size = 1024, + .word_size = 1, + .stride = 1, + .owner = THIS_MODULE, + .reg_read = jz4780_efuse_read, +}; + +static int jz4780_efuse_probe(struct platform_device *pdev) +{ + struct nvmem_device *nvmem; + struct jz4780_efuse *efuse; + struct resource *res; + unsigned long clk_rate; + struct device *dev = &pdev->dev; + + efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL); + if (!efuse) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + efuse->iomem = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(efuse->iomem)) + return PTR_ERR(efuse->iomem); + + efuse->clk = devm_clk_get(&pdev->dev, "bus_clk"); + if (IS_ERR(efuse->clk)) + return PTR_ERR(efuse->clk); + + clk_rate = clk_get_rate(efuse->clk); + /* + * rd_adj and rd_strobe are 4 bit values + * bus clk period * (rd_adj + 1) > 6.5ns + * bus clk period * (rd_adj + 5 + rd_strobe) > 35ns + */ + efuse->rd_adj = (((6500 * (clk_rate / 1000000)) / 1000000) + 1) - 1; + efuse->rd_strobe = ((((35000 * (clk_rate / 1000000)) / 1000000) + 1) + - 5 - efuse->rd_adj); + + if ((efuse->rd_adj > 0x1F) || (efuse->rd_strobe > 0x1F)) { + dev_err(&pdev->dev, "Cannot set clock configuration\n"); + return -EINVAL; + } + efuse->dev = dev; + + jz4780_efuse_nvmem_config.dev = &pdev->dev; + jz4780_efuse_nvmem_config.priv = efuse; + + nvmem = nvmem_register(&jz4780_efuse_nvmem_config); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); + + platform_set_drvdata(pdev, nvmem); + + return 0; +} + +static int jz4780_efuse_remove(struct platform_device *pdev) +{ + struct nvmem_device *nvmem = platform_get_drvdata(pdev); + + nvmem_unregister(nvmem); + + return 0; +} + +static const struct of_device_id jz4780_efuse_match[] = { + { .compatible = "ingenic,jz4780-efuse" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, jz4780_efuse_match); + +static struct platform_driver jz4780_efuse_driver = { + .probe = jz4780_efuse_probe, + .remove = jz4780_efuse_remove, + .driver = { + .name = "jz4780-efuse", + .of_match_table = jz4780_efuse_match, + }, +}; +module_platform_driver(jz4780_efuse_driver); + +MODULE_AUTHOR("PrasannaKumar Muralidharan "); +MODULE_AUTHOR("H. Nikolaus Schaller "); +MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sun Feb 16 19:20:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11384631 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 34E33109A for ; Sun, 16 Feb 2020 19:21:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 045312086A for ; Sun, 16 Feb 2020 19:21:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="Ile70HFn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727946AbgBPTVS (ORCPT ); Sun, 16 Feb 2020 14:21:18 -0500 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.80]:27187 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726020AbgBPTVK (ORCPT ); Sun, 16 Feb 2020 14:21:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1581880865; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=+WXKJfjQk4+uCAFCxbcqyDka7uNwOTJLqOppo9UdKOA=; b=Ile70HFns8RbRVh+gFHWgl3gZJNrclFf867CiPvGZdlj+q7voVGP/cIs3cEAlRPI5a xguKZb9siW46CdoVaVU2prz0DoLMOJfNLlZCn5NB4r7TH7Om8atpoll77gqmP4EHRxIx LW0ka/2s2IfTWYxC8ocm7n2t7xwoAZeW/X3yGtTiQN4IuDnESUo8gAQq9p84LDoSMaoH L90xxAyMdbjeU7ejqoa5OIqa3KqeFa/ABAOq1Bel/y79zWfWhyUDrRkUDmCZjgF6dql4 KDBNVMhEmNravPT1mDBh0qfI/qaZx4BDdKssIvG2X9WBSNk6Zo/7TdBZFkZW0oFY/4TS UW3w== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1OAA2UNf2M0OoPPevMB" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1GJKsJlZ (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 16 Feb 2020 20:20:54 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [RFC v3 2/9] rework to use regmap Date: Sun, 16 Feb 2020 20:20:44 +0100 Message-Id: <0ec45ea82ef933a141215d0dd747c1c5dc09a980.1581880851.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Paul Cercueil should/will be squashed into the previous commit ("nvmem: add driver for JZ4780 efuse") but is kept separately for this RFC to make the modifications more transparent. --- drivers/nvmem/jz4780-efuse.c | 179 ++++++++++++++++------------------- 1 file changed, 84 insertions(+), 95 deletions(-) diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c index ac03e1900ef9..79dc42431bfe 100644 --- a/drivers/nvmem/jz4780-efuse.c +++ b/drivers/nvmem/jz4780-efuse.c @@ -30,38 +30,35 @@ #include #include -#define JZ_EFUCTRL (0x0) /* Control Register */ -#define JZ_EFUCFG (0x4) /* Configure Register*/ -#define JZ_EFUSTATE (0x8) /* Status Register */ -#define JZ_EFUDATA(n) (0xC + (n)*4) - -#define JZ_EFUSE_START_ADDR 0x200 - -#define JZ_EFUSE_EFUCTRL_CS BIT(30) -#define JZ_EFUSE_EFUCTRL_ADDR_MASK 0x1FF -#define JZ_EFUSE_EFUCTRL_ADDR_SHIFT 21 -#define JZ_EFUSE_EFUCTRL_LEN_MASK 0x1F -#define JZ_EFUSE_EFUCTRL_LEN_SHIFT 16 -#define JZ_EFUSE_EFUCTRL_PG_EN BIT(15) -#define JZ_EFUSE_EFUCTRL_WR_EN BIT(1) -#define JZ_EFUSE_EFUCTRL_RD_EN BIT(0) - -#define JZ_EFUSE_EFUCFG_INT_EN BIT(31) -#define JZ_EFUSE_EFUCFG_RD_ADJ_MASK 0xF -#define JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT 20 -#define JZ_EFUSE_EFUCFG_RD_STR_MASK 0xF -#define JZ_EFUSE_EFUCFG_RD_STR_SHIFT 16 -#define JZ_EFUSE_EFUCFG_WR_ADJ_MASK 0xF -#define JZ_EFUSE_EFUCFG_WR_ADJ_SHIFT 12 -#define JZ_EFUSE_EFUCFG_WR_STR_MASK 0xFFF -#define JZ_EFUSE_EFUCFG_WR_STR_SHIFT 0 - -#define JZ_EFUSE_EFUSTATE_WR_DONE BIT(1) -#define JZ_EFUSE_EFUSTATE_RD_DONE BIT(0) +#define JZ_EFUCTRL (0x0) /* Control Register */ +#define JZ_EFUCFG (0x4) /* Configure Register*/ +#define JZ_EFUSTATE (0x8) /* Status Register */ +#define JZ_EFUDATA(n) (0xC + (n)*4) + +#define EFUCTRL_ADDR_MASK 0x3FF +#define EFUCTRL_ADDR_SHIFT 21 +#define EFUCTRL_LEN_MASK 0x1F +#define EFUCTRL_LEN_SHIFT 16 +#define EFUCTRL_PG_EN BIT(15) +#define EFUCTRL_WR_EN BIT(1) +#define EFUCTRL_RD_EN BIT(0) + +#define EFUCFG_INT_EN BIT(31) +#define EFUCFG_RD_ADJ_MASK 0xF +#define EFUCFG_RD_ADJ_SHIFT 20 +#define EFUCFG_RD_STR_MASK 0xF +#define EFUCFG_RD_STR_SHIFT 16 +#define EFUCFG_WR_ADJ_MASK 0xF +#define EFUCFG_WR_ADJ_SHIFT 12 +#define EFUCFG_WR_STR_MASK 0xFFF +#define EFUCFG_WR_STR_SHIFT 0 + +#define EFUSTATE_WR_DONE BIT(1) +#define EFUSTATE_RD_DONE BIT(0) struct jz4780_efuse { struct device *dev; - void __iomem *iomem; + struct regmap *map; struct clk *clk; unsigned int rd_adj; unsigned int rd_strobe; @@ -71,59 +68,29 @@ struct jz4780_efuse { static int jz4780_efuse_read_32bytes(struct jz4780_efuse *efuse, char *buf, unsigned int addr) { - unsigned int tmp = 0; - int i = 0; - int timeout = 1000; - int size = 32; - - /* 1. Set config register */ - tmp = readl(efuse->iomem + JZ_EFUCFG); - tmp &= ~((JZ_EFUSE_EFUCFG_RD_ADJ_MASK << JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT) - | (JZ_EFUSE_EFUCFG_RD_STR_MASK << JZ_EFUSE_EFUCFG_RD_STR_SHIFT)); - tmp |= (efuse->rd_adj << JZ_EFUSE_EFUCFG_RD_ADJ_SHIFT) - | (efuse->rd_strobe << JZ_EFUSE_EFUCFG_RD_STR_SHIFT); - writel(tmp, efuse->iomem + JZ_EFUCFG); - - /* - * 2. Set control register to indicate what to read data address, - * read data numbers and read enable. - */ - tmp = readl(efuse->iomem + JZ_EFUCTRL); - tmp &= ~(JZ_EFUSE_EFUCFG_RD_STR_SHIFT - | (JZ_EFUSE_EFUCTRL_ADDR_MASK << JZ_EFUSE_EFUCTRL_ADDR_SHIFT) - | JZ_EFUSE_EFUCTRL_PG_EN | JZ_EFUSE_EFUCTRL_WR_EN - | JZ_EFUSE_EFUCTRL_WR_EN); - - /* Need to select CS bit if address accesses upper 4Kbits memory */ - if (addr >= (JZ_EFUSE_START_ADDR + 512)) - tmp |= JZ_EFUSE_EFUCTRL_CS; - - tmp |= (addr << JZ_EFUSE_EFUCTRL_ADDR_SHIFT) - | ((size - 1) << JZ_EFUSE_EFUCTRL_LEN_SHIFT) - | JZ_EFUSE_EFUCTRL_RD_EN; - writel(tmp, efuse->iomem + JZ_EFUCTRL); - - /* - * 3. Wait status register RD_DONE set to 1 or EFUSE interrupted, - * software can read EFUSE data buffer 0 - 8 registers. - */ - do { - tmp = readl(efuse->iomem + JZ_EFUSTATE); - usleep_range(1000, 2000); - if (timeout--) - break; - } while (!(tmp & JZ_EFUSE_EFUSTATE_RD_DONE)); - - if (timeout <= 0) { - dev_err(efuse->dev, "Timed out while reading\n"); - return -EAGAIN; + unsigned int tmp; + u32 ctrl; + int ret; + const int size = 32; + + ctrl = (addr << EFUCTRL_ADDR_SHIFT) + | ((size - 1) << EFUCTRL_LEN_SHIFT) + | EFUCTRL_RD_EN; + + regmap_update_bits(efuse->map, JZ_EFUCTRL, + (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) | + (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) | + EFUCTRL_PG_EN | EFUCTRL_WR_EN | EFUCTRL_RD_EN, ctrl); + + ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE, + tmp, tmp & EFUSTATE_RD_DONE, + 1 * MSEC_PER_SEC, 50 * MSEC_PER_SEC); + if (ret < 0) { + dev_err(efuse->dev, "Time out while reading efuse data"); + return ret; } - for (i = 0; i < (size / 4); i++) - *((unsigned int *)(buf + i * 4)) - = readl(efuse->iomem + JZ_EFUDATA(i)); - - return 0; + return regmap_bulk_read(efuse->map, JZ_EFUDATA(0), buf, size / sizeof(u32)); } /* main entry point */ @@ -132,12 +99,13 @@ static int jz4780_efuse_read(void *context, unsigned int offset, { struct jz4780_efuse *efuse = context; int ret; + const int size = 32; while (bytes > 0) { - unsigned int start = offset & ~(32 - 1); - unsigned chunk = min(bytes, (start + 32 - offset)); + unsigned int start = offset & ~(size - 1); + unsigned chunk = min(bytes, (start + size) - offset); - if (start == offset && chunk == 32) { + if (start == offset && chunk == size) { ret = jz4780_efuse_read_32bytes(efuse, val, start); if (ret < 0) return ret; @@ -159,7 +127,7 @@ static int jz4780_efuse_read(void *context, unsigned int offset, return 0; } -static struct nvmem_config jz4780_efuse_nvmem_config = { +static __initdata struct nvmem_config jz4780_efuse_nvmem_config = { .name = "jz4780-efuse", .read_only = true, .size = 1024, @@ -169,28 +137,42 @@ static struct nvmem_config jz4780_efuse_nvmem_config = { .reg_read = jz4780_efuse_read, }; +static const struct regmap_config jz4780_efuse_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = JZ_EFUDATA(7), +}; + static int jz4780_efuse_probe(struct platform_device *pdev) { struct nvmem_device *nvmem; struct jz4780_efuse *efuse; - struct resource *res; + struct nvmem_config cfg; unsigned long clk_rate; struct device *dev = &pdev->dev; + void __iomem *regs; - efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL); + efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); if (!efuse) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - efuse->iomem = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (IS_ERR(efuse->iomem)) - return PTR_ERR(efuse->iomem); + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + efuse->map = devm_regmap_init_mmio(dev, regs, + &jz4780_efuse_regmap_config); + if (IS_ERR(efuse->map)) + return PTR_ERR(efuse->map); - efuse->clk = devm_clk_get(&pdev->dev, "bus_clk"); + efuse->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(efuse->clk)) return PTR_ERR(efuse->clk); clk_rate = clk_get_rate(efuse->clk); + + efuse->dev = dev; /* * rd_adj and rd_strobe are 4 bit values * bus clk period * (rd_adj + 1) > 6.5ns @@ -204,12 +186,18 @@ static int jz4780_efuse_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Cannot set clock configuration\n"); return -EINVAL; } - efuse->dev = dev; - jz4780_efuse_nvmem_config.dev = &pdev->dev; - jz4780_efuse_nvmem_config.priv = efuse; + regmap_update_bits(efuse->map, JZ_EFUCFG, + (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) | + (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT), + (efuse->rd_adj << EFUCFG_RD_ADJ_SHIFT) | + (efuse->rd_strobe << EFUCFG_RD_STR_SHIFT)); + + cfg = jz4780_efuse_nvmem_config; + cfg.dev = &pdev->dev; + cfg.priv = efuse; - nvmem = nvmem_register(&jz4780_efuse_nvmem_config); + nvmem = nvmem_register(&cfg); if (IS_ERR(nvmem)) return PTR_ERR(nvmem); @@ -245,5 +233,6 @@ module_platform_driver(jz4780_efuse_driver); MODULE_AUTHOR("PrasannaKumar Muralidharan "); MODULE_AUTHOR("H. Nikolaus Schaller "); +MODULE_AUTHOR("Paul Cercueil "); MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver"); MODULE_LICENSE("GPL v2"); From patchwork Sun Feb 16 19:20:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11384635 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A650917F0 for ; Sun, 16 Feb 2020 19:21:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 885E824125 for ; Sun, 16 Feb 2020 19:21:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="bMNA2fs6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727691AbgBPTVJ (ORCPT ); Sun, 16 Feb 2020 14:21:09 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.101]:36624 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726059AbgBPTVI (ORCPT ); Sun, 16 Feb 2020 14:21:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1581880865; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=x19Yc0lwgVFAHPYdn2uCmqE96DBTXWvCWwEjKHcs+zU=; b=bMNA2fs65RrwGNGGQGziAS8PIpPY/YhTOUNGQyp3JUs7zK1Ae2QL3Gc9mNHSyafHhv Poqr/d171MM7v1jF1BxYGQAIaX+XGEJV0fmKfWn+HWh0BV0WKBAR8ySLn2eQ53amqaTx SZBeLdI189egGqUPQw/wvzpevw4c3xIdyr4U58yo+Bkzb+Y+2G+UB/pb+aQsG+szEP2a 8G6oqa7nFUb3cjc83CxEs6F01xNigZLwJtMs9eM/4v+q0EvZNzxfPZKGxJrohfaBYnta rorBZg6uSVLcTPRtusDqPNBO1TXZD77xJoJCls0t3Y3R5XU7ARNnagn9qvPLwNrpNtAv TqPA== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1OAA2UNf2M0OoPPevMB" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1GJKtJla (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 16 Feb 2020 20:20:55 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [RFC v3 3/9] Bindings: nvmem: add bindings for JZ4780 efuse Date: Sun, 16 Feb 2020 20:20:45 +0100 Message-Id: <39c7917248e29e365b6939fed2be0d00d30b11df.1581880851.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre Signed-off-by: H. Nikolaus Schaller --- .../bindings/nvmem/ingenic,jz4780-efuse.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt new file mode 100644 index 000000000000..339e74daa9a9 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.txt @@ -0,0 +1,17 @@ +Ingenic JZ EFUSE driver bindings + +Required properties: +- "compatible" Must be set to "ingenic,jz4780-efuse" +- "reg" Register location and length +- "clocks" Handle for the ahb clock for the efuse. +- "clock-names" Must be "bus_clk" + +Example: + +efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0x2c>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; +}; From patchwork Sun Feb 16 19:20:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11384643 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A4F54109A for ; Sun, 16 Feb 2020 19:21:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8529220857 for ; Sun, 16 Feb 2020 19:21:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="T7JQXDBZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727592AbgBPTVJ (ORCPT ); Sun, 16 Feb 2020 14:21:09 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.102]:21592 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726037AbgBPTVI (ORCPT ); Sun, 16 Feb 2020 14:21:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1581880865; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=gTk8MRIaL+Zoo6AYmT56Y6jd8ZDzvosVYa8gE1FYjOU=; b=T7JQXDBZcIbnomwlB8Y3FhhdxbInHoPy1im1+4E/uo8rhXDGvLiRiwVdmW5wqDBilo 6N/F5vln542BtN6ROLefQyLi9WpGdTQpe4pT7oMJKbpnA+rppgVTVQc3Tkryr5hfvwul fMoWvKUJHAgqfSZk4Ke3eBQmwDHMbsy9ia3UJxkklywrEZLv1lyXzQEiHrzD5EjwceEt IVoSloC4tKeG+iG4szvHYd+SDtDQ0gi9tHx5ek2ZGH+QDFZNCGwAd6MaqpzbcDyFJQQD 04AdQUg9agr0cIy4P3L8484rZiGx7b6tr0ue5qhJX5Cw7LHUyU2gwg4xhaDc4lWs3mRX sK7A== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1OAA2UNf2M0OoPPevMB" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1GJKtJlb (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 16 Feb 2020 20:20:55 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [RFC v3 4/9] Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI Date: Sun, 16 Feb 2020 20:20:46 +0100 Message-Id: <1b73eead5d7237cddfcbe835bfbf31ae89fb6b61.1581880851.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre --- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse diff --git a/Documentation/ABI/testing/sysfs-driver-jz4780-efuse b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file mode 100644 index 000000000000..bb6f5d6ceea0 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse @@ -0,0 +1,16 @@ +What: /sys/devices/*//nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan +Description: read-only access to the efuse on the Ingenic JZ4780 SoC + The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot key +Users: any user space application which wants to read the Chip + and Customer ID From patchwork Sun Feb 16 19:20:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11384627 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF39E109A for ; Sun, 16 Feb 2020 19:21:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F00BD20857 for ; Sun, 16 Feb 2020 19:21:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="OEFPZwUh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726482AbgBPTVI (ORCPT ); Sun, 16 Feb 2020 14:21:08 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.175]:18748 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726043AbgBPTVI (ORCPT ); Sun, 16 Feb 2020 14:21:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1581880865; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=Ube8VBr6jQ46GNcYtt3t/7muF+rpEcuH7jTgqb7/If4=; b=OEFPZwUhNwRxALw7zK1OKmlIQoLcvy+XECwgqWA6vu5IHkuiaLQ4Um5Qo0wMkUF1MQ 6g2v5kOX0MvAHRe1PuKZslSGJ17rwAnaHXP2+y0PO5xSg0MyEpcicLPfsWyZWp3ezaPV VeGmz2MndUw6C1AYAP5uKCXWbyeP0WNX8Hxgu7v3WMHq3pEC2lBZIINeL1B8KJAovn6O XQco8iL77YDoUkouDQpqKFLz633EoS0RzjuK2FU4gQ6UhGMSAu8Y2bYdgMEWwPI9RIOX qKMUgQmsEwPYljPM/8mRGbXxalTEp2T1o71V5M+olSFbBV/TWqATVD1YQxvjOn5LRcY4 B5Cg== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1OAA2UNf2M0OoPPevMB" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1GJKuJlc (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 16 Feb 2020 20:20:56 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [RFC v3 5/9] nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver Date: Sun, 16 Feb 2020 20:20:47 +0100 Message-Id: <1f956bba79044d8787adb9e00c19e4780f50241a.1581880851.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only expose a read only access to the entire 8K bits efuse memory. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 33f811f517d4..88f247456a48 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8270,6 +8270,11 @@ M: Zubair Lutfullah Kakakhel S: Maintained F: drivers/dma/dma-jz4780.c +INGENIC JZ4780 EFUSE Driver +M: PrasannaKumar Muralidharan +S: Maintained +F: drivers/nvmem/jz4780-efuse.c + INGENIC JZ4780 NAND DRIVER M: Harvey Hunt L: linux-mtd@lists.infradead.org From patchwork Sun Feb 16 19:20:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11384645 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB628109A for ; Sun, 16 Feb 2020 19:21:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8CB64227BF for ; Sun, 16 Feb 2020 19:21:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="BABAFtaD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726716AbgBPTVI (ORCPT ); Sun, 16 Feb 2020 14:21:08 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.100]:16455 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726036AbgBPTVI (ORCPT ); Sun, 16 Feb 2020 14:21:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1581880864; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=vmDYEr1Ci3CaW1+MaKFxny28O8OXp6bacidAtKmGGQo=; b=BABAFtaDoAay2rDVcM7FElNPtwd8QpkxCcY7c3FZLwbzgS7BLcW0HsyuiDnC/bkhWl qfNLuj7tatPF/WY2NoMp/0xNKBTkbsmRLphlgfYaUzQNLiznmTlPAU8newGUHWzHN+pj cJ+L/Y9VJK1BNlUu9U+TymjVOY0v4YLuIDc0CuT5HkreYRxRjvxOikDey78F94sZl8Ep pLbIvp5C017TwoG7lvTKXuo8YKcPZtYzKLwZrYQeQ3VFR4LGxjejUp0eR/bFViPfHidN KbTtYzwFgwP+7HoGEHkxvV2xLBG8VSrZCmDwefeTjzJQ90JgigmkZgl4ZbFkjARW/C7E uvMA== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1OAA2UNf2M0OoPPevMB" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1GJKuJld (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 16 Feb 2020 20:20:56 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [RFC v3 6/9] MIPS: DTS: JZ4780: define node for JZ4780 efuse Date: Sun, 16 Feb 2020 20:20:48 +0100 Message-Id: <974fc10f0134a4449f4d4ba545b651cd7f772542.1581880851.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and the ethernet mac address for the davicom dm9000 chip on the CI20 board. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre Signed-off-by: H. Nikolaus Schaller --- arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index 301b62da025e..4cc8abe675c2 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -393,7 +393,7 @@ nemc: nemc@13410000 { compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; + reg = <0x13410000 0x4c>; #address-cells = <2>; #size-cells = <1>; ranges = <1 0 0x1b000000 0x1000000 @@ -408,6 +408,21 @@ status = "disabled"; }; + efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0x2c>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "bus_clk"; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_addr: eth-mac-addr@0x22 { + reg = <0x22 0x6>; + }; + }; + dma: dma@13420000 { compatible = "ingenic,jz4780-dma"; reg = <0x13420000 0x400 From patchwork Sun Feb 16 19:20:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11384633 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 00133109A for ; Sun, 16 Feb 2020 19:21:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D5F8F227BF for ; Sun, 16 Feb 2020 19:21:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="ZGVJy+CL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726020AbgBPTVY (ORCPT ); Sun, 16 Feb 2020 14:21:24 -0500 Received: from mo4-p04-ob.smtp.rzone.de ([85.215.255.124]:20790 "EHLO mo4-p04-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726701AbgBPTVK (ORCPT ); Sun, 16 Feb 2020 14:21:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1581880866; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=3MxmeyOPuBNsjQw7Sua8KxvKXNHTrqUU51j9mzRygRA=; b=ZGVJy+CLGg7qMFtQq3wGiOilylMgo58v2sfpj/bwcu5ucKUPP+BDAMZ1tnPo1hV4QG OsqG3jafK9VlyrJ7YdMWvNFYauX/kX1c5On0bUr5qPiMkAdQug4LIAHGsK3m5BKmZvid KYThqp3ig10DgzPMWElgM12htqpzonUF/+OTfeMo4Vj4i5NuwyGq42Zo5YJVOnIAVIPY l9NhlmOCp5+eDCajvYNlGksQM+AhArs3WfqTJ4VMum8stYXjd3/CC3mxJ8M7bYWzoMJY BeCeK3dgBy07L75CFrPK0EQwC1ArFro+noxkJrfOv5diPyHX5ZGH+eMitD7LDVWmUCyE Zkkg== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1OAA2UNf2M0OoPPevMB" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1GJKvJle (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 16 Feb 2020 20:20:57 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [RFC v3 7/9] MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the default MAC address Date: Sun, 16 Feb 2020 20:20:49 +0100 Message-Id: <544dd607622a87741e3c02d61d581e42288ab960.1581880851.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org There is a default MAC address factory programmed into the eFuses of the JZ4780 chip. By using this every CI20 board has an individual but stable MAC address and DHCP can assing stable IP addresses. Signed-off-by: H. Nikolaus Schaller --- arch/mips/boot/dts/ingenic/ci20.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 1166f3203ff8..63b4b53b5df5 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -428,6 +428,9 @@ Optional input supply properties: interrupt-parent = <&gpe>; interrupts = <19 4>; + + nvmem-cells = <ð0_addr>; + nvmem-cell-names = "mac-address"; }; }; From patchwork Sun Feb 16 19:20:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11384639 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 175D8109A for ; Sun, 16 Feb 2020 19:21:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E31FD24125 for ; Sun, 16 Feb 2020 19:21:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="sMYcLkKY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728043AbgBPTVg (ORCPT ); Sun, 16 Feb 2020 14:21:36 -0500 Received: from mo4-p04-ob.smtp.rzone.de ([81.169.146.177]:31410 "EHLO mo4-p04-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726656AbgBPTVJ (ORCPT ); Sun, 16 Feb 2020 14:21:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1581880866; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=kPUcf/GvZL1nupNS3IZr+BX1pSqIjowqBPh5G4yQp6A=; b=sMYcLkKYljzx3CW+K12/ySPKYORsogyLsfboQogkNpay+H6AwI2azhykbL0uia4qhg sEQRTMOyyDLg3XsXIb4bFLdC7OR6vaOthPbYAX/xKKdCB25QnYfVVzlBbTxhpS2yTE8L h59Yeocjk4SOhO001gQi1nzHTanTYLGR0FpTQ+bsjUH58HqVhfF59hjwSdp4I2P6MATD A4ynOl5lBdH/nGuGsmHAFWCG5WJhpslQxTlYjVA7Woxyi5OjjZr55i81niSCGgbQtemB yZC1toxlW2A8cAZUPl6aPO+42ifavIz2abIFo+Auc7HpCxY6hdDgS8/WgNQBWG7BA9AE x7SA== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1OAA2UNf2M0OoPPevMB" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1GJKwJlf (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 16 Feb 2020 20:20:58 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [RFC v3 8/9] MIPS: CI20 defconfig: Probe efuse for CI20 Date: Sun, 16 Feb 2020 20:20:50 +0100 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Mathieu Malaterre MIPS Creator CI20 comes with JZ4780 SoC. Provides access to the efuse block using jz4780 efuse driver. Tested-by: H. Nikolaus Schaller Signed-off-by: Mathieu Malaterre --- arch/mips/configs/ci20_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index 6e613bbb6807..614dc18211bc 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -193,3 +193,5 @@ CONFIG_RC_DEVICES=y CONFIG_IR_GPIO_CIR=m CONFIG_IR_GPIO_TX=m CONFIG_RTC_DRV_PCF8563=m +CONFIG_NVMEM=y +CONFIG_JZ4780_EFUSE=y From patchwork Sun Feb 16 19:20:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11384641 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80B3E1820 for ; Sun, 16 Feb 2020 19:21:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6238F2467C for ; Sun, 16 Feb 2020 19:21:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="Zq0exAHU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728048AbgBPTVg (ORCPT ); Sun, 16 Feb 2020 14:21:36 -0500 Received: from mo4-p04-ob.smtp.rzone.de ([81.169.146.178]:13562 "EHLO mo4-p04-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726671AbgBPTVJ (ORCPT ); Sun, 16 Feb 2020 14:21:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1581880867; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=oqhgP+NtrwgBX56WD4djyrk4OHTirbJ1JPDtLAAIn4U=; b=Zq0exAHUW7mN6WAgqTWaIq3IQcsNs7q0p4lBZJ6SBxPmw74FuqNLXMt5k18mNJLBw3 u2vjKRTMYRVgIO5WX+iO8qLwNkDOwzL4aoKxovy3GaaRqA9B2BBS7gaWJCw0vcOovu2p 1CWIFviuiPz+xB0RcxzR9wq0N5ia56TySgJ959kbW2jLiFqRHGnNDoEW+Ic7hTwjia15 8JbAtUYXlB8GRQqv0jnYc7rBvDrOoWNVz7eLBpP3sHpLmR/uXG0N+9N0HR7USwEupWaC thBmKdbDb33YA8BbRYKAug8KyclWaU1RB/zMAymtk4u7tpR8gR3njKUxHfNjQ+uj9RU0 T34w== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1OAA2UNf2M0OoPPevMB" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1GJKwJlg (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sun, 16 Feb 2020 20:20:58 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [RFC v3 9/9] MIPS: CI20 defconfig: DEMO HACK: make DM9000 a module Date: Sun, 16 Feb 2020 20:20:51 +0100 Message-Id: <71ea739c7be432da356b4d3f7dca8b7658f3d2fb.1581880851.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org It appears that reading the ethernet mac address from NVMEM, i.e. through the jz4780-efuse driver, requires the jz4780-efuse driver to be up and running before the dm9000 driver is probed. This is because there is a registration mechanism for nvmem devices and consumers scan the global table. If the provider has not yet been registered, the required matching entry is not found and the consumer assumes there is no nvram. In the case of the dm9000 it will not wait but assign a random MAC address. It appears that if the dm9000 is configured into the kernel binary, it will be probed first and the correct sequence is broken. If it is a module (or even both), the way deferred probing works seems to serialize properly. So this hack is for demo purposes only and makes the dm9000 probing being delayed. A proper solution is to make sure the jz4780-efuse driver is probed earlier than the dm9000 driver (or mac address lookup). Signed-off-by: H. Nikolaus Schaller --- arch/mips/configs/ci20_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index 614dc18211bc..1d3d1d9b62bc 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -59,7 +59,7 @@ CONFIG_MTD_UBI_FASTMAP=y CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_BROADCOM is not set -CONFIG_DM9000=y +CONFIG_DM9000=m CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MARVELL is not set