From patchwork Mon Feb 17 09:35:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11385931 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 673871580 for ; Mon, 17 Feb 2020 09:36:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4843120732 for ; Mon, 17 Feb 2020 09:36:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="egQkMmyo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728945AbgBQJgI (ORCPT ); Mon, 17 Feb 2020 04:36:08 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:19842 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728911AbgBQJgH (ORCPT ); Mon, 17 Feb 2020 04:36:07 -0500 X-UUID: 53c0cfbd5d8a428db8be9821ede531bf-20200217 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=r7AqXWWI2XOKb8o72epYunSOyZikfu2WAV4cdgSvlQU=; b=egQkMmyoh7DXNkcULir9MSrkozqejp1Ig+OmZqS1QYBPCtHqw1dPfD7mpdbwk7eHTQYV1boUsu987vL78e33iFsAmp5rHckPYHgp4rn7vbFPrjOm9DXMZEufyufhv5Iv0UgfIP0ihsork6Nx3E6Kb3ImTuY/YkaX9u/llTaYD9Y=; X-UUID: 53c0cfbd5d8a428db8be9821ede531bf-20200217 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 774111493; Mon, 17 Feb 2020 17:36:01 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 17 Feb 2020 17:33:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 17 Feb 2020 17:35:36 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , Stanley Chu Subject: [PATCH v1 1/2] scsi: ufs: add required delay after gating reference clock Date: Mon, 17 Feb 2020 17:35:58 +0800 Message-ID: <20200217093559.16830-2-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200217093559.16830-1-stanley.chu@mediatek.com> References: <20200217093559.16830-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 6F93E073A79775700A46518EB217FC1397C16A2E0DDEF6E3FF63E042F98D71FF2000:8 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org In UFS version 3.0, a newly added attribute bRefClkGatingWaitTime defines the minimum time for which the reference clock is required by device during transition to LS-MODE or HIBERN8 state. Currently this time is detected and stored in hba->dev_info.clk_gating_wait_us but applied to vendor implementatios only. Make it applied to reference clock named as "ref_clk" in device tree in common path. Signed-off-by: Stanley Chu --- drivers/scsi/ufs/ufshcd.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 744b8254220c..7f60721f54d1 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -7417,8 +7417,10 @@ static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on, struct ufs_clk_info *clki; struct list_head *head = &hba->clk_list_head; unsigned long flags; + unsigned long wait_us; ktime_t start = ktime_get(); bool clk_state_changed = false; + bool ref_clk; if (list_empty(head)) goto out; @@ -7436,7 +7438,8 @@ static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on, list_for_each_entry(clki, head, list) { if (!IS_ERR_OR_NULL(clki->clk)) { - if (skip_ref_clk && !strcmp(clki->name, "ref_clk")) + ref_clk = !strcmp(clki->name, "ref_clk") ? true : false; + if (skip_ref_clk && ref_clk) continue; clk_state_changed = on ^ clki->enabled; @@ -7449,6 +7452,9 @@ static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on, } } else if (!on && clki->enabled) { clk_disable_unprepare(clki->clk); + wait_us = hba->dev_info.clk_gating_wait_us; + if (ref_clk && wait_us) + usleep_range(wait_us, wait_us + 10); } clki->enabled = on; dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, From patchwork Mon Feb 17 09:35:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 11385929 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 00E65109A for ; Mon, 17 Feb 2020 09:36:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CDDF92070B for ; Mon, 17 Feb 2020 09:36:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="TTf5/rFT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728947AbgBQJgI (ORCPT ); Mon, 17 Feb 2020 04:36:08 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:64865 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728933AbgBQJgH (ORCPT ); Mon, 17 Feb 2020 04:36:07 -0500 X-UUID: b7f94c8d211b44cdbd02e2c4d1097126-20200217 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=j1shUdhIMGXtvTw4SkKdC2CAhrzkCOkweoDSyilUUBo=; b=TTf5/rFTNAbBLj6+Uzfr7G0Gk3ywkP/lWKGHWyD4XZTWUwYRSUSFHv9bhSLZnpWYuogNvNnCzb5FuTo0/WgYe10wG7LW44WPWQGvsP3BY4hcywDWpH6/3SS1+AeFR3nw8h1WrmxV9sqnVZdX2JQs5/GQlXmBFo1zFQvYN0rqDiw=; X-UUID: b7f94c8d211b44cdbd02e2c4d1097126-20200217 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 424605006; Mon, 17 Feb 2020 17:36:01 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 17 Feb 2020 17:34:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 17 Feb 2020 17:35:36 +0800 From: Stanley Chu To: , , , , CC: , , , , , , , , , , , , Stanley Chu Subject: [PATCH v1 2/2] scsi: ufs: ufs-mediatek: add waiting time for reference clock Date: Mon, 17 Feb 2020 17:35:59 +0800 Message-ID: <20200217093559.16830-3-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200217093559.16830-1-stanley.chu@mediatek.com> References: <20200217093559.16830-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Some delays may be required either after gating or before ungating reference clock for device according to vendor requirements. Note that in UFS 3.0, the delay time after gating reference clock can be defined by attribute bRefClkGatingWaitTime. Use the formal value instead if it can be queried from device. Signed-off-by: Stanley Chu --- drivers/scsi/ufs/ufs-mediatek.c | 46 +++++++++++++++++++++++++++++++-- drivers/scsi/ufs/ufs-mediatek.h | 2 ++ 2 files changed, 46 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 9d05962feb15..de650822c9d9 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -100,6 +100,17 @@ static int ufs_mtk_bind_mphy(struct ufs_hba *hba) return err; } +static void ufs_mtk_udelay(unsigned long us) +{ + if (!us) + return; + + if (us < 10) + udelay(us); + else + usleep_range(us, us + 10); +} + static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); @@ -112,6 +123,7 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) if (on) { ufs_mtk_ref_clk_notify(on, res); + ufs_mtk_udelay(host->ref_clk_ungating_wait_us); ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL); } else { ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL); @@ -137,12 +149,29 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) out: host->ref_clk_enabled = on; - if (!on) + if (!on) { + ufs_mtk_udelay(host->ref_clk_gating_wait_us); ufs_mtk_ref_clk_notify(on, res); + } return 0; } +static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba, + u16 gating_us, u16 ungating_us) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + + if (hba->dev_info.clk_gating_wait_us) { + host->ref_clk_gating_wait_us = + hba->dev_info.clk_gating_wait_us; + } else { + host->ref_clk_gating_wait_us = gating_us; + } + + host->ref_clk_ungating_wait_us = ungating_us; +} + static u32 ufs_mtk_link_get_state(struct ufs_hba *hba) { u32 val; @@ -502,10 +531,23 @@ static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba) static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba) { struct ufs_dev_info *dev_info = &hba->dev_info; + u16 mid = dev_info->wmanufacturerid; - if (dev_info->wmanufacturerid == UFS_VENDOR_SAMSUNG) + if (mid == UFS_VENDOR_SAMSUNG) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6); + /* + * Decide waiting time before gating reference clock and + * after ungating reference clock according to vendors' + * requirements. + */ + if (mid == UFS_VENDOR_SAMSUNG) + ufs_mtk_setup_ref_clk_wait_us(hba, 1, 1); + else if (mid == UFS_VENDOR_SKHYNIX) + ufs_mtk_setup_ref_clk_wait_us(hba, 30, 30); + else if (mid == UFS_VENDOR_TOSHIBA) + ufs_mtk_setup_ref_clk_wait_us(hba, 100, 32); + return 0; } diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index 492414e5f481..4c787b99fe41 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -92,6 +92,8 @@ struct ufs_mtk_host { struct ufs_hba *hba; struct phy *mphy; bool ref_clk_enabled; + u16 ref_clk_ungating_wait_us; + u16 ref_clk_gating_wait_us; }; #endif /* !_UFS_MEDIATEK_H */