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Wed, 19 Feb 2020 09:59:44 +0000 From: peng.fan@nxp.com To: sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, abel.vesa@nxp.com, leonard.crestez@nxp.com Cc: kernel@pengutronix.de, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anson.huang@nxp.com, ping.bai@nxp.com, l.stach@pengutronix.de, Peng Fan Subject: [PATCH V3 1/4] clk: imx: composite-8m: add imx8m_clk_hw_composite_core Date: Wed, 19 Feb 2020 17:53:35 +0800 Message-Id: <1582106022-20926-2-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> References: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> X-ClientProxiedBy: HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) MIME-Version: 1.0 Received: from localhost.localdomain (119.31.174.66) by HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2750.8 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: oCdmfLr0Aief1Inn9DCOPo+7qIe7aoaUGVM6hdAzjlviQpOk59oVxmcbgm/7Q6hJauA9wBzdSdy4izaU90gI+kYjBne2XH3nEikaxbFYi1lyzyvQfo8ORY04POzd3YlHF06YQBJyelZufFU56l50ljHb+zj8Rc7452NrZWyu/a7nCYrkzkCKRdsKZdkzxv1pJzcvRHo3YOh6grjV1Tbf+cZL9csXL9AHN6YaBgKiyRhf0i/1N3F3JR0R73qNax/jLbRzRpe6ZDHkT9p9LYMs0lyDwQpeJUVr+m5opJehPEeZ8pJMBI8mUW4FcUtBc/1chRHtI+fZiH3oWBMdoP4Biez3cebgIG3K7PBwa9kvb4vvVpPaE7EArqgODvdS7Vg/LmnRqO81hB9S+VJ+/9Ssva5wdMfFVhPHI07x6wO69T/PPLwVsDFGdyLCE27+Oen6oodfU4iypCsHn3Oa2VLx67KDPegYZfG0iuronI0D4FcxkG/n27GruN8rjSwNgwnZ30KCBVx3XxfgbdUQwWAfjwYQqYvLWyWKKaWnNZqAR94= X-MS-Exchange-AntiSpam-MessageData: nkOpPJIvAfYqHMOa4Sur1x5wHhkw8+bk1B1hvQCTRK+NOMwd+UJkhWVUAO1uvkhTewVaRoEGJEX5ullLfDp6Pn7DUBkplCeA7VdDAPpKWqcSz8MtTRMCj6jQ2hNPA0pwnqx7lvvrvO9aHphU8/oYSw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: eb7bbb8d-db4a-4070-c23a-08d7b52271e0 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Feb 2020 09:59:44.2164 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: tuR5FiYSqmbIDK9/QtPWm3mmDOroa4zUOlfqU4FtPmtvRXQP8dYV5dd8zzEJ8JgEP/fVTOK4CFUzD304TKcwcg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6514 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan There are several clock slices, current composite code only support bus/ip clock slices, it could not support core slice. So introduce a new API imx8m_clk_hw_composite_core to support core slice. To core slice, post divider with 3 bits width and no pre divider. Other fields are same as bus/ip slices. Add a flag IMX_COMPOSITE_CORE for the usecase. Reviewed-by: Abel Vesa Signed-off-by: Peng Fan --- drivers/clk/imx/clk-composite-8m.c | 18 ++++++++++++++---- drivers/clk/imx/clk.h | 13 +++++++++++-- 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index e0f25983e80f..4174506e8bdd 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -15,6 +15,7 @@ #define PCG_PREDIV_MAX 8 #define PCG_DIV_SHIFT 0 +#define PCG_CORE_DIV_WIDTH 3 #define PCG_DIV_WIDTH 6 #define PCG_DIV_MAX 64 @@ -126,6 +127,7 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = { struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, + u32 composite_flags, unsigned long flags) { struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; @@ -133,6 +135,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, struct clk_divider *div = NULL; struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; + const struct clk_ops *divider_ops; mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) @@ -149,8 +152,16 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, div_hw = &div->hw; div->reg = reg; - div->shift = PCG_PREDIV_SHIFT; - div->width = PCG_PREDIV_WIDTH; + if (composite_flags & IMX_COMPOSITE_CORE) { + div->shift = PCG_DIV_SHIFT; + div->width = PCG_CORE_DIV_WIDTH; + divider_ops = &clk_divider_ops; + } else { + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + divider_ops = &imx8m_clk_composite_divider_ops; + } + div->lock = &imx_ccm_lock; div->flags = CLK_DIVIDER_ROUND_CLOSEST; @@ -164,8 +175,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &clk_mux_ops, div_hw, - &imx8m_clk_composite_divider_ops, - gate_hw, &clk_gate_ops, flags); + divider_ops, gate_hw, &clk_gate_ops, flags); if (IS_ERR(hw)) goto fail; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index b05213b91dcf..f074dd8ec42e 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); +#define IMX_COMPOSITE_CORE BIT(0) + struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, + u32 composite_flags, unsigned long flags); +#define imx8m_clk_hw_composite_core(name, parent_names, reg) \ + imx8m_clk_hw_composite_flags(name, parent_names, \ + ARRAY_SIZE(parent_names), reg, \ + IMX_COMPOSITE_CORE, \ + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \ flags) \ to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \ - num_parents, reg, flags)) + num_parents, reg, 0, flags)) #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \ imx8m_clk_hw_composite_flags(name, parent_names, \ - ARRAY_SIZE(parent_names), reg, \ + ARRAY_SIZE(parent_names), reg, 0, \ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) #define __imx8m_clk_composite(name, parent_names, reg, flags) \ From patchwork Wed Feb 19 09:53:37 2020 Content-Type: text/plain; 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Wed, 19 Feb 2020 09:59:53 +0000 From: peng.fan@nxp.com To: sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, abel.vesa@nxp.com, leonard.crestez@nxp.com Cc: kernel@pengutronix.de, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anson.huang@nxp.com, ping.bai@nxp.com, l.stach@pengutronix.de, Peng Fan Subject: [PATCH v3 2/4] clk: imx: imx8mm: fix a53 cpu clock Date: Wed, 19 Feb 2020 17:53:37 +0800 Message-Id: <1582106022-20926-4-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> References: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> X-ClientProxiedBy: HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) MIME-Version: 1.0 Received: from localhost.localdomain (119.31.174.66) by HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2750.8 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: jVY5W2jvxC4zbnN+w6H96bRWPgpDsJcPuZB2uuMW2WrkKCuuubaojfN5cMUThkINkNw4ZuFiblwSnogwQpZ2D8gALzLs+utn3k+Q97zKQtRpSZN+AHAUSOKTrcfKIAjIQi/RKcz8TCCKPmrg16uCnGik580c8TpWivwz2pnrDBSISM6DWv4q0LVdHxx+ClIO975DAwwV4twE7q05zqThJQGUQOWeuTWKv/9LBi/Bh4ISU+jrm7yiw8IHE8zifaVZ87BA5TVfEWMsx5xEWwostcRu3lKOTClO+PkUUc3rQXjYvycZok7cuE890ktpHpPsOHMKIvB6J67EhZFB1+MXSTMhh0Ii+AtlGBq8377xOoleDnoeIyu47m+sNq3KENEyM/EGDZGmN+oFCossRq+QEvZiX/RIeAYiBhGy8ph+o26zPloM60K9St4TgYsCWX1vGxaKofc6zc2nxLIMn+FdQJzYWCcyPgPxl48LeHuNATAt1CfxYVHJ5P0AGDOdHaPjtbvOsYqXoHmEdsHoIgdrhda/E/YJRDmQ8gBpdauh+zuKlas6rV0R0alcdlgX1SLI X-MS-Exchange-AntiSpam-MessageData: KRupF1gGLG8OuehhS0SluxDO9iNNltN9GVCGe0AFj5fSTfFJzD/k5H5uIDttW5civ4UPvKGlOywuzUQeXJ1S6DZh3YKAY8gbUGhbLWM5OVZt34mslSiVTHYKnzyKiaUSchFXTwZAl4zElHPrAN0AKg== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 00c3f69e-8468-4de5-158c-08d7b522777c X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Feb 2020 09:59:53.6459 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XWX7tlkltt6sk4X2Tq/ohvswtJhmx92vfy6m7t6ERN29hzZb21PrzAxMmnI0BsMb0nfvDwjKN/OAbWzST59jYg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6514 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clock Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Reviewed-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mm.c | 16 ++++++++++++---- include/dt-bindings/clock/imx8mm-clock.h | 4 +++- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 2f2c240a86e2..f851cd447e7c 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -41,6 +41,8 @@ static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; +static const char * const imx8mm_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; + static const char *imx8mm_m4_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "sys_pll1_266m", "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; @@ -439,6 +441,9 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws[IMX8MM_CLK_GPU2D_CG] = hws[IMX8MM_CLK_GPU2D_CORE]; hws[IMX8MM_CLK_GPU2D_DIV] = hws[IMX8MM_CLK_GPU2D_CORE]; + /* CORE SEL */ + hws[IMX8MM_CLK_A53_CORE] = imx_clk_hw_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels), CLK_IS_CRITICAL); + /* BUS */ hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800); hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mm_enet_axi_sels, base + 0x8880); @@ -605,11 +610,14 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws[IMX8MM_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4); hws[IMX8MM_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels), CLK_IS_CRITICAL); - hws[IMX8MM_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div", - hws[IMX8MM_CLK_A53_DIV]->clk, - hws[IMX8MM_CLK_A53_SRC]->clk, + clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC], hws[IMX8MM_SYS_PLL1_800M]); + clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE], hws[IMX8MM_ARM_PLL_OUT]); + + hws[IMX8MM_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", + hws[IMX8MM_CLK_A53_CORE]->clk, + hws[IMX8MM_CLK_A53_CORE]->clk, hws[IMX8MM_ARM_PLL_OUT]->clk, - hws[IMX8MM_SYS_PLL1_800M]->clk); + hws[IMX8MM_CLK_A53_DIV]->clk); imx_check_clk_hws(hws, IMX8MM_CLK_END); diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index dbfee6579d6c..e63a5530aed7 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -272,6 +272,8 @@ #define IMX8MM_CLK_CLKO2 250 -#define IMX8MM_CLK_END 251 +#define IMX8MM_CLK_A53_CORE 251 + +#define IMX8MM_CLK_END 252 #endif From patchwork Wed Feb 19 09:53:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 11390863 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E420D92A for ; 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Received: from AM0PR04MB4481.eurprd04.prod.outlook.com (52.135.147.15) by AM0PR04MB6514.eurprd04.prod.outlook.com (20.179.254.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.17; Wed, 19 Feb 2020 10:00:03 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::91e2:17:b3f4:d422]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::91e2:17:b3f4:d422%3]) with mapi id 15.20.2729.032; Wed, 19 Feb 2020 10:00:03 +0000 From: peng.fan@nxp.com To: sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, abel.vesa@nxp.com, leonard.crestez@nxp.com Cc: kernel@pengutronix.de, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anson.huang@nxp.com, ping.bai@nxp.com, l.stach@pengutronix.de, Peng Fan Subject: [PATCH V3 3/4] clk: imx: imx8mm: use imx8m_clk_hw_composite_core Date: Wed, 19 Feb 2020 17:53:39 +0800 Message-Id: <1582106022-20926-6-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> References: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> X-ClientProxiedBy: HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) MIME-Version: 1.0 Received: from localhost.localdomain (119.31.174.66) by HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2750.8 via Frontend Transport; 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Reviewed-by: Abel Vesa Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mm.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 2ed93fc25087..197ba2cdab7d 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -414,20 +414,13 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) /* Core Slice */ hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)); - hws[IMX8MM_CLK_M4_SRC] = imx_clk_hw_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mm_m4_sels, ARRAY_SIZE(imx8mm_m4_sels)); - hws[IMX8MM_CLK_VPU_SRC] = imx_clk_hw_mux2("vpu_src", base + 0x8100, 24, 3, imx8mm_vpu_sels, ARRAY_SIZE(imx8mm_vpu_sels)); - hws[IMX8MM_CLK_GPU3D_SRC] = imx_clk_hw_mux2("gpu3d_src", base + 0x8180, 24, 3, imx8mm_gpu3d_sels, ARRAY_SIZE(imx8mm_gpu3d_sels)); - hws[IMX8MM_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src", base + 0x8200, 24, 3, imx8mm_gpu2d_sels, ARRAY_SIZE(imx8mm_gpu2d_sels)); hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28); - hws[IMX8MM_CLK_M4_CG] = imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); - hws[IMX8MM_CLK_VPU_CG] = imx_clk_hw_gate3("vpu_cg", "vpu_src", base + 0x8100, 28); - hws[IMX8MM_CLK_GPU3D_CG] = imx_clk_hw_gate3("gpu3d_cg", "gpu3d_src", base + 0x8180, 28); - hws[IMX8MM_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg", "gpu2d_src", base + 0x8200, 28); hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3); - hws[IMX8MM_CLK_M4_DIV] = imx_clk_hw_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); - hws[IMX8MM_CLK_VPU_DIV] = imx_clk_hw_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3); - hws[IMX8MM_CLK_GPU3D_DIV] = imx_clk_hw_divider2("gpu3d_div", "gpu3d_cg", base + 0x8180, 0, 3); - hws[IMX8MM_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div", "gpu2d_cg", base + 0x8200, 0, 3); + + hws[IMX8MM_CLK_M4_DIV] = imx8m_clk_hw_composite_core("arm_m4_div", imx8mm_m4_sels, base + 0x8080); + hws[IMX8MM_CLK_VPU_DIV] = imx8m_clk_hw_composite_core("vpu_div", imx8mm_vpu_sels, base + 0x8100); + hws[IMX8MM_CLK_GPU3D_DIV] = imx8m_clk_hw_composite_core("gpu3d_div", imx8mm_gpu3d_sels, base + 0x8180); + hws[IMX8MM_CLK_GPU2D_DIV] = imx8m_clk_hw_composite_core("gpu2d_div", imx8mm_gpu2d_sels, base + 0x8200); /* BUS */ hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800); From patchwork Wed Feb 19 09:53:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 11390869 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD6AE109A for ; Wed, 19 Feb 2020 10:00:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B634224687 for ; Wed, 19 Feb 2020 10:00:25 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Received: from AM0PR04MB4481.eurprd04.prod.outlook.com (52.135.147.15) by AM0PR04MB6770.eurprd04.prod.outlook.com (52.132.214.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2729.31; Wed, 19 Feb 2020 10:00:17 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::91e2:17:b3f4:d422]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::91e2:17:b3f4:d422%3]) with mapi id 15.20.2729.032; Wed, 19 Feb 2020 10:00:17 +0000 From: peng.fan@nxp.com To: sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, abel.vesa@nxp.com, leonard.crestez@nxp.com Cc: kernel@pengutronix.de, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anson.huang@nxp.com, ping.bai@nxp.com, l.stach@pengutronix.de, Peng Fan Subject: [PATCH v3 4/4] clk: imx: imx8mp: fix a53 cpu clock Date: Wed, 19 Feb 2020 17:53:42 +0800 Message-Id: <1582106022-20926-9-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> References: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> X-ClientProxiedBy: HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) MIME-Version: 1.0 Received: from localhost.localdomain (119.31.174.66) by HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2750.8 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: 5WnmOIZbeQ+hG3haYvRxAlTZZKJHYJVP3i3AFEom+yBzBkoA7gGztxopA/apTQjJaAkg001ZaecYnrs3kiBERYzgyhuxzSggT90pHCXXbQa4DwZY3Jsdsri7b/KzTFDidEIamf9b2LRHNolWr5xEsasPoS40RnLjLRAW0msPsoK4yhRbq+BQsFj6U4GKC9KlkF1qCVzVCJjILYcNFgN/WVdcnLJgiN+/b4MKqo2Aed+JrfPRY3VPiKcMihBSLyCk3hOrCDn6HEvLzYcFUcR7zuz3A3ojJQfswA8diNgAo66ar+Kk2lvyucnnkNCOA58ry2vF+RSpwo4Sixo5dZO8YSt6gQUbWrhBUzkRM7T4/Ig6IK1BN5CEuEk2cAlbGZcOrGxNbDgRLmgAectcDVMftD1KGxYS0scuipawgk9qkfXJ6FYiBYAxZrDnygNO8Kq7cUlfGKeWwxT7H+sVxqW9+abpNPtP+1eEsm/0v8jBg0TF9mXq8imtLvSaCTg+gWKRUBt6fkesz58M6wV9FeOMQdUVrOReiD8Ddy+VkTFKxugAbfovdNSOb84JySJXFmCr X-MS-Exchange-AntiSpam-MessageData: BYrnBWBoAo169dcoJH7e0i8szaYkKrlxk+MiQBpo7H9PY5AeC4HoVPUwyHuUa/1RpnTDpv0xTQIjpctB5cfA2E+G1HWwlX0MGTeyk8slpTkNkE4xhqgSAYJiCJPybBI9mfiEIraEbiRYfpAUWI8fKA== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f308db0a-d74f-490b-3b62-08d7b52285ea X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Feb 2020 10:00:17.8629 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: EP9Nntow6ExhkMXPb4tWSGU38SwmbOFPd2dOwgJ3imgEj6x5aNcKPC1naxQbqLCPgqqx+3x6MwD2G9YtQ9Ra6g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6770 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clk Reviewed-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mp.c | 16 ++++++++++++---- include/dt-bindings/clock/imx8mp-clock.h | 3 ++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index a16af4fce044..d67ee36b84de 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -34,6 +34,8 @@ static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; +static const char * const imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; + static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; @@ -554,6 +556,9 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_hw_divider2("hsio_axi_div", "hsio_axi_cg", ccm_base + 0x8380, 0, 3); hws[IMX8MP_CLK_MEDIA_ISP_DIV] = imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0, 3); + /* CORE SEL */ + hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2_flags("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels), CLK_IS_CRITICAL); + hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800); hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880); hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900); @@ -724,11 +729,14 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0); - hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div", - hws[IMX8MP_CLK_A53_DIV]->clk, - hws[IMX8MP_CLK_A53_SRC]->clk, + clk_hw_set_parent(hws[IMX8MP_CLK_A53_SRC], hws[IMX8MP_SYS_PLL1_800M]); + clk_hw_set_parent(hws[IMX8MP_CLK_A53_CORE], hws[IMX8MP_ARM_PLL_OUT]); + + hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", + hws[IMX8MP_CLK_A53_CORE]->clk, + hws[IMX8MP_CLK_A53_CORE]->clk, hws[IMX8MP_ARM_PLL_OUT]->clk, - hws[IMX8MP_SYS_PLL1_800M]->clk); + hws[IMX8MP_CLK_A53_DIV]->clk); imx_check_clk_hws(hws, IMX8MP_CLK_END); diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 2fab63186bca..c92d1f4117eb 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -294,7 +294,8 @@ #define IMX8MP_CLK_DRAM_ALT_ROOT 285 #define IMX8MP_CLK_DRAM_CORE 286 #define IMX8MP_CLK_ARM 287 +#define IMX8MP_CLK_A53_CORE 288 -#define IMX8MP_CLK_END 288 +#define IMX8MP_CLK_END 289 #endif