From patchwork Thu Feb 20 03:22:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393155 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 844C4930 for ; Thu, 20 Feb 2020 03:24:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BDB5521D56 for ; Thu, 20 Feb 2020 03:24:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="iU0LwKGW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BDB5521D56 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRo-0006I7-Ev for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:24:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41171) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR3-0004af-QN for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR2-0008Hn-Gr for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:33 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:38355) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR1-0008Di-NJ; Wed, 19 Feb 2020 22:23:32 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg02RwLz9sSK; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169004; bh=XfjqatoySBeh8fCxko51poY2tUcpJr05c4AB3WcSL8E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iU0LwKGWANHBJGlyk06SBgvsUwCEsjLeXu28ndqODzs/mKpj0XMjFXQvxZYgSPW6L zLh4lmlU5deFAwqSeOXFDbrbcxaCoq/I+igRwl2Xfu0IVAkXc3Tf2k0NWqRYCM+UT7 ptPmF9k8iDHmlQY6/zo1WMspom7cucbNE37M9Yak= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 01/18] ppc: Remove stub support for 32-bit hypervisor mode Date: Thu, 20 Feb 2020 14:22:59 +1100 Message-Id: <20200220032317.96884-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Fabiano Rosas , Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" a4f30719a8cd, way back in 2007 noted that "PowerPC hypervisor mode is not fundamentally available only for PowerPC 64" and added a 32-bit version of the MSR[HV] bit. But nothing was ever really done with that; there is no meaningful support for 32-bit hypervisor mode 13 years later. Let's stop pretending and just remove the stubs. Signed-off-by: David Gibson Reviewed-by: Fabiano Rosas --- target/ppc/cpu.h | 21 +++++++-------------- target/ppc/translate_init.inc.c | 6 +++--- 2 files changed, 10 insertions(+), 17 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b283042515..8077fdb068 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -24,8 +24,6 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" -/* #define PPC_EMULATE_32BITS_HYPV */ - #define TCG_GUEST_DEFAULT_MO 0 #define TARGET_PAGE_BITS_64K 16 @@ -300,13 +298,12 @@ typedef struct ppc_v3_pate_t { #define MSR_SF 63 /* Sixty-four-bit mode hflags */ #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ -#define MSR_SHV 60 /* hypervisor state hflags */ +#define MSR_HV 60 /* hypervisor state hflags */ #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */ #define MSR_TS1 33 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */ #define MSR_CM 31 /* Computation mode for BookE hflags */ #define MSR_ICM 30 /* Interrupt computation mode for BookE */ -#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ #define MSR_GS 28 /* guest state for BookE */ #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ #define MSR_VR 25 /* altivec available x hflags */ @@ -401,10 +398,13 @@ typedef struct ppc_v3_pate_t { #define msr_sf ((env->msr >> MSR_SF) & 1) #define msr_isf ((env->msr >> MSR_ISF) & 1) -#define msr_shv ((env->msr >> MSR_SHV) & 1) +#if defined(TARGET_PPC64) +#define msr_hv ((env->msr >> MSR_HV) & 1) +#else +#define msr_hv (0) +#endif #define msr_cm ((env->msr >> MSR_CM) & 1) #define msr_icm ((env->msr >> MSR_ICM) & 1) -#define msr_thv ((env->msr >> MSR_THV) & 1) #define msr_gs ((env->msr >> MSR_GS) & 1) #define msr_ucle ((env->msr >> MSR_UCLE) & 1) #define msr_vr ((env->msr >> MSR_VR) & 1) @@ -449,16 +449,9 @@ typedef struct ppc_v3_pate_t { /* Hypervisor bit is more specific */ #if defined(TARGET_PPC64) -#define MSR_HVB (1ULL << MSR_SHV) -#define msr_hv msr_shv -#else -#if defined(PPC_EMULATE_32BITS_HYPV) -#define MSR_HVB (1ULL << MSR_THV) -#define msr_hv msr_thv +#define MSR_HVB (1ULL << MSR_HV) #else #define MSR_HVB (0ULL) -#define msr_hv (0) -#endif #endif /* DSISR */ diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 53995f62ea..a0d0eaabf2 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8804,7 +8804,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206; pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_SHV) | + (1ull << MSR_HV) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | @@ -9017,7 +9017,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_SHV) | + (1ull << MSR_HV) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | @@ -9228,7 +9228,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_SHV) | + (1ull << MSR_HV) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | From patchwork Thu Feb 20 03:23:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393171 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 282C0930 for ; Thu, 20 Feb 2020 03:27:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F29F021D56 for ; Thu, 20 Feb 2020 03:27:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="odBCp9Mw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F29F021D56 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cVE-0005Az-5s for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:27:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41179) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR3-0004ak-U3 for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR2-0008Hz-K1 for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:33 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:45613 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR1-0008Dg-Lt; Wed, 19 Feb 2020 22:23:32 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg01cdCz9sSD; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169004; bh=3yZHI6i+ESlOY6Bm+OB1zHwskVZfGDMZIUebGR7XvSM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=odBCp9MwioUg+1u11VhsKs9Qms7+bbIKDUF6m5ylZJ96pRdvZcotvxD7GdV/JmKLG spHUaPuBV9zjDMF/XolTUeRpN0dui14Hn84RFYP2P/mKNPjGzl2kUc0GpEqaq4AdRN DgBdpVne2pwO9d6N9WrlOrmpzGTt2jPCBELfGTmk= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 02/18] ppc: Remove stub of PPC970 HID4 implementation Date: Thu, 20 Feb 2020 14:23:00 +1100 Message-Id: <20200220032317.96884-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor capability. However, it can be (and often was) strapped into "Apple mode", where the hypervisor capabilities were disabled (essentially putting it always in hypervisor mode). That's actually the only mode of the 970 we support in qemu, and we're unlikely to change that any time soon. However, we do have a partial implementation of the 970's HID4 register which affects things only relevant for hypervisor mode. That stub is also really ugly, since it attempts to duplicate the effects of HID4 by re-encoding it into the LPCR register used in newer CPUs, but in a really confusing way. Just get rid of it. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz --- target/ppc/mmu-hash64.c | 29 +---------------------------- target/ppc/translate_init.inc.c | 20 ++++++++------------ 2 files changed, 9 insertions(+), 40 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index da8966ccf5..3e0be4d55f 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1091,33 +1091,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) /* Filter out bits */ switch (env->mmu_model) { - case POWERPC_MMU_64B: /* 970 */ - if (val & 0x40) { - lpcr |= LPCR_LPES0; - } - if (val & 0x8000000000000000ull) { - lpcr |= LPCR_LPES1; - } - if (val & 0x20) { - lpcr |= (0x4ull << LPCR_RMLS_SHIFT); - } - if (val & 0x4000000000000000ull) { - lpcr |= (0x2ull << LPCR_RMLS_SHIFT); - } - if (val & 0x2000000000000000ull) { - lpcr |= (0x1ull << LPCR_RMLS_SHIFT); - } - env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26; - - /* - * XXX We could also write LPID from HID4 here - * but since we don't tag any translation on it - * it doesn't actually matter - * - * XXX For proper emulation of 970 we also need - * to dig HRMOR out of HID5 - */ - break; case POWERPC_MMU_2_03: /* P5p */ lpcr = val & (LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | @@ -1154,7 +1127,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) } break; default: - ; + g_assert_not_reached(); } env->spr[SPR_LPCR] = lpcr; ppc_hash64_update_rmls(cpu); diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index a0d0eaabf2..ab79975fec 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -7895,25 +7895,21 @@ static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) { gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); } - -static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn) -{ -#if defined(TARGET_PPC64) - spr_write_generic(ctx, sprn, gprn); - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); -#endif -} - #endif /* !defined(CONFIG_USER_ONLY) */ static void gen_spr_970_lpar(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) - /* Logical partitionning */ - /* PPC970: HID4 is effectively the LPCR */ + /* + * PPC970: HID4 covers things later controlled by the LPCR and + * RMOR in later CPUs, but with a different encoding. We only + * support the 970 in "Apple mode" which has all hypervisor + * facilities disabled by strapping, so we can basically just + * ignore it + */ spr_register(env, SPR_970_HID4, "HID4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_970_hid4, + &spr_read_generic, &spr_write_generic, 0x00000000); #endif } From patchwork Thu Feb 20 03:23:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393191 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5FE99109A for ; Thu, 20 Feb 2020 03:33:19 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 36F35208C4 for ; Thu, 20 Feb 2020 03:33:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="NQqanpmE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 36F35208C4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35403 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4caU-0005SS-Cw for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:33:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41400) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRA-0004hA-02 for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR6-0008Lo-Ml for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:39 -0500 Received: from ozlabs.org ([203.11.71.1]:49191) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR6-0008IB-AM; Wed, 19 Feb 2020 22:23:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg03ztqz9sSQ; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169004; bh=GpG7JIVsiHpMpesoVJsSFbR7MFKVdTtNyC10o80HfXM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NQqanpmEFWysOwRm2YLPYflYVs/ZQMaqreoK7+H1+hmM5p79DCEHWlw3k9ViENuKu ECTxqLLb6zrrcSO7jewHBZqBgoeLzbAXxi18A6XII005HzVJooG/NAzG4U0iyQFF5I tfQjPZW1jELUdPfEGzpF+xiBKfijNWMwjMy3mnks= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 03/18] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU Date: Thu, 20 Feb 2020 14:23:01 +1100 Message-Id: <20200220032317.96884-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" On ppc we have the concept of virtual hypervisor ("vhyp") mode, where we only model the non-hypervisor-privileged parts of the cpu. Essentially we model the hypervisor's behaviour from the point of view of a guest OS, but we don't model the hypervisor's execution. In particular, in this mode, qemu's notion of target physical address is a guest physical address from the vcpu's point of view. So accesses in guest real mode don't require translation. If we were modelling the hypervisor mode, we'd need to translate the guest physical address into a host physical address. Currently, we handle this sloppily: we rely on setting up the virtual LPCR and RMOR registers so that GPAs are simply HPAs plus an offset, which we set to zero. This is already conceptually dubious, since the LPCR and RMOR registers don't exist in the non-hypervisor portion of the CPU. It gets worse with POWER9, where RMOR and LPCR[VPM0] no longer exist at all. Clean this up by explicitly handling the vhyp case. While we're there, remove some unnecessary nesting of if statements that made the logic to select the correct real mode behaviour a bit less clear than it could be. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/mmu-hash64.c | 60 ++++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 3e0be4d55f..392f90e0ae 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -789,27 +789,30 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, */ raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; - /* In HV mode, add HRMOR if top EA bit is clear */ - if (msr_hv || !env->has_hv_mode) { + if (cpu->vhyp) { + /* + * In virtual hypervisor mode, there's nothing to do: + * EA == GPA == qemu guest address + */ + } else if (msr_hv || !env->has_hv_mode) { + /* In HV mode, add HRMOR if top EA bit is clear */ if (!(eaddr >> 63)) { raddr |= env->spr[SPR_HRMOR]; } - } else { - /* Otherwise, check VPM for RMA vs VRMA */ - if (env->spr[SPR_LPCR] & LPCR_VPM0) { - slb = &env->vrma_slb; - if (slb->sps) { - goto skip_slb_search; - } - /* Not much else to do here */ + } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + /* Emulated VRMA mode */ + slb = &env->vrma_slb; + if (!slb->sps) { + /* Invalid VRMA setup, machine check */ cs->exception_index = POWERPC_EXCP_MCHECK; env->error_code = 0; return 1; - } else if (raddr < env->rmls) { - /* RMA. Check bounds in RMLS */ - raddr |= env->spr[SPR_RMOR]; - } else { - /* The access failed, generate the approriate interrupt */ + } + + goto skip_slb_search; + } else { + /* Emulated old-style RMO mode, bounds check against RMLS */ + if (raddr >= env->rmls) { if (rwx == 2) { ppc_hash64_set_isi(cs, SRR1_PROTFAULT); } else { @@ -821,6 +824,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, } return 1; } + + raddr |= env->spr[SPR_RMOR]; } tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, @@ -953,22 +958,27 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) /* In real mode the top 4 effective address bits are ignored */ raddr = addr & 0x0FFFFFFFFFFFFFFFULL; - /* In HV mode, add HRMOR if top EA bit is clear */ - if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { + if (cpu->vhyp) { + /* + * In virtual hypervisor mode, there's nothing to do: + * EA == GPA == qemu guest address + */ + return raddr; + } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { + /* In HV mode, add HRMOR if top EA bit is clear */ return raddr | env->spr[SPR_HRMOR]; - } - - /* Otherwise, check VPM for RMA vs VRMA */ - if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + /* Emulated VRMA mode */ slb = &env->vrma_slb; if (!slb->sps) { return -1; } - } else if (raddr < env->rmls) { - /* RMA. Check bounds in RMLS */ - return raddr | env->spr[SPR_RMOR]; } else { - return -1; + /* Emulated old-style RMO mode, bounds check against RMLS */ + if (raddr >= env->rmls) { + return -1; + } + return raddr | env->spr[SPR_RMOR]; } } else { slb = slb_lookup(cpu, addr); From patchwork Thu Feb 20 03:23:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393157 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B53DE14BC for ; Thu, 20 Feb 2020 03:24:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8C0FB21D56 for ; Thu, 20 Feb 2020 03:24:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="i/p0jqN/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8C0FB21D56 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRr-0006RK-KR for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:24:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41253) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR6-0004bK-Sf for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR5-0008Jw-H5 for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:36 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:53671 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR5-0008I9-6Y; Wed, 19 Feb 2020 22:23:35 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg03Mbxz9sSJ; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169004; bh=4XiokVgfdNhjja2TStYKYuF9QU8EUX+Y1oGsbrdG1jU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i/p0jqN/L01wQ78NvsC3HBoxRAzGgxgPmiW8EjmP9zPDCxJWH5Sne6zfndwuENpXS LiOyURvHHLsDjb1lD7npLgtvq4XT7SyAs92tLgIUrLhLLIjgUKBdOMlg0jR0v2pYox Dl+4asVLhJtSDZHQcDVTZt6zwzrJvnzV5xYdi7EM= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 04/18] target/ppc: Introduce ppc_hash64_use_vrma() helper Date: Thu, 20 Feb 2020 14:23:02 +1100 Message-Id: <20200220032317.96884-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" When running guests under a hypervisor, the hypervisor obviously needs to be protected from guest accesses even if those are in what the guest considers real mode (translation off). The POWER hardware provides two ways of doing that: The old way has guest real mode accesses simply offset and bounds checked into host addresses. It works, but requires that a significant chunk of the guest's memory - the RMA - be physically contiguous in the host, which is pretty inconvenient. The new way, known as VRMA, has guest real mode accesses translated in roughly the normal way but with some special parameters. In POWER7 and POWER8 the LPCR[VPM0] bit selected between the two modes, but in POWER9 only VRMA mode is supported and LPCR[VPM0] no longer exists. We handle that difference in behaviour in ppc_hash64_set_isi().. but not in other places that we blindly check LPCR[VPM0]. Correct those instances with a new helper to tell if we should be in VRMA mode. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/mmu-hash64.c | 43 ++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 392f90e0ae..0f9c0149e8 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -668,6 +668,21 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, return 0; } +static bool ppc_hash64_use_vrma(CPUPPCState *env) +{ + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* + * ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR + * register no longer exist + */ + return true; + + default: + return !!(env->spr[SPR_LPCR] & LPCR_VPM0); + } +} + static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) { CPUPPCState *env = &POWERPC_CPU(cs)->env; @@ -676,15 +691,7 @@ static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) if (msr_ir) { vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - switch (env->mmu_model) { - case POWERPC_MMU_3_00: - /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ - vpm = true; - break; - default: - vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); - break; - } + vpm = ppc_hash64_use_vrma(env); } if (vpm && !msr_hv) { cs->exception_index = POWERPC_EXCP_HISI; @@ -702,15 +709,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr) if (msr_dr) { vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - switch (env->mmu_model) { - case POWERPC_MMU_3_00: - /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ - vpm = true; - break; - default: - vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); - break; - } + vpm = ppc_hash64_use_vrma(env); } if (vpm && !msr_hv) { cs->exception_index = POWERPC_EXCP_HDSI; @@ -799,7 +798,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, if (!(eaddr >> 63)) { raddr |= env->spr[SPR_HRMOR]; } - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ slb = &env->vrma_slb; if (!slb->sps) { @@ -967,7 +966,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { /* In HV mode, add HRMOR if top EA bit is clear */ return raddr | env->spr[SPR_HRMOR]; - } else if (env->spr[SPR_LPCR] & LPCR_VPM0) { + } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ slb = &env->vrma_slb; if (!slb->sps) { @@ -1056,8 +1055,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) slb->sps = NULL; /* Is VRMA enabled ? */ - lpcr = env->spr[SPR_LPCR]; - if (!(lpcr & LPCR_VPM0)) { + if (ppc_hash64_use_vrma(env)) { return; } @@ -1065,6 +1063,7 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) * Make one up. Mostly ignore the ESID which will not be needed * for translation */ + lpcr = env->spr[SPR_LPCR]; vsid = SLB_VSID_VRMA; vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); From patchwork Thu Feb 20 03:23:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393163 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D105D930 for ; Thu, 20 Feb 2020 03:26:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A567321D56 for ; Thu, 20 Feb 2020 03:26:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="PAyKlyz3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A567321D56 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35282 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cTq-0002Kf-Q3 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:26:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41282) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR7-0004bY-Ig for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR6-0008L9-Ab for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:37 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:55797 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR5-0008IC-Ur; Wed, 19 Feb 2020 22:23:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg05Dj2z9sST; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169004; bh=0lvTfXqoiUNxVPWrgRrJhN5mbXpUL6Tid8JMNpe1p8U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PAyKlyz3rNomo5ok2C5C61dHmDZoAcp+O7+iOkfDzdYVYmoJkX/WIRriPTo1x9NLE w+pX9LBgD4dc3ZnNV59FA0i4VHo6tn7q6F+1GF84R5/2s3QEuUq5ZzciVgzNGmVAss XTc0xSiINEGzCcyT7g+fwMReX2wGmNmIelwV6JtU= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 05/18] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 Date: Thu, 20 Feb 2020 14:23:03 +1100 Message-Id: <20200220032317.96884-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" For the "pseries" machine, we use "virtual hypervisor" mode where we only model the CPU in non-hypervisor privileged mode. This means that we need guest physical addresses within the modelled cpu to be treated as absolute physical addresses. We used to do that by clearing LPCR[VPM0] and setting LPCR[RMLS] to a high limit so that the old offset based translation for guest mode applied, which does what we need. However, POWER9 has removed support for that translation mode, which meant we had some ugly hacks to keep it working. We now explicitly handle this sort of translation for virtual hypervisor mode, so the hacks aren't necessary. We don't need to set VPM0 and RMLS from the machine type code - they're now ignored in vhyp mode. On the cpu side we don't need to allow LPCR[RMLS] to be set on POWER9 in vhyp mode - that was only there to allow the hack on the machine side. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- hw/ppc/spapr_cpu_core.c | 6 +----- target/ppc/mmu-hash64.c | 8 -------- 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index d09125d9af..ea5e11f1d9 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -58,14 +58,10 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) * we don't get spurious wakups before an RTAS start-cpu call. * For the same reason, set PSSCR_EC. */ - lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); + lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); lpcr |= LPCR_LPES0 | LPCR_LPES1; env->spr[SPR_PSSCR] |= PSSCR_EC; - /* Set RMLS to the max (ie, 16G) */ - lpcr &= ~LPCR_RMLS; - lpcr |= 1ull << LPCR_RMLS_SHIFT; - ppc_store_lpcr(cpu, lpcr); /* Set a full AMOR so guest can use the AMR as it sees fit */ diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0f9c0149e8..71e08801cc 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1126,14 +1126,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); - /* - * If we have a virtual hypervisor, we need to bring back RMLS. It - * doesn't exist on an actual P9 but that's all we know how to - * configure with softmmu at the moment - */ - if (cpu->vhyp) { - lpcr |= (val & LPCR_RMLS); - } break; default: g_assert_not_reached(); From patchwork Thu Feb 20 03:23:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393177 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4DE0F1395 for ; Thu, 20 Feb 2020 03:29:28 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E6CE42071E for ; Thu, 20 Feb 2020 03:29:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="VsGGg13E" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E6CE42071E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cWk-0007iv-TP for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:29:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41280) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR7-0004bU-Hi for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR6-0008Kx-8K for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:37 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:52931 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR5-0008ID-TE; Wed, 19 Feb 2020 22:23:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg04VZHz9sSL; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169004; bh=+8n08mVffDMTcd5vOcig56fSB0Fl8e0bs0SvTi5PJhE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VsGGg13EcPIgkM1N3o2sEiAHfD+qlgNIGoQbDJxr/cf/fwp9BhhT9Fma/MAiWvuWT KNyVLrN2ByMphMRjFmCCdCfdQGmeneJoT5xN+VjVXuW6WtBbvDOMUQNYCntV2ZzYu+ HmOqs0i3G5+lkBNOwDEDuQXQx4GG+4+kbWjO9pJo= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 06/18] target/ppc: Remove RMOR register from POWER9 & POWER10 Date: Thu, 20 Feb 2020 14:23:04 +1100 Message-Id: <20200220032317.96884-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently we create the Real Mode Offset Register (RMOR) on all Book3S cpus from POWER7 onwards. However the translation mode which the RMOR controls is no longer supported in POWER9, and so the register has been removed from the architecture. Remove it from our model on POWER9 and POWER10. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/translate_init.inc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index ab79975fec..925bc31ca5 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8015,12 +8015,16 @@ static void gen_spr_book3s_ids(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register_hv(env, SPR_RMOR, "RMOR", + spr_register_hv(env, SPR_HRMOR, "HRMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register_hv(env, SPR_HRMOR, "HRMOR", +} + +static void gen_spr_rmor(CPUPPCState *env) +{ + spr_register_hv(env, SPR_RMOR, "RMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -8535,6 +8539,7 @@ static void init_proc_POWER7(CPUPPCState *env) /* POWER7 Specific Registers */ gen_spr_book3s_ids(env); + gen_spr_rmor(env); gen_spr_amr(env); gen_spr_book3s_purr(env); gen_spr_power5p_common(env); @@ -8676,6 +8681,7 @@ static void init_proc_POWER8(CPUPPCState *env) /* POWER8 Specific Registers */ gen_spr_book3s_ids(env); + gen_spr_rmor(env); gen_spr_amr(env); gen_spr_iamr(env); gen_spr_book3s_purr(env); From patchwork Thu Feb 20 03:23:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393173 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9F9914E3 for ; Thu, 20 Feb 2020 03:28:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AFF2921D56 for ; Thu, 20 Feb 2020 03:28:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="PVIVMARj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AFF2921D56 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35308 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cVN-0005Wu-T5 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:28:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41299) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR7-0004bv-PB for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR6-0008Kr-5p for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:37 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:53519 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR5-0008IG-R1; Wed, 19 Feb 2020 22:23:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg05z0lz9sSS; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169004; bh=XybeyuGonoRfWhvkVUbbvr/LSdk75uUZN7T4a9TIaQM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PVIVMARjmJII8dVYFcProkupqsrbunhKJ1xR5TSWBQT+O3M8QYaj24jfgf5vzGtTz ItTS57HrfJiaMrRGkUSa2UhYWoNJ3QK0MxoWigCWMm+UP4fT6djm6it+0mLxFMfruH EyeUm0VZ0CsfyRr/2Xbq9UfMoDpZ1aMngthl/REg= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 07/18] target/ppc: Use class fields to simplify LPCR masking Date: Thu, 20 Feb 2020 14:23:05 +1100 Message-Id: <20200220032317.96884-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" When we store the Logical Partitioning Control Register (LPCR) we have a big switch statement to work out which are valid bits for the cpu model we're emulating. As well as being ugly, this isn't really conceptually correct, since it is based on the mmu_model variable, whereas the LPCR isn't (only) about the MMU, so mmu_model is basically just acting as a proxy for the cpu model. Handle this in a simpler way, by adding a suitable lpcr_mask to the QOM class. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/cpu-qom.h | 1 + target/ppc/mmu-hash64.c | 36 ++------------------------------- target/ppc/translate_init.inc.c | 27 +++++++++++++++++++++---- 3 files changed, 26 insertions(+), 38 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index e499575dc8..15d6b54a7d 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -177,6 +177,7 @@ typedef struct PowerPCCPUClass { uint64_t insns_flags; uint64_t insns_flags2; uint64_t msr_mask; + uint64_t lpcr_mask; /* Available bits in the LPCR */ uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ powerpc_mmu_t mmu_model; powerpc_excp_t excp_model; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 71e08801cc..8acd1f78ae 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1095,42 +1095,10 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu) void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) { + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; - uint64_t lpcr = 0; - /* Filter out bits */ - switch (env->mmu_model) { - case POWERPC_MMU_2_03: /* P5p */ - lpcr = val & (LPCR_RMLS | LPCR_ILE | - LPCR_LPES0 | LPCR_LPES1 | - LPCR_RMI | LPCR_HDICE); - break; - case POWERPC_MMU_2_06: /* P7 */ - lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | - LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | - LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | - LPCR_MER | LPCR_TC | - LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); - break; - case POWERPC_MMU_2_07: /* P8 */ - lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | - LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | - LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | - LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | - LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); - break; - case POWERPC_MMU_3_00: /* P9 */ - lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); - break; - default: - g_assert_not_reached(); - } - env->spr[SPR_LPCR] = lpcr; + env->spr[SPR_LPCR] = val & pcc->lpcr_mask; ppc_hash64_update_rmls(cpu); ppc_hash64_update_vrma(cpu); } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 925bc31ca5..5b7a5226e1 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8476,6 +8476,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI); + pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | + LPCR_RMI | LPCR_HDICE; pcc->mmu_model = POWERPC_MMU_2_03; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; @@ -8653,6 +8655,12 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | + LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | + LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | + LPCR_MER | LPCR_TC | + LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; + pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; @@ -8669,7 +8677,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; - pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; } static void init_proc_POWER8(CPUPPCState *env) @@ -8825,6 +8832,13 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_TS0) | (1ull << MSR_TS1) | (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | + LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | + LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | + LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | + LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; + pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | + LPCR_P8_PECE3 | LPCR_P8_PECE4; pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; @@ -8842,8 +8856,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; - pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | - LPCR_P8_PECE3 | LPCR_P8_PECE4; } #ifdef CONFIG_SOFTMMU @@ -9036,6 +9048,14 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | + LPCR_DEE | LPCR_OEE)) + | LPCR_MER | LPCR_GTSE | LPCR_TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; pcc->mmu_model = POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; @@ -9055,7 +9075,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; - pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; } #ifdef CONFIG_SOFTMMU From patchwork Thu Feb 20 03:23:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393183 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C081414E3 for ; Thu, 20 Feb 2020 03:30:58 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96468208C4 for ; Thu, 20 Feb 2020 03:30:58 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Wed, 19 Feb 2020 22:23:37 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:38161 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR5-0008II-Pk; Wed, 19 Feb 2020 22:23:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg070d5z9sSV; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169004; bh=RRBYOYs77/SsmZjN3ZGuK3pIJMM/GJemM7kFf49sycw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wwif7NwtdB4TenzmNsZ+RjNOtlGou4nM59pKCANpYKw8raH90KfoJiimXDUIBO3e/ URQDR1/UQgzrkoU0gFA0o4VQH3MgVtZtrIGOfnvHPVPKEqn69MVHAww874dP+phv2Y 84iiD9NrGJ5LbmLQfqKZF9tF7mqfgmP7tiJJ2yOc= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 08/18] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] Date: Thu, 20 Feb 2020 14:23:06 +1100 Message-Id: <20200220032317.96884-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently we use a big switch statement in ppc_hash64_update_rmls() to work out what the right RMA limit is based on the LPCR[RMLS] field. There's no formula for this - it's just an arbitrary mapping defined by the existing CPU implementations - but we can make it a bit more readable by using a lookup table rather than a switch. In addition we can use the MiB/GiB symbols to make it a bit clearer. While there we add a bit of clarity and rationale to the comment about what happens if the LPCR[RMLS] doesn't contain a valid value. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/mmu-hash64.c | 71 ++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 36 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 8acd1f78ae..4e6c1f722b 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -18,6 +18,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -757,6 +758,39 @@ static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); } +static target_ulong rmls_limit(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + /* + * This is the full 4 bits encoding of POWER8. Previous + * CPUs only support a subset of these but the filtering + * is done when writing LPCR + */ + const target_ulong rma_sizes[] = { + [0] = 0, + [1] = 16 * GiB, + [2] = 1 * GiB, + [3] = 64 * MiB, + [4] = 256 * MiB, + [5] = 0, + [6] = 0, + [7] = 128 * MiB, + [8] = 32 * MiB, + }; + target_ulong rmls = (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SHIFT; + + if (rmls < ARRAY_SIZE(rma_sizes)) { + return rma_sizes[rmls]; + } else { + /* + * Bad value, so the OS has shot itself in the foot. Return a + * 0-sized RMA which we expect to trigger an immediate DSI or + * ISI + */ + return 0; + } +} + int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { @@ -1006,41 +1040,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; } -static void ppc_hash64_update_rmls(PowerPCCPU *cpu) -{ - CPUPPCState *env = &cpu->env; - uint64_t lpcr = env->spr[SPR_LPCR]; - - /* - * This is the full 4 bits encoding of POWER8. Previous - * CPUs only support a subset of these but the filtering - * is done when writing LPCR - */ - switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { - case 0x8: /* 32MB */ - env->rmls = 0x2000000ull; - break; - case 0x3: /* 64MB */ - env->rmls = 0x4000000ull; - break; - case 0x7: /* 128MB */ - env->rmls = 0x8000000ull; - break; - case 0x4: /* 256MB */ - env->rmls = 0x10000000ull; - break; - case 0x2: /* 1GB */ - env->rmls = 0x40000000ull; - break; - case 0x1: /* 16GB */ - env->rmls = 0x400000000ull; - break; - default: - /* What to do here ??? */ - env->rmls = 0; - } -} - static void ppc_hash64_update_vrma(PowerPCCPU *cpu) { CPUPPCState *env = &cpu->env; @@ -1099,7 +1098,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env = &cpu->env; env->spr[SPR_LPCR] = val & pcc->lpcr_mask; - ppc_hash64_update_rmls(cpu); + env->rmls = rmls_limit(cpu); ppc_hash64_update_vrma(cpu); } From patchwork Thu Feb 20 03:23:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393159 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 905A514BC for ; Thu, 20 Feb 2020 03:24:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6779E21D56 for ; Thu, 20 Feb 2020 03:24:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="g6xxKlTu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6779E21D56 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRt-0006WR-Gp for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:24:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41318) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR8-0004cp-5m for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR6-0008Li-Mj for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:38 -0500 Received: from ozlabs.org ([203.11.71.1]:35861) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR6-0008Ic-Ba; Wed, 19 Feb 2020 22:23:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg11jDTz9sSZ; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169005; bh=5V3Fkwnhhaf99LksVVnXh9d+PmvLqtote/We8hZMvyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g6xxKlTuVDFRhFigVBuaLQmCrDvi0vQBdFF9uNx2gzCMU9hp+y3dU30Q1ljUMN1rt oRUbtAx/6d31zbwQMlZypyEH1RnF5LE4QFHqZADJldP5MGDI9wnculft6837DFCyaM nKuykWh2rP8WqShs8nr3pnAEoCmA1z6P7QzVx7MI= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 09/18] target/ppc: Correct RMLS table Date: Thu, 20 Feb 2020 14:23:07 +1100 Message-Id: <20200220032317.96884-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The table of RMA limits based on the LPCR[RMLS] field is slightly wrong. We're missing the RMLS == 0 => 256 GiB RMA option, which is available on POWER8, so add that. The comment that goes with the table is much more wrong. We *don't* filter invalid RMLS values when writing the LPCR, and there's not really a sensible way to do so. Furthermore, while in theory the set of RMLS values is implementation dependent, it seems in practice the same set has been available since around POWER4+ up until POWER8, the last model which supports RMLS at all. So, correct that as well. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/mmu-hash64.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 4e6c1f722b..46690bc79b 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -762,12 +762,12 @@ static target_ulong rmls_limit(PowerPCCPU *cpu) { CPUPPCState *env = &cpu->env; /* - * This is the full 4 bits encoding of POWER8. Previous - * CPUs only support a subset of these but the filtering - * is done when writing LPCR + * In theory the meanings of RMLS values are implementation + * dependent. In practice, this seems to have been the set from + * POWER4+..POWER8, and RMLS is no longer supported in POWER9. */ const target_ulong rma_sizes[] = { - [0] = 0, + [0] = 256 * GiB, [1] = 16 * GiB, [2] = 1 * GiB, [3] = 64 * MiB, From patchwork Thu Feb 20 03:23:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393175 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 443B01395 for ; Thu, 20 Feb 2020 03:28:04 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B38E21D56 for ; Thu, 20 Feb 2020 03:28:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="SCOA0Fdn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1B38E21D56 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cVP-0005ZW-8f for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:28:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41329) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR8-0004dS-GO for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR6-0008LT-In for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:38 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:44713 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR6-0008IZ-8Z; Wed, 19 Feb 2020 22:23:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg10cTLz9sSW; Thu, 20 Feb 2020 14:23:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169005; bh=pvwsDEYE4Sh8lhF4sfzNlBn6swIslRJZWqjlh3D2SbM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SCOA0Fdnjz7fP0Jcqy6RdfPF1AXX45I069o3JgaJXq4f56luCbOBJQ7Nr8VpkrFq9 yfx2+iYk+V45UE1phiEy/9TJdb9R83yM1U1qDyrDZidsY/V6yBYzq5+THoSmdvQcx4 jy1nO404KrSICQ/0fUxxlhekveEDCp9JoIrlrv6c= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 10/18] target/ppc: Only calculate RMLS derived RMA limit on demand Date: Thu, 20 Feb 2020 14:23:08 +1100 Message-Id: <20200220032317.96884-11-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" When the LPCR is written, we update the env->rmls field with the RMA limit it implies. Simplify things by just calculating the value directly from the LPCR value when we need it. It's possible this is a little slower, but it's unlikely to be significant, since this is only for real mode accesses in a translation configuration that's not used very often, and the whole thing is behind the qemu TLB anyway. Therefore, keeping the number of state variables down and not having to worry about making sure it's always in sync seems the better option. Signed-off-by: David Gibson Reviewed-by: Cédric Le Goater --- target/ppc/cpu.h | 1 - target/ppc/mmu-hash64.c | 8 +++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8077fdb068..f9871b1233 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1046,7 +1046,6 @@ struct CPUPPCState { uint64_t insns_flags2; #if defined(TARGET_PPC64) ppc_slb_t vrma_slb; - target_ulong rmls; #endif int error_code; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 46690bc79b..203a41cca1 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -844,8 +844,10 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, goto skip_slb_search; } else { + target_ulong limit = rmls_limit(cpu); + /* Emulated old-style RMO mode, bounds check against RMLS */ - if (raddr >= env->rmls) { + if (raddr >= limit) { if (rwx == 2) { ppc_hash64_set_isi(cs, SRR1_PROTFAULT); } else { @@ -1007,8 +1009,9 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) return -1; } } else { + target_ulong limit = rmls_limit(cpu); /* Emulated old-style RMO mode, bounds check against RMLS */ - if (raddr >= env->rmls) { + if (raddr >= limit) { return -1; } return raddr | env->spr[SPR_RMOR]; @@ -1098,7 +1101,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env = &cpu->env; env->spr[SPR_LPCR] = val & pcc->lpcr_mask; - env->rmls = rmls_limit(cpu); ppc_hash64_update_vrma(cpu); } From patchwork Thu Feb 20 03:23:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393189 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8078109A for ; Thu, 20 Feb 2020 03:33:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BEA0A208C4 for ; Thu, 20 Feb 2020 03:33:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="V+Hfp7eL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BEA0A208C4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4caI-00054T-T4 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:33:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41422) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRA-0004hr-Ck for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR8-0008OG-QJ for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:40 -0500 Received: from ozlabs.org ([203.11.71.1]:39081) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR8-0008LZ-E4; Wed, 19 Feb 2020 22:23:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg13CWcz9sSc; Thu, 20 Feb 2020 14:23:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169005; bh=/AkTT+ugkeVoIN+7JAwU/EPjvumM4GWvTt+5ak8RmnE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V+Hfp7eLFrRXopvCRvz6nO7ARk1rSqQEwuo7ETrNxWt/BHBEfRDwIwEhLSfCIZKho q8mvz/TI5/sHg0M/9hK6W+342h23K3FG0AEiNMuPfI0WpBJZ6s72SQ31Fg7PmV+d8P osXrhrcWP1v+1okxpm26CYrJC4Nt0EcD6dw5y6xI= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 11/18] target/ppc: Streamline construction of VRMA SLB entry Date: Thu, 20 Feb 2020 14:23:09 +1100 Message-Id: <20200220032317.96884-12-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" When in VRMA mode (i.e. a guest thinks it has the MMU off, but the hypervisor is still applying translation) we use a special SLB entry, rather than looking up an SLBE by address as we do when guest translation is on. We build that special entry in ppc_hash64_update_vrma() along with some logic for handling some non-VRMA cases. Split the actual build of the VRMA SLBE into a separate helper and streamline it a bit. Signed-off-by: David Gibson --- target/ppc/mmu-hash64.c | 74 +++++++++++++++++++---------------------- 1 file changed, 34 insertions(+), 40 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 203a41cca1..ac21c14f68 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -791,6 +791,35 @@ static target_ulong rmls_limit(PowerPCCPU *cpu) } } +static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb) +{ + CPUPPCState *env = &cpu->env; + target_ulong lpcr = env->spr[SPR_LPCR]; + uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; + target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK); + int i; + + for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { + const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i]; + + if (!sps->page_shift) { + break; + } + + if ((vsid & SLB_VSID_LLP_MASK) == sps->slb_enc) { + slb->esid = SLB_ESID_V; + slb->vsid = vsid; + slb->sps = sps; + return 0; + } + } + + error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x" + TARGET_FMT_lx"\n", lpcr); + + return -1; +} + int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { @@ -1046,53 +1075,18 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, static void ppc_hash64_update_vrma(PowerPCCPU *cpu) { CPUPPCState *env = &cpu->env; - const PPCHash64SegmentPageSizes *sps = NULL; - target_ulong esid, vsid, lpcr; ppc_slb_t *slb = &env->vrma_slb; - uint32_t vrmasd; - int i; - - /* First clear it */ - slb->esid = slb->vsid = 0; - slb->sps = NULL; /* Is VRMA enabled ? */ if (ppc_hash64_use_vrma(env)) { - return; - } - - /* - * Make one up. Mostly ignore the ESID which will not be needed - * for translation - */ - lpcr = env->spr[SPR_LPCR]; - vsid = SLB_VSID_VRMA; - vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; - vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); - esid = SLB_ESID_V; - - for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { - const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i]; - - if (!sps1->page_shift) { - break; - } - - if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { - sps = sps1; - break; + if (build_vrma_slbe(cpu, slb) == 0) { + return; } } - if (!sps) { - error_report("Bad page size encoding esid 0x"TARGET_FMT_lx - " vsid 0x"TARGET_FMT_lx, esid, vsid); - return; - } - - slb->vsid = vsid; - slb->esid = esid; - slb->sps = sps; + /* Otherwise, clear it to indicate error */ + slb->esid = slb->vsid = 0; + slb->sps = NULL; } void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) From patchwork Thu Feb 20 03:23:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393185 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 142AF14E3 for ; Thu, 20 Feb 2020 03:31:12 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DFC5D208C4 for ; Thu, 20 Feb 2020 03:31:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="WL5zyLIk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DFC5D208C4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35370 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cYR-0002Jb-3c for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:31:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41388) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR9-0004ga-Pr for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR8-0008Np-Gf for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:39 -0500 Received: from ozlabs.org ([203.11.71.1]:58371) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR8-0008Kc-4P; Wed, 19 Feb 2020 22:23:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg12dMkz9sSY; Thu, 20 Feb 2020 14:23:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169005; bh=/gYCLL/Jk6TTuPaJCqEEFdhUfEKdZ2BLlTEIKLhOQP8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WL5zyLIkqdSFt24TjxqU9HWZCpTaaILt0qXt6clbGtcL8+QBdEOpkdZCP4PnMMfi2 jf6gmSq1Iwg930gNLCnGZAZafuyhhDidORlgIMkKvj4rJaS+6D58WXS/41iTZXq2s1 GZrAa7iPS86pSx7r/BYKyYhKwnszQpdZkaCSMtFw= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 12/18] target/ppc: Don't store VRMA SLBE persistently Date: Thu, 20 Feb 2020 14:23:10 +1100 Message-Id: <20200220032317.96884-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, we construct the SLBE used for VRMA translations when the LPCR is written (which controls some bits in the SLBE), then use it later for translations. This is a bit complex and confusing - simplify it by simply constructing the SLBE directly from the LPCR when we need it. Signed-off-by: David Gibson --- target/ppc/cpu.h | 3 --- target/ppc/mmu-hash64.c | 28 ++++++---------------------- 2 files changed, 6 insertions(+), 25 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f9871b1233..5a55fb02bd 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1044,9 +1044,6 @@ struct CPUPPCState { uint32_t flags; uint64_t insns_flags; uint64_t insns_flags2; -#if defined(TARGET_PPC64) - ppc_slb_t vrma_slb; -#endif int error_code; uint32_t pending_interrupts; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index ac21c14f68..f8bf92aa2e 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -825,6 +825,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; + ppc_slb_t vrma_slbe; ppc_slb_t *slb; unsigned apshift; hwaddr ptex; @@ -863,8 +864,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, } } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ - slb = &env->vrma_slb; - if (!slb->sps) { + slb = &vrma_slbe; + if (build_vrma_slbe(cpu, slb) != 0) { /* Invalid VRMA setup, machine check */ cs->exception_index = POWERPC_EXCP_MCHECK; env->error_code = 0; @@ -1012,6 +1013,7 @@ skip_slb_search: hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) { CPUPPCState *env = &cpu->env; + ppc_slb_t vrma_slbe; ppc_slb_t *slb; hwaddr ptex, raddr; ppc_hash_pte64_t pte; @@ -1033,8 +1035,8 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) return raddr | env->spr[SPR_HRMOR]; } else if (ppc_hash64_use_vrma(env)) { /* Emulated VRMA mode */ - slb = &env->vrma_slb; - if (!slb->sps) { + slb = &vrma_slbe; + if (build_vrma_slbe(cpu, slb) != 0) { return -1; } } else { @@ -1072,30 +1074,12 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; } -static void ppc_hash64_update_vrma(PowerPCCPU *cpu) -{ - CPUPPCState *env = &cpu->env; - ppc_slb_t *slb = &env->vrma_slb; - - /* Is VRMA enabled ? */ - if (ppc_hash64_use_vrma(env)) { - if (build_vrma_slbe(cpu, slb) == 0) { - return; - } - } - - /* Otherwise, clear it to indicate error */ - slb->esid = slb->vsid = 0; - slb->sps = NULL; -} - void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) { PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; env->spr[SPR_LPCR] = val & pcc->lpcr_mask; - ppc_hash64_update_vrma(cpu); } void helper_store_lpcr(CPUPPCState *env, target_ulong val) From patchwork Thu Feb 20 03:23:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393179 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD0381395 for ; Thu, 20 Feb 2020 03:29:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B4B9F24658 for ; Thu, 20 Feb 2020 03:29:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="LPb+al20" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B4B9F24658 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35328 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cWy-00086Y-Uj for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:29:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41414) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRA-0004hW-6Z for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR8-0008OL-RD for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:40 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:54247 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR8-0008Lu-EH; Wed, 19 Feb 2020 22:23:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg14yzfz9sSh; Thu, 20 Feb 2020 14:23:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169005; bh=aBsVfkPLqtLYAJVvSFLlYU9uQn9tdTvG94/i9S6mjsA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LPb+al20cCFacYersPRalufjTqONeNU/DZV7uLBy99XtsjdqDveCO4qmJKZXWAtVm NmY6I9d8uJF8nZVyKat600DJNRnszh1Dw3Mv1PNP3JOqao8CMmv6JuKjhGjgREBuZp +wXsRdv3R5y1oQMqeiWA2xSauvSErJ/E1WquWrQg= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 13/18] spapr: Don't use weird units for MIN_RMA_SLOF Date: Thu, 20 Feb 2020 14:23:11 +1100 Message-Id: <20200220032317.96884-14-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" MIN_RMA_SLOF records the minimum about of RMA that the SLOF firmware requires. It lets us give a meaningful error if the RMA ends up too small, rather than just letting SLOF crash. It's currently stored as a number of megabytes, which is strange for global constants. Move that megabyte scaling into the definition of the constant like most other things use. Change from M to MiB in the associated message while we're at it. Signed-off-by: David Gibson --- hw/ppc/spapr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 828e2cc135..272a270b7a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -103,7 +103,7 @@ #define FW_OVERHEAD 0x2800000 #define KERNEL_LOAD_ADDR FW_MAX_SIZE -#define MIN_RMA_SLOF 128UL +#define MIN_RMA_SLOF (128 * MiB) #define PHANDLE_INTC 0x00001111 @@ -2959,10 +2959,10 @@ static void spapr_machine_init(MachineState *machine) } } - if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { + if (spapr->rma_size < MIN_RMA_SLOF) { error_report( - "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", - MIN_RMA_SLOF); + "pSeries SLOF firmware requires >= %ldMiB guest RMA (Real Mode Area memory)", + MIN_RMA_SLOF / MiB); exit(1); } From patchwork Thu Feb 20 03:23:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393181 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1FF1314E3 for ; Thu, 20 Feb 2020 03:29:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EB36E2071E for ; Thu, 20 Feb 2020 03:29:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="mEi1Hdjy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EB36E2071E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cXB-0008Qd-4v for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:29:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41413) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRA-0004hT-67 for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR8-0008O1-KH for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:40 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:41493 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR8-0008Lc-8q; Wed, 19 Feb 2020 22:23:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg14C5jz9sSb; Thu, 20 Feb 2020 14:23:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169005; bh=G9vVCBQAxL325dmu2RbgIx5Jm0SP2MYRe+FEiLxyaO4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mEi1Hdjy9ycQjWRge4BcINSs794W0lUQ5KkNflv/Rqd/7acOnV5qRTie6Tv3R7Pld SejIDBCRZyyCkZ7hcxrFgSkgV14XMbedJcK+TznrJmxmjfe5eY9ATDJe4h+vtafr3V 07RDcM9WREjc05jgse91yLqfiVE04PpJZOCuTx2g= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 14/18] spapr,ppc: Simplify signature of kvmppc_rma_size() Date: Thu, 20 Feb 2020 14:23:12 +1100 Message-Id: <20200220032317.96884-15-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , Cedric Le Goater , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This function calculates the maximum size of the RMA as implied by the host's page size of structure of the VRMA (there are a number of other constraints on the RMA size which will supersede this one in many circumstances). The current interface takes the current RMA size estimate, and clamps it to the VRMA derived size. The only current caller passes in an arguably wrong value (it will match the current RMA estimate in some but not all cases). We want to fix that, but for now just keep concerns separated by having the KVM helper function just return the VRMA derived limit, and let the caller combine it with other constraints. We call the new function kvmppc_vrma_limit() to more clearly indicate its limited responsibility. The helper should only ever be called in the KVM enabled case, so replace its !CONFIG_KVM stub with an assert() rather than a dummy value. Signed-off-by: David Gibson Reviewed-by: Cedric Le Goater Reviewed-by: Greg Kurz Reviewed-by: Alexey Kardashevskiy --- hw/ppc/spapr.c | 5 +++-- target/ppc/kvm.c | 5 ++--- target/ppc/kvm_ppc.h | 7 +++---- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 272a270b7a..b68d80ba69 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1586,8 +1586,9 @@ void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); if (spapr->vrma_adjust) { - spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), - spapr->htab_shift); + hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); + + spapr->rma_size = MIN(spapr_node0_size(MACHINE(spapr)), vrma_limit); } } diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 7f44b1aa1a..597f72be1b 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2113,7 +2113,7 @@ void kvmppc_error_append_smt_possible_hint(Error *const *errp) #ifdef TARGET_PPC64 -uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) +uint64_t kvmppc_vrma_limit(unsigned int hash_shift) { struct kvm_ppc_smmu_info info; long rampagesize, best_page_shift; @@ -2140,8 +2140,7 @@ uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) } } - return MIN(current_size, - 1ULL << (best_page_shift + hash_shift - 7)); + return 1ULL << (best_page_shift + hash_shift - 7); } #endif diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 9e4f2357cc..332fa0aa1c 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -47,7 +47,7 @@ void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift, int *pfd, bool need_vfio); int kvmppc_remove_spapr_tce(void *table, int pfd, uint32_t window_size); int kvmppc_reset_htab(int shift_hint); -uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift); +uint64_t kvmppc_vrma_limit(unsigned int hash_shift); bool kvmppc_has_cap_spapr_vfio(void); #endif /* !CONFIG_USER_ONLY */ bool kvmppc_has_cap_epr(void); @@ -255,10 +255,9 @@ static inline int kvmppc_reset_htab(int shift_hint) return 0; } -static inline uint64_t kvmppc_rma_size(uint64_t current_size, - unsigned int hash_shift) +static inline uint64_t kvmppc_vrma_limit(unsigned int hash_shift) { - return ram_size; + g_assert_not_reached(); } static inline bool kvmppc_hpt_needs_host_contiguous_pages(void) From patchwork Thu Feb 20 03:23:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BF8E109A for ; Thu, 20 Feb 2020 03:31:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 22E82208C4 for ; Thu, 20 Feb 2020 03:31:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="nwaIdGg9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 22E82208C4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cZ8-00038d-Ak for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:31:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41477) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRB-0004k0-AR for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR9-0008Ot-8b for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:41 -0500 Received: from ozlabs.org ([203.11.71.1]:41079) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR8-0008MT-S2; Wed, 19 Feb 2020 22:23:39 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg23hyDz9sSt; Thu, 20 Feb 2020 14:23:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169006; bh=QIIJTxC1CVum2uJ2TEw+qN4tR/LbdQA/xEU74HqkcYg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nwaIdGg9AWyrb/ilDRiQh7IwMeJCZmTTqkxep+ghY5CL0JwmcMkpaVHq5eRwK9CHt NHNOHp+GgeX705sC2WJBMxX2+NuPI+2FwoiHHrZ5eMaaIzg/6ZB+fAOE7f7TvqI2vk J+kWZ/b8ZxeEUkBuq/jrerWUjteQcEZAb4e3BR4Y= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 15/18] spapr: Don't attempt to clamp RMA to VRMA constraint Date: Thu, 20 Feb 2020 14:23:13 +1100 Message-Id: <20200220032317.96884-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The Real Mode Area (RMA) is the part of memory which a guest can access when in real (MMU off) mode. Of course, for a guest under KVM, the MMU isn't really turned off, it's just in a special translation mode - Virtual Real Mode Area (VRMA) - which looks like real mode in guest mode. The mechanics of how this works when using the hash MMU (HPT) put a constraint on the size of the RMA, which depends on the size of the HPT. So, the latter part of spapr_setup_hpt_and_vrma() clamps the RMA we advertise to the guest based on this VRMA limit. There are several things wrong with this: 1) spapr_setup_hpt_and_vrma() doesn't actually clamp, it takes the minimum of Node 0 memory size and the VRMA limit. That will *often* work the same as clamping, but there can be other constraints on RMA size which supersede Node 0 memory size. We have real bugs caused by this (currently worked around in the guest kernel) 2) Some callers of spapr_setup_hpt_and_vrma() are in a situation where we're past the point that we can actually advertise an RMA limit to the guest 3) But most fundamentally, the VRMA limit depends on host configuration (page size) which shouldn't be visible to the guest, but this partially exposes it. This can cause problems with migration in certain edge cases, although we will mostly get away with it. In practice, this clamping is almost never applied anyway. With 64kiB pages and the normal rules for sizing of the HPT, the theoretical VRMA limit will be 4x(guest memory size) and so never hit. It will hit with 4kiB pages, where it will be (guest memory size)/4. However all mainstream distro kernels for POWER have used a 64kiB page size for at least 10 years. So, simply replace this logic with a check that the RMA we've calculated based only on guest visible configuration will fit within the host implied VRMA limit. This can break if running HPT guests on a host kernel with 4kiB page size. As noted that's very rare. There also exist several possible workarounds: * Change the host kernel to use 64kiB pages * Use radix MMU (RPT) guests instead of HPT * Use 64kiB hugepages on the host to back guest memory * Increase the guest memory size so that the RMA hits one of the fixed limits before the RMA limit. This is relatively easy on POWER8 which has a 16GiB limit, harder on POWER9 which has a 1TiB limit. * Use a guest NUMA configuration which artificially constrains the RMA within the VRMA limit (the RMA must always fit within Node 0). Previously, on KVM, we also temporarily reduced the rma_size to 256M so that the we'd load the kernel and initrd safely, regardless of the VRMA limit. This was a) confusing, b) could significantly limit the size of images we could load and c) introduced a behavioural difference between KVM and TCG. So we remove that as well. Signed-off-by: David Gibson Reviewed-by: Alexey Kardashevskiy --- hw/ppc/spapr.c | 28 ++++++++++------------------ hw/ppc/spapr_hcall.c | 4 ++-- include/hw/ppc/spapr.h | 3 +-- 3 files changed, 13 insertions(+), 22 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b68d80ba69..4dab489931 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1569,7 +1569,7 @@ void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); } -void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) +void spapr_setup_hpt(SpaprMachineState *spapr) { int hpt_shift; @@ -1585,10 +1585,16 @@ void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) } spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); - if (spapr->vrma_adjust) { + if (kvm_enabled()) { hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); - spapr->rma_size = MIN(spapr_node0_size(MACHINE(spapr)), vrma_limit); + /* Check our RMA fits in the possible VRMA */ + if (vrma_limit < spapr->rma_size) { + error_report("Unable to create %" HWADDR_PRIu + "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", + spapr->rma_size / MiB, vrma_limit / MiB); + exit(EXIT_FAILURE); + } } } @@ -1628,7 +1634,7 @@ static void spapr_machine_reset(MachineState *machine) spapr->patb_entry = PATE1_GR; spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); } else { - spapr_setup_hpt_and_vrma(spapr); + spapr_setup_hpt(spapr); } qemu_devices_reset(); @@ -2696,20 +2702,6 @@ static void spapr_machine_init(MachineState *machine) spapr->rma_size = node0_size; - /* With KVM, we don't actually know whether KVM supports an - * unbounded RMA (PR KVM) or is limited by the hash table size - * (HV KVM using VRMA), so we always assume the latter - * - * In that case, we also limit the initial allocations for RTAS - * etc... to 256M since we have no way to know what the VRMA size - * is going to be as it depends on the size of the hash table - * which isn't determined yet. - */ - if (kvm_enabled()) { - spapr->vrma_adjust = 1; - spapr->rma_size = MIN(spapr->rma_size, 0x10000000); - } - /* Actually we don't support unbounded RMA anymore since we added * proper emulation of HV mode. The max we can get is 16G which * also happens to be what we configure for PAPR mode so make sure diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 6db3dbde9c..11e8a4f153 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1458,7 +1458,7 @@ static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, spapr_free_hpt(spapr); } else if (!(patbe_new & PATE1_GR)) { /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ - spapr_setup_hpt_and_vrma(spapr); + spapr_setup_hpt(spapr); } return; } @@ -1846,7 +1846,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, * (because the guest isn't going to use radix) then set it up here. */ if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { /* legacy hash or new hash: */ - spapr_setup_hpt_and_vrma(spapr); + spapr_setup_hpt(spapr); } if (fdt_bufsize < sizeof(hdr)) { diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 09110961a5..fc49c1a710 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -156,7 +156,6 @@ struct SpaprMachineState { SpaprPendingHpt *pending_hpt; /* in-progress resize */ hwaddr rma_size; - int vrma_adjust; uint32_t fdt_size; uint32_t fdt_initial_size; void *fdt_blob; @@ -795,7 +794,7 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); void spapr_events_init(SpaprMachineState *sm); void spapr_dt_events(SpaprMachineState *sm, void *fdt); void close_htab_fd(SpaprMachineState *spapr); -void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr); +void spapr_setup_hpt(SpaprMachineState *spapr); void spapr_free_hpt(SpaprMachineState *spapr); SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); void spapr_tce_table_enable(SpaprTceTable *tcet, From patchwork Thu Feb 20 03:23:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393193 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2837814E3 for ; Thu, 20 Feb 2020 03:34:44 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AE880208C4 for ; Thu, 20 Feb 2020 03:34:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="KlwVbPdA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AE880208C4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cbq-0007Y4-Mz for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:34:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41426) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRA-0004iA-Hs for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR8-0008OZ-T6 for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:40 -0500 Received: from ozlabs.org ([203.11.71.1]:48641) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR8-0008Lz-FZ; Wed, 19 Feb 2020 22:23:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg20t9Hz9sSd; Thu, 20 Feb 2020 14:23:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169006; bh=5vj5hZheaPC8JaSv3aSxTYhdCA9hs4iVnlvVk/qgUQc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KlwVbPdAniOO+nlxBGibIneDQ3m00QAERwWxPSjtdhgRAZfRx8mok+o+s15nCHi2H ohW4lTAIcTRKWYNZEz/dSd24iHEYjI8PZYKPfHOrJw8CJ4IjoQUvRim1LBHe3h/8pf hb4qxH9fVfyBIoF+cxDzim3iZvN+zCSu4ScCGHpQ= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 16/18] spapr: Don't clamp RMA to 16GiB on new machine types Date: Thu, 20 Feb 2020 14:23:14 +1100 Message-Id: <20200220032317.96884-17-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" In spapr_machine_init() we clamp the size of the RMA to 16GiB and the comment saying why doesn't make a whole lot of sense. In fact, this was done because the real mode handling code elsewhere limited the RMA in TCG mode to the maximum value configurable in LPCR[RMLS], 16GiB. But, * Actually LPCR[RMLS] has been able to encode a 256GiB size for a very long time, we just didn't implement it properly in the softmmu * LPCR[RMLS] shouldn't really be relevant anyway, it only was because we used to abuse the RMOR based translation mode in order to handle the fact that we're not modelling the hypervisor parts of the cpu We've now removed those limitations in the modelling so the 16GiB clamp no longer serves a function. However, we can't just remove the limit universally: that would break migration to earlier qemu versions, where the 16GiB RMLS limit still applies, no matter how bad the reasons for it are. So, we replace the 16GiB clamp, with a clamp to a limit defined in the machine type class. We set it to 16 GiB for machine types 4.2 and earlier, but set it to 0 meaning unlimited for the new 5.0 machine type. Signed-off-by: David Gibson --- hw/ppc/spapr.c | 13 ++++++++----- include/hw/ppc/spapr.h | 1 + 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 4dab489931..6e9f15f64d 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2702,12 +2702,14 @@ static void spapr_machine_init(MachineState *machine) spapr->rma_size = node0_size; - /* Actually we don't support unbounded RMA anymore since we added - * proper emulation of HV mode. The max we can get is 16G which - * also happens to be what we configure for PAPR mode so make sure - * we don't do anything bigger than that + /* + * Clamp the RMA size based on machine type. This is for + * migration compatibility with older qemu versions, which limited + * the RMA size for complicated and mostly bad reasons. */ - spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); + if (smc->rma_limit) { + spapr->rma_size = MIN(spapr->rma_size, smc->rma_limit); + } if (spapr->rma_size > node0_size) { error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", @@ -4600,6 +4602,7 @@ static void spapr_machine_4_2_class_options(MachineClass *mc) compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF; + smc->rma_limit = 16 * GiB; mc->nvdimm_supported = false; } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index fc49c1a710..8a44a1f488 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -126,6 +126,7 @@ struct SpaprMachineClass { bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ bool linux_pci_probe; bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ + hwaddr rma_limit; /* clamp the RMA to this size */ void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio, From patchwork Thu Feb 20 03:23:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BF00E109A for ; Thu, 20 Feb 2020 03:34:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96005208C4 for ; Thu, 20 Feb 2020 03:34:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="VW3UMOPF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 96005208C4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cc0-0007o2-Q7 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:34:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41441) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRA-0004ik-Pi for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR9-0008PE-Dt for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:40 -0500 Received: from ozlabs.org ([203.11.71.1]:49623) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR9-0008Ma-23; Wed, 19 Feb 2020 22:23:39 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg306Frz9sSx; Thu, 20 Feb 2020 14:23:26 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169007; bh=2HMMcHS71SZcl1mdEZbUO8BqzSboB4TqxyWpdz2JwgM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VW3UMOPFhLjxzUaxL+TwjyZFBImw5w+P3irNmlszwdWfsSFVdSISKqVvF21Ozxkq0 0Ot227sXBibSGXqL9rBcBbkMcsf5VJAps0xEkMbv9Lfgfv1Wyr8E3X/KitG9kdme54 0u0HFAs2mE4YMzx3pErv3ey74t+41KKFn8XNS+N0= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 17/18] spapr: Clean up RMA size calculation Date: Thu, 20 Feb 2020 14:23:15 +1100 Message-Id: <20200220032317.96884-18-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Move the calculation of the Real Mode Area (RMA) size into a helper function. While we're there clean it up and correct it in a few ways: * Add comments making it clearer where the various constraints come from * Remove a pointless check that the RMA fits within Node 0 (we've just clamped it so that it does) Signed-off-by: David Gibson --- hw/ppc/spapr.c | 59 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 24 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 6e9f15f64d..f0354b699d 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2648,6 +2648,40 @@ static PCIHostState *spapr_create_default_phb(void) return PCI_HOST_BRIDGE(dev); } +static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) +{ + MachineState *machine = MACHINE(spapr); + hwaddr rma_size = machine->ram_size; + hwaddr node0_size = spapr_node0_size(machine); + + /* RMA has to fit in the first NUMA node */ + rma_size = MIN(rma_size, node0_size); + + /* + * VRMA access is via a special 1TiB SLB mapping, so the RMA can + * never exceed that + */ + rma_size = MIN(rma_size, TiB); + + /* + * Clamp the RMA size based on machine type. This is for + * migration compatibility with older qemu versions, which limited + * the RMA size for complicated and mostly bad reasons. + */ + if (smc->rma_limit) { + spapr->rma_size = MIN(spapr->rma_size, smc->rma_limit); + } + + if (rma_size < (MIN_RMA_SLOF * MiB)) { + error_setg(errp, +"pSeries SLOF firmware requires >= %ldMiB guest RMA (Real Mode Area)", + MIN_RMA_SLOF); + return -1; + } + + return rma_size; +} + /* pSeries LPAR / sPAPR hardware init */ static void spapr_machine_init(MachineState *machine) { @@ -2660,7 +2694,6 @@ static void spapr_machine_init(MachineState *machine) int i; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); - hwaddr node0_size = spapr_node0_size(machine); long load_limit, fw_size; char *filename; Error *resize_hpt_err = NULL; @@ -2700,22 +2733,7 @@ static void spapr_machine_init(MachineState *machine) exit(1); } - spapr->rma_size = node0_size; - - /* - * Clamp the RMA size based on machine type. This is for - * migration compatibility with older qemu versions, which limited - * the RMA size for complicated and mostly bad reasons. - */ - if (smc->rma_limit) { - spapr->rma_size = MIN(spapr->rma_size, smc->rma_limit); - } - - if (spapr->rma_size > node0_size) { - error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", - spapr->rma_size); - exit(1); - } + spapr->rma_size = spapr_rma_size(spapr, &error_fatal); /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; @@ -2954,13 +2972,6 @@ static void spapr_machine_init(MachineState *machine) } } - if (spapr->rma_size < MIN_RMA_SLOF) { - error_report( - "pSeries SLOF firmware requires >= %ldMiB guest RMA (Real Mode Area memory)", - MIN_RMA_SLOF / MiB); - exit(1); - } - if (kernel_filename) { uint64_t lowaddr = 0; From patchwork Thu Feb 20 03:23:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11393169 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B0DC01395 for ; Thu, 20 Feb 2020 03:26:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8795B21D56 for ; Thu, 20 Feb 2020 03:26:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="P9l/S2Xu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8795B21D56 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cUJ-0003BQ-PD for patchwork-qemu-devel@patchwork.kernel.org; Wed, 19 Feb 2020 22:26:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41646) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cRU-0005cy-FV for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:24:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cRT-0000L2-B2 for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:24:00 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:58279 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cRT-0008MX-0c; Wed, 19 Feb 2020 22:23:59 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg250nsz9sSk; Thu, 20 Feb 2020 14:23:26 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169006; bh=GyzBZMDoAMPRnJCvIsnfxFsMHlBhNBqGfLr4nb9ELlM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P9l/S2XupeblVRk6FAraFfTj56Bl+B4I9PdBWu5OQ5aVh+1VhCQGmo8iCPSc7D+M1 1TYuIuOODHoZARciHmZnugdzmMnu1M6LSkz3Db4oJXU1vJXdCH2n3oEG031ikjRX19 czyqRXPmtSqHLxUZ01KTlbymj0PopsHTGaWq9+Rw= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 18/18] spapr: Fold spapr_node0_size() into its only caller Date: Thu, 20 Feb 2020 14:23:16 +1100 Message-Id: <20200220032317.96884-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The Real Mode Area (RMA) needs to fit within the NUMA node owning memory at address 0. That's usually node 0, but can be a later one if there are some nodes which have no memory (only CPUs). This is currently handled by the spapr_node0_size() helper. It has only one caller, so there's not a lot of point splitting it out. It's also extremely easy to misread the code as clamping to the size of the smallest node rather than the first node with any memory. So, fold it into the caller, and add some commentary to make it a bit clearer exactly what it's doing. Signed-off-by: David Gibson --- hw/ppc/spapr.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f0354b699d..9ba645c9cb 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -296,20 +296,6 @@ static void spapr_populate_pa_features(SpaprMachineState *spapr, _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); } -static hwaddr spapr_node0_size(MachineState *machine) -{ - if (machine->numa_state->num_nodes) { - int i; - for (i = 0; i < machine->numa_state->num_nodes; ++i) { - if (machine->numa_state->nodes[i].node_mem) { - return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), - machine->ram_size); - } - } - } - return machine->ram_size; -} - static void add_str(GString *s, const gchar *s1) { g_string_append_len(s, s1, strlen(s1) + 1); @@ -2652,10 +2638,24 @@ static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) { MachineState *machine = MACHINE(spapr); hwaddr rma_size = machine->ram_size; - hwaddr node0_size = spapr_node0_size(machine); /* RMA has to fit in the first NUMA node */ - rma_size = MIN(rma_size, node0_size); + if (machine->numa_state->num_nodes) { + /* + * It's possible for there to be some zero-memory nodes first + * in the list. We need the RMA to fit inside the memory of + * the first node which actually has some memory. + */ + int i; + + for (i = 0; i < machine->numa_state->num_nodes; ++i) { + if (machine->numa_state->nodes[i].node_mem != 0) { + rma_size = MIN(rma_size, + machine->numa_state->nodes[i].node_mem); + break; + } + } + } /* * VRMA access is via a special 1TiB SLB mapping, so the RMA can @@ -2672,6 +2672,11 @@ static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) spapr->rma_size = MIN(spapr->rma_size, smc->rma_limit); } + /* + * RMA size must be a power of 2 + */ + rma_size = pow2floor(rma_size); + if (rma_size < (MIN_RMA_SLOF * MiB)) { error_setg(errp, "pSeries SLOF firmware requires >= %ldMiB guest RMA (Real Mode Area)",