From patchwork Sat Feb 22 10:25:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11398043 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8CABF109A for ; Sat, 22 Feb 2020 10:26:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 587342192A for ; Sat, 22 Feb 2020 10:26:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="kMvFsUNk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727247AbgBVK0E (ORCPT ); Sat, 22 Feb 2020 05:26:04 -0500 Received: from mo4-p02-ob.smtp.rzone.de ([81.169.146.170]:21597 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726763AbgBVK0B (ORCPT ); Sat, 22 Feb 2020 05:26:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582367158; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=cBdMvB+ZAt2Ro9a10DB3XI6liBhMUR4iU151lcfcamk=; b=kMvFsUNkwQnzUPDKNHEStuy1TCx6mUJOtARWZwXf73WGnW29/T5HiL2K5dN5tiMROm C+LK/yelX/94MMMOex/b8Gw8L13Hmi1UWfT7/t6LC+81v1ISnQBhbtgSGWrnFlP8R6ux ZbomS87U3ojY/YjPiyICBHthsUjzfAL01hCm5IE9wvB6PbAbPI1pCEVkhvBgt61AnD5m hIYonn5EdLvJxjcWnXMD8/DQzbKiqqN/j65mmqR8kR84++hQ40y9bBfyV0oXgN55JL6A wpi/0nUomxpfUxR7DOf/is+CJ34qiYqsl6UXJxNGjqttStd8GZ73WeWQuoUAdYC1oaDW OIcw== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0pAz7pC6Q5M" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1MAPijMa (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sat, 22 Feb 2020 11:25:44 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v5 1/6] nvmem: add driver for JZ4780 efuse Date: Sat, 22 Feb 2020 11:25:36 +0100 Message-Id: <1c180f72967425a365295770e7f98426e0f7714f.1582367141.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre Signed-off-by: H. Nikolaus Schaller Signed-off-by: Paul Cercueil --- drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 229 +++++++++++++++++++++++++++++++++++ 3 files changed, 241 insertions(+) create mode 100644 drivers/nvmem/jz4780-efuse.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 35efab1ba8d9..8143e6e1dd82 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -55,6 +55,16 @@ config NVMEM_IMX_OCOTP_SCU This is a driver for the SCU On-Chip OTP Controller (OCOTP) available on i.MX8 SoCs. +config JZ4780_EFUSE + tristate "JZ4780 EFUSE Memory Support" + depends on MACH_INGENIC || COMPILE_TEST + depends on HAS_IOMEM + help + Say Y here to include support for JZ4780 efuse memory found on + all JZ4780 SoC based devices. + To compile this driver as a module, choose M here: the module + will be called nvmem_jz4780_efuse. + config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6b466cd1427b..65a268d17807 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +nvmem_jz4780_efuse-y := jz4780-efuse.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c new file mode 100644 index 000000000000..08b63de0e9cc --- /dev/null +++ b/drivers/nvmem/jz4780-efuse.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * JZ4780 EFUSE Memory Support driver + * + * Copyright (c) 2017 PrasannaKumar Muralidharan + * Copyright (c) 2020 H. Nikolaus Schaller + */ + +/* + * Currently supports JZ4780 efuse which has 8K programmable bit. + * Efuse is separated into seven segments as below: + * + * ----------------------------------------------------------------------- + * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit | + * ----------------------------------------------------------------------- + * + * The rom itself is accessed using a 9 bit address line and an 8 word wide bus + * which reads/writes based on strobes. The strobe is configured in the config + * register and is based on number of cycles of the bus clock. + * + * Driver supports read only as the writes are done in the Factory. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define JZ_EFUCTRL (0x0) /* Control Register */ +#define JZ_EFUCFG (0x4) /* Configure Register*/ +#define JZ_EFUSTATE (0x8) /* Status Register */ +#define JZ_EFUDATA(n) (0xC + (n) * 4) + +#define EFUCTRL_ADDR_MASK 0x3FF +#define EFUCTRL_ADDR_SHIFT 21 +#define EFUCTRL_LEN_MASK 0x1F +#define EFUCTRL_LEN_SHIFT 16 +#define EFUCTRL_PG_EN BIT(15) +#define EFUCTRL_WR_EN BIT(1) +#define EFUCTRL_RD_EN BIT(0) + +#define EFUCFG_INT_EN BIT(31) +#define EFUCFG_RD_ADJ_MASK 0xF +#define EFUCFG_RD_ADJ_SHIFT 20 +#define EFUCFG_RD_STR_MASK 0xF +#define EFUCFG_RD_STR_SHIFT 16 +#define EFUCFG_WR_ADJ_MASK 0xF +#define EFUCFG_WR_ADJ_SHIFT 12 +#define EFUCFG_WR_STR_MASK 0xFFF +#define EFUCFG_WR_STR_SHIFT 0 + +#define EFUSTATE_WR_DONE BIT(1) +#define EFUSTATE_RD_DONE BIT(0) + +struct jz4780_efuse { + struct device *dev; + struct regmap *map; + struct clk *clk; + unsigned int rd_adj; + unsigned int rd_strobe; +}; + +/* We read 32 byte chunks to avoid complexity in the driver. */ +static int jz4780_efuse_read_32bytes(struct jz4780_efuse *efuse, char *buf, + unsigned int addr) +{ + unsigned int tmp; + u32 ctrl; + int ret; + const int size = 32; + + ctrl = (addr << EFUCTRL_ADDR_SHIFT) + | ((size - 1) << EFUCTRL_LEN_SHIFT) + | EFUCTRL_RD_EN; + + regmap_update_bits(efuse->map, JZ_EFUCTRL, + (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) | + (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) | + EFUCTRL_PG_EN | EFUCTRL_WR_EN | EFUCTRL_RD_EN, ctrl); + + ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE, + tmp, tmp & EFUSTATE_RD_DONE, + 1 * MSEC_PER_SEC, 50 * MSEC_PER_SEC); + if (ret < 0) { + dev_err(efuse->dev, "Time out while reading efuse data"); + return ret; + } + + return regmap_bulk_read(efuse->map, JZ_EFUDATA(0), + buf, size / sizeof(u32)); +} + +/* main entry point */ +static int jz4780_efuse_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct jz4780_efuse *efuse = context; + int ret; + const int size = 32; + + while (bytes > 0) { + unsigned int start = offset & ~(size - 1); + unsigned int chunk = min(bytes, (start + size) - offset); + + if (start == offset && chunk == size) { + ret = jz4780_efuse_read_32bytes(efuse, val, start); + if (ret < 0) + return ret; + + } else { + char buf[32]; + + ret = jz4780_efuse_read_32bytes(efuse, buf, start); + if (ret < 0) + return ret; + + memcpy(val, &buf[offset - start], chunk); + } + + val += chunk; + offset += chunk; + bytes -= chunk; + } + + return 0; +} + +static struct nvmem_config jz4780_efuse_nvmem_config __initdata = { + .name = "jz4780-efuse", + .size = 1024, + .word_size = 1, + .stride = 1, + .owner = THIS_MODULE, + .reg_read = jz4780_efuse_read, +}; + +static const struct regmap_config jz4780_efuse_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = JZ_EFUDATA(7), +}; + +static int jz4780_efuse_probe(struct platform_device *pdev) +{ + struct nvmem_device *nvmem; + struct jz4780_efuse *efuse; + struct nvmem_config cfg; + unsigned long clk_rate; + struct device *dev = &pdev->dev; + void __iomem *regs; + + efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); + if (!efuse) + return -ENOMEM; + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + efuse->map = devm_regmap_init_mmio(dev, regs, + &jz4780_efuse_regmap_config); + if (IS_ERR(efuse->map)) + return PTR_ERR(efuse->map); + + efuse->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(efuse->clk)) + return PTR_ERR(efuse->clk); + + clk_rate = clk_get_rate(efuse->clk); + + efuse->dev = dev; + /* + * rd_adj and rd_strobe are 4 bit values + * bus clk period * (rd_adj + 1) > 6.5ns + * bus clk period * (rd_adj + 5 + rd_strobe) > 35ns + */ + efuse->rd_adj = (((6500 * (clk_rate / 1000000)) / 1000000) + 1) - 1; + efuse->rd_strobe = ((((35000 * (clk_rate / 1000000)) / 1000000) + 1) + - 5 - efuse->rd_adj); + + if (efuse->rd_adj > 0x1F || efuse->rd_strobe > 0x1F) { + dev_err(&pdev->dev, "Cannot set clock configuration\n"); + return -EINVAL; + } + + regmap_update_bits(efuse->map, JZ_EFUCFG, + (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) | + (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT), + (efuse->rd_adj << EFUCFG_RD_ADJ_SHIFT) | + (efuse->rd_strobe << EFUCFG_RD_STR_SHIFT)); + + cfg = jz4780_efuse_nvmem_config; + cfg.dev = &pdev->dev; + cfg.priv = efuse; + + nvmem = devm_nvmem_register(dev, &cfg); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); + + platform_set_drvdata(pdev, nvmem); + + return 0; +} + +static const struct of_device_id jz4780_efuse_match[] = { + { .compatible = "ingenic,jz4780-efuse" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, jz4780_efuse_match); + +static struct platform_driver jz4780_efuse_driver = { + .probe = jz4780_efuse_probe, + .driver = { + .name = "jz4780-efuse", + .of_match_table = jz4780_efuse_match, + }, +}; +module_platform_driver(jz4780_efuse_driver); + +MODULE_AUTHOR("PrasannaKumar Muralidharan "); +MODULE_AUTHOR("H. Nikolaus Schaller "); +MODULE_AUTHOR("Paul Cercueil "); +MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sat Feb 22 10:25:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11398041 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 15B53109A for ; Sat, 22 Feb 2020 10:26:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E974021D56 for ; Sat, 22 Feb 2020 10:26:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="W9+y84et" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727259AbgBVK0F (ORCPT ); Sat, 22 Feb 2020 05:26:05 -0500 Received: from mo4-p02-ob.smtp.rzone.de ([81.169.146.169]:32110 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727090AbgBVK0B (ORCPT ); Sat, 22 Feb 2020 05:26:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582367157; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=FSCakIJ7lik565E7xYsWBWIgKVoOYG25iccTR4ReXm8=; b=W9+y84etZ6JrAoUyuKFFfKbxmDlKEOSNtZMaMmALc4ZCDDeoUy+txu7fUk/HwW4Y8J iDCyH73ldHBh8IAxvvnaJYyB8lzHMHT6MIRMVe0vPsFBQV/UsBtO6YJg5tRu+6KaTr6U TPGrjWQQswWKnmviDo8sgo92wj4OdrvAEgneWONZyp+5jl2mAWgrUae1irOlxanqPo9A VFOO1nhbybGwcxFBhpEq704eDxbLZBxdXGME83JR74tLL6/5Q9j1/K/T3EHNIvbYm2Hu xnhuHkNczITSLVntzFXt4hICOtB1w4Nd++K/K/lik/wtn5gWl1ohz7m3ffisNeVmRAyX GKqw== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0pAz7pC6Q5M" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1MAPjjMb (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sat, 22 Feb 2020 11:25:45 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v5 2/6] Bindings: nvmem: add bindings for JZ4780 efuse Date: Sat, 22 Feb 2020 11:25:37 +0100 Message-Id: <51642368a064073ab99bb3110863b5fadc382f82.1582367141.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre Signed-off-by: H. Nikolaus Schaller [converted to yaml] Signed-off-by: Andreas Kemnade --- .../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..09a8ef937750 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic JZ EFUSE driver bindings + +maintainers: + - PrasannaKumar Muralidharan + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - ingenic,jz4780-efuse + + reg: + maxItems: 1 + + clocks: + # Handle for the ahb for the efuse. + maxItems: 1 + + clock-names: + items: + - const: ahb2 + +required: + - compatible + - reg + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0x2c>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "ahb2"; + }; + +... From patchwork Sat Feb 22 10:25:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11398039 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2181924 for ; Sat, 22 Feb 2020 10:26:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D02672071E for ; Sat, 22 Feb 2020 10:26:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="B+vjdYA+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727202AbgBVK0B (ORCPT ); Sat, 22 Feb 2020 05:26:01 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.175]:22896 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727134AbgBVK0B (ORCPT ); Sat, 22 Feb 2020 05:26:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582367158; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=Ay31G7exAkSbg3PL1nOzfK8qqlNf1gmdrl8NmheHFD8=; b=B+vjdYA+07jSSF76l0/K7VCEm0iRvbLG4wVPCFQbjJL9Souq2SkSHl0X8d3PBcnc1J RZTB1SDuxCnt+PDPFryFRST2fKOsRAQ1N9+W1iCQlOflH7MIOM0i9ocaxRYyrPYXAPtM MBnDtAJl6gQgmYeAMrv0T/GVDdypdJaGrwppTEo0NYkwwEa5ZA2PlyagqZRgHFJDnFf9 dpv7/zgebclUi9xpFmd6PvicRzXM5Fqlb3oZw5e7JDoLfdr9mSJZsV4v/IpGH8D2uj3F tbmueRYJtu2Jbw/qTG49+AiB4RXB7OXUqwEBDAdW8KzaQIrI6bxg0yo2jlJEtHPalzXf PAFg== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0pAz7pC6Q5M" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1MAPkjMc (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sat, 22 Feb 2020 11:25:46 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v5 3/6] Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI Date: Sat, 22 Feb 2020 11:25:38 +0100 Message-Id: <3ef965a3e7f135c51c150fbbb12917ce94d3e9dc.1582367141.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre --- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse diff --git a/Documentation/ABI/testing/sysfs-driver-jz4780-efuse b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file mode 100644 index 000000000000..bb6f5d6ceea0 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse @@ -0,0 +1,16 @@ +What: /sys/devices/*//nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan +Description: read-only access to the efuse on the Ingenic JZ4780 SoC + The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot key +Users: any user space application which wants to read the Chip + and Customer ID From patchwork Sat Feb 22 10:25:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11398047 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F5F6924 for ; Sat, 22 Feb 2020 10:26:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E294A2467E for ; Sat, 22 Feb 2020 10:26:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="g3Ldxpr+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727318AbgBVK0P (ORCPT ); Sat, 22 Feb 2020 05:26:15 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.175]:16448 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727100AbgBVK0B (ORCPT ); Sat, 22 Feb 2020 05:26:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582367157; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=UhK6kPx1izFEDwGPZRQ8Vz3EeWwMJdEuEzrh1rnL18s=; b=g3Ldxpr+Vf+GgTpIVu6HJWcbvZMrD4POZOedoFvAJgaopY3fMNa/ynn7zcrYMrlyen A4t9d9r5Y4tgwdA2LOa397ZQAPBTNrOwzx9gKeMbSZSN5fu2ebFGg33C44v9sxV+E7BN PlBuQSb8YirhEsRXXx/WBOpVeLpqKMeq40vXZrfZ+P132wAFHS0SGt4OKpyG1FyMWuuA C3rOSgwjmJGw2PUmnQsYDcBCot4XdVJ1haEh2H0MIkxL/NWTB55qtyS7lVxF4E6+p9Ly D2coNTWtwLuZ6m4iXL9VC9nkd2oY2ajSdXBOhbAkSm7wWKdCjSVkB0SSOKoOtW5DuKCI Gn2g== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0pAz7pC6Q5M" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1MAPkjMd (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sat, 22 Feb 2020 11:25:46 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v5 4/6] nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver Date: Sat, 22 Feb 2020 11:25:39 +0100 Message-Id: <2ccdf9e354e12a10cb5f5c6cda9f81065306471e.1582367141.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a0d86490c2c6..5bab216d8fe9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8270,6 +8270,11 @@ M: Zubair Lutfullah Kakakhel S: Maintained F: drivers/dma/dma-jz4780.c +INGENIC JZ4780 EFUSE Driver +M: PrasannaKumar Muralidharan +S: Maintained +F: drivers/nvmem/jz4780-efuse.c + INGENIC JZ4780 NAND DRIVER M: Harvey Hunt L: linux-mtd@lists.infradead.org From patchwork Sat Feb 22 10:25:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11398049 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B2E6D109A for ; Sat, 22 Feb 2020 10:26:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 91C2524676 for ; Sat, 22 Feb 2020 10:26:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="Gr3HjOMY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727304AbgBVK0P (ORCPT ); Sat, 22 Feb 2020 05:26:15 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.100]:11238 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727124AbgBVK0B (ORCPT ); Sat, 22 Feb 2020 05:26:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582367158; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=V1+Q4JesqWcFYmt/4rldi7rtX4QsYdV77esVgLGK1a4=; b=Gr3HjOMYR2wjg+I8qajMOSRxldcCJmwWve/0wTk0GoAIz0vRPBOjZKoCxOUqaU7XjX epUvCFCd9nuvptu65ttsmCrSJVn7qmJS/CKGURH9IeW55iMLVJsixoAlXRxxAmcbPY8W SCIvH50vsN2WlQDle9czv5WeMjyiPVN8WBI34eLAkpCN/Gs+iyDtJ/eqwhTkPY/cwR1A 5u4hQlpwVM35s8ke9NWlFiKzcFapy7XxFRbK4FKZRy6PL/CnJSTBpij95QxYFB38ekSr m3iy1YONRUgtKNx01yj+VnwG4RE755v2NwzHjKXec0m42aDV31gFGYWk1fLdUl3SaS/7 nrtA== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0pAz7pC6Q5M" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1MAPljMe (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sat, 22 Feb 2020 11:25:47 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v5 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse Date: Sat, 22 Feb 2020 11:25:40 +0100 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and the ethernet mac address for the davicom dm9000 chip on the CI20 board. It also changes the nemc reg range to avoid overlap. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre Signed-off-by: H. Nikolaus Schaller --- arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index f928329b034b..1e266be28096 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -358,7 +358,7 @@ nemc: nemc@13410000 { compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; + reg = <0x13410000 0x4c>; #address-cells = <2>; #size-cells = <1>; ranges = <1 0 0x1b000000 0x1000000 @@ -373,6 +373,21 @@ status = "disabled"; }; + efuse: efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0x2c>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + clock-names = "ahb2"; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_addr: eth-mac-addr@0x22 { + reg = <0x22 0x6>; + }; + }; + dma: dma@13420000 { compatible = "ingenic,jz4780-dma"; reg = <0x13420000 0x400 From patchwork Sat Feb 22 10:25:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11398037 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 745C4924 for ; Sat, 22 Feb 2020 10:26:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C080F214DB for ; Sat, 22 Feb 2020 10:26:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="N4w343kE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727166AbgBVK0B (ORCPT ); Sat, 22 Feb 2020 05:26:01 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.101]:16511 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726794AbgBVK0B (ORCPT ); Sat, 22 Feb 2020 05:26:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582367158; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=ex+tP/S3jJM/1n8mzovxtL99ooZIHpji+z8Ck9o3ixM=; b=N4w343kENoioT8Zh9eiIb/W69ahujIM+joZhXM2rLO1Z3gIiPlXsSCqYjJBKabLnlw h5GUKDQGQbpOtm8W83TEDMn8wgvVEReM3SMg1453tnRZTneVSh1NK2gxjxg05odniiot ivthAYIAd7SX7qWBwmxZwzTibZMtVdjJQVfG922muChI/CDFhDFyR4MKNexi1ryBAO3X OIpeL3KJMHlz9q4CWWujjE9Kx39GRXnhoWEz/E/ebwCsLldJRCNGEhGvjkKIp46cxKdh Zhuq2b2FOWxIko91F4IL2OhmEMlzT5wNAkhKMgME4zbdKUKC9YZTU47N/O0K0RaPUnt9 Vr8Q== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNOsPj0pAz7pC6Q5M" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.1.12 DYNA|AUTH) with ESMTPSA id U06217w1MAPljMg (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Sat, 22 Feb 2020 11:25:47 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v5 6/6] MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the default MAC address Date: Sat, 22 Feb 2020 11:25:41 +0100 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org There is a unique MAC address programmed into the eFuses of the JZ4780 chip in the CI20 factory. By using this for initializing the DM9000 Ethernet controller, every CI20 board has an individual - but stable - MAC address and DHCP can assign stable IP addresses. Signed-off-by: H. Nikolaus Schaller --- arch/mips/boot/dts/ingenic/ci20.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 37b93166bf22..6dc1f9eeff00 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -355,6 +355,9 @@ interrupt-parent = <&gpe>; interrupts = <19 4>; + + nvmem-cells = <ð0_addr>; + nvmem-cell-names = "mac-address"; }; };