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Thu, 27 Feb 2020 11:51:25 +0000 Received: from DOMINUS.corp.kimin.kr (1.214.196.86) by HK2PR02CA0191.apcprd02.prod.outlook.com (2603:1096:201:21::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.18 via Frontend Transport; Thu, 27 Feb 2020 11:51:24 +0000 From: Stephanos Ioannidis Subject: [PATCH v2 1/2] hw/core: Support device reset handler priority Thread-Topic: [PATCH v2 1/2] hw/core: Support device reset handler priority Thread-Index: AQHV7WQ98J8teEqi+0udzomYEWjImQ== Date: Thu, 27 Feb 2020 11:51:25 +0000 Message-ID: <20200227115005.66349-2-root@stephanos.io> References: <20200227115005.66349-1-root@stephanos.io> In-Reply-To: <20200227115005.66349-1-root@stephanos.io> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR02CA0191.apcprd02.prod.outlook.com (2603:1096:201:21::27) To SLXP216MB0285.KORP216.PROD.OUTLOOK.COM (2603:1096:100:9::8) x-mailer: git-send-email 2.17.1 authentication-results: spf=none (sender IP is ) smtp.mailfrom=root@stephanos.io; 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x-microsoft-antispam-message-info: sjbIqX5goeE2tH7EsNYLZz0JpIbZyYLiWrDSGV2/AcDLOBpbnse48NxxvoTriG5aNdEMbY8JaALO2eHIFFm1ogDXhv/OdJoyc6YjwLxsf9fpKDYhxeC+x+sxhZ6n0kfd91P79BR+0DTu6q8kAFlFuy10LU8Rf6Lmwi66eVPbJ+MDsvoXE7lDkskHVqCvYAa44HGTKFe0SdGmT97dUiidZCk9+IMaeJSZPznLHe8UvJEU5cnXw5xLD743qvfTDEFuQFkbBIHPodYaJkgLY6fAoGp3k+VBmltU0SSUcu8Xo3uQ5aY+A2ksxrOM10HwYG/iotIF2afC81GQGlShm8tv4de+b8ZSVqcvICoGMV/SmGqyDdZeAIg90P/GsYSs5fOfUsfwmBrqGddZJbQaJOxHq6ub6AAQEaL3W5WaaNuEV4rTN6qYI1xdRoTvW4UtcSGQtcqY+y37dNvcmbbNFvWj9RWZ2yYGwXKjMTBQjPIifkQgA0YkhnmNfUquVKa2jUgPOog6BO1xkJ4DU7nn+NEpBw== x-ms-exchange-antispam-messagedata: A1E3j0/pRd2tCVsHEDNwM+KFwCWM4L/vGH3pzFesaJX5Xsxz1uxj3NzL14N9y7UqFYuw/N83iEgUk1jBPPn4XaS5+tn+OjpFIymRatEDsTB7xm3mrmtfzHPZrphp+xjdVWsn24qKiQpDdMB4OtLfJw== MIME-Version: 1.0 X-OriginatorOrg: stephanos.io X-MS-Exchange-CrossTenant-Network-Message-Id: 50956d2d-a1de-4efe-017f-08d7bb7b5fb4 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Feb 2020 11:51:25.9477 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: c98113d8-f05d-4479-8605-bfc8e93dc16d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4A/Q+ZwYAYq+G3FJwpipVEPD0/fwj9sSFMdkK0HMavrq3zOn6KBgnVlQuOLL8nSYnEoCsPYY6lYGjsC6B87AOQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SLXP216MB0351 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.128.119 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephanos Ioannidis , "open list:All patches CC here" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The device reset handler invocation order is currently dependent on the order of handler registration, and this is less than ideal because there may exist dependencies among the handlers that require them to be invoked in a specific order. This commit adds the `priority` field to the reset entry struct and introduces the `qemu_register_reset_with_priority` function that implements descending-order insertion into the reset handler list based on the priority value, in order to allow the reset handler invocation order to be specified by the caller. Signed-off-by: Stephanos Ioannidis --- hw/core/reset.c | 32 ++++++++++++++++++++++++++++++-- include/sysemu/reset.h | 24 ++++++++++++++++++++++++ 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/hw/core/reset.c b/hw/core/reset.c index 9c477f2bf5..74f3677d96 100644 --- a/hw/core/reset.c +++ b/hw/core/reset.c @@ -31,6 +31,7 @@ typedef struct QEMUResetEntry { QTAILQ_ENTRY(QEMUResetEntry) entry; + uint16_t priority; QEMUResetHandler *func; void *opaque; } QEMUResetEntry; @@ -38,13 +39,40 @@ typedef struct QEMUResetEntry { static QTAILQ_HEAD(, QEMUResetEntry) reset_handlers = QTAILQ_HEAD_INITIALIZER(reset_handlers); -void qemu_register_reset(QEMUResetHandler *func, void *opaque) +void qemu_register_reset_with_priority(uint16_t priority, + QEMUResetHandler *func, void *opaque) { + /* Initialise reset entry */ QEMUResetEntry *re = g_malloc0(sizeof(QEMUResetEntry)); + re->priority = priority; re->func = func; re->opaque = opaque; - QTAILQ_INSERT_TAIL(&reset_handlers, re, entry); + + /* Insert sorted by priority into the reset entry list */ + if (QTAILQ_EMPTY(&reset_handlers) || + QTAILQ_LAST(&reset_handlers)->priority >= priority) + { + QTAILQ_INSERT_TAIL(&reset_handlers, re, entry); + } + else + { + QEMUResetEntry *cur = QTAILQ_LAST(&reset_handlers); + + while (QTAILQ_PREV(cur, entry) != NULL && + QTAILQ_PREV(cur, entry)->priority < priority) + { + cur = QTAILQ_PREV(cur, entry); + } + + QTAILQ_INSERT_BEFORE(cur, re, entry); + } +} + +void qemu_register_reset(QEMUResetHandler *func, void *opaque) +{ + qemu_register_reset_with_priority( + QEMU_RESET_PRIORITY_DEFAULT, func, opaque); } void qemu_unregister_reset(QEMUResetHandler *func, void *opaque) diff --git a/include/sysemu/reset.h b/include/sysemu/reset.h index 0b0d6d7598..39a0fe55f0 100644 --- a/include/sysemu/reset.h +++ b/include/sysemu/reset.h @@ -1,8 +1,32 @@ #ifndef QEMU_SYSEMU_RESET_H #define QEMU_SYSEMU_RESET_H +/* + * The device reset handlers are executed in descending order of their priority + * values (i.e. the reset handler with the greatest numerical priority value + * will be executed first). + */ +#define QEMU_RESET_PRIORITY_DEFAULT (0x8000) + +/* + * The priority level can range from -8 to +7, where the reset handler with the + * highest priority level is executed first. + */ +#define QEMU_RESET_PRIORITY_LEVEL(l) \ + (QEMU_RESET_PRIORITY_DEFAULT + (l * 0x1000)) + +/* + * Each priority level may be further divided into a maximum of 4096 sub-levels + * (0 to 4095). + */ +#define QEMU_RESET_PRIORITY_SUBLEVEL(l, s) \ + (QEMU_RESET_PRIORITY_DEFAULT + (l * 0x1000) + s) + typedef void QEMUResetHandler(void *opaque); +void qemu_register_reset_with_priority(uint16_t priority, + QEMUResetHandler *func, void *opaque); + void qemu_register_reset(QEMUResetHandler *func, void *opaque); void qemu_unregister_reset(QEMUResetHandler *func, void *opaque); void qemu_devices_reset(void); From patchwork Thu Feb 27 11:51:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephanos Ioannidis X-Patchwork-Id: 11408381 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4900A14BC for ; Thu, 27 Feb 2020 11:53:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F81C2468F for ; Thu, 27 Feb 2020 11:53:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=stephanosio.onmicrosoft.com header.i=@stephanosio.onmicrosoft.com header.b="Qs+d50mH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F81C2468F Authentication-Results: mail.kernel.org; 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Thu, 27 Feb 2020 11:51:28 +0000 Received: from DOMINUS.corp.kimin.kr (1.214.196.86) by HK2PR02CA0191.apcprd02.prod.outlook.com (2603:1096:201:21::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.18 via Frontend Transport; Thu, 27 Feb 2020 11:51:27 +0000 From: Stephanos Ioannidis Subject: [PATCH v2 2/2] hw/arm/armv7m: Downgrade CPU reset handler priority Thread-Topic: [PATCH v2 2/2] hw/arm/armv7m: Downgrade CPU reset handler priority Thread-Index: AQHV7WQ/RCF2oAiXBUCnUB+VwCKjkQ== Date: Thu, 27 Feb 2020 11:51:28 +0000 Message-ID: <20200227115005.66349-3-root@stephanos.io> References: <20200227115005.66349-1-root@stephanos.io> In-Reply-To: <20200227115005.66349-1-root@stephanos.io> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR02CA0191.apcprd02.prod.outlook.com (2603:1096:201:21::27) To SLXP216MB0285.KORP216.PROD.OUTLOOK.COM (2603:1096:100:9::8) x-mailer: git-send-email 2.17.1 authentication-results: spf=none (sender IP is ) smtp.mailfrom=root@stephanos.io; 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x-microsoft-antispam-message-info: l/xM858PiLrxabv6ZAFWlAdMA+vtNs/G70G7Mb/OSHPhRWkZd24qcgBB71+CKc2LbxBH3ewPAjVGZltVmOu9BL6l1F/WFSaGOnupG5TtytF+vfN4O103a48TPwH+annrM2DDI/vG/Z7VVEgXB+oN7bPHmTUWZFGYpcsD78+QcPO0ab1rWQ95yYFB8+HGnytW574uMKT+l9TP6KeWOnv+0RIFrbF41YmgH3pU2hkJtzwKKovUmUQYmEK6rpxO+YeyxGJGNBcmpt3jN5eLG5yw+ZBNVj7P+QYpiXopF/HoHsZWXaIPONpVEJLHZcSmFZo9lPOAr0DmxvEgoAL0JD/uwDf3TWgx0eiEbDW9lrpT9pZP+IdOmlwZSzPEIycdTmLEGD0oYgehfkooxiHhbPrDiNFwiL7NlkCnRB22skPIUXYh+5PvtcGN2xciKdinqSfQCS+BilJ/mzM81PDjCslQFK9OcRfVoXt7VKz9tjnTjCS6MRDOr//NhVELRs5UoGRIEm/nY+p2UHtALv2nwKuLpQ== x-ms-exchange-antispam-messagedata: btNrkfSqEB7iYePsevFIC2uVmKrULyHXhWdRHjjP7FPkfoP8U8b0i2KiuBzkfsyvssYLmm4PThqHWuTPrwDjTSlVJtVTnnT05xnFwX7tYDpT7huZCSsjsi4osDNPMD9Ic/xKtxjniTszH3kUVfqu6A== MIME-Version: 1.0 X-OriginatorOrg: stephanos.io X-MS-Exchange-CrossTenant-Network-Message-Id: 864a5210-f431-4280-e84d-08d7bb7b6170 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Feb 2020 11:51:28.8344 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: c98113d8-f05d-4479-8605-bfc8e93dc16d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lzMtDlS1r6ZXdFrEn70aQdMZl4PAN8OF8mM+53BHzzSCRpEDjH1YdI+cE2MwCtLxPKLZ1cNGXhlGgUHp0NDOVQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SLXP216MB0351 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.128.119 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:ARM TCG CPUs" , Stephanos Ioannidis , "open list:All patches CC here" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The ARMv7-M CPU reset handler, which loads the initial SP and PC register values from the vector table, is currently executed before the ROM reset handler (rom_reset), and this causes the devices that alias low memory region (e.g. STM32F405 that aliases the flash memory located at 0x8000000 to 0x0) to load an invalid reset vector of 0 when the kernel image is linked to be loaded at the high memory address. For instance, it is norm for the STM32F405 firmware ELF image to have the text and rodata sections linked at 0x8000000, as this facilitates proper image loading by the firmware burning utility, and the processor can execute in place from the high flash memory address region as well. In order to resolve this issue, this commit downgrades the ARMCPU reset handler invocation priority level to -1 such that it is always executed after the ROM reset handler, which has a priority level of 0. Signed-off-by: Stephanos Ioannidis --- hw/arm/armv7m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 7531b97ccd..8b7c4b12a6 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -352,7 +352,8 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) * way A-profile does it. Note that this means that every M profile * board must call this function! */ - qemu_register_reset(armv7m_reset, cpu); + qemu_register_reset_with_priority( + QEMU_RESET_PRIORITY_LEVEL(-1), armv7m_reset, cpu); } static Property bitband_properties[] = {