From patchwork Fri Sep 7 17:43:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 10620903 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C163115A6 for ; Sat, 29 Sep 2018 17:33:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A242B29F18 for ; Sat, 29 Sep 2018 17:33:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9129A29F1C; Sat, 29 Sep 2018 17:33:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=2.0 tests=BAYES_00,DATE_IN_PAST_96_XX, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D5BA729F18 for ; Sat, 29 Sep 2018 17:33:56 +0000 (UTC) Received: from localhost ([::1]:51733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6J7r-0007Bq-J7 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 29 Sep 2018 13:33:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6J6e-0005z7-WE for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g6J6b-0005kI-Rd for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:40 -0400 Received: from pio-pvt-msa1.bahnhof.se ([79.136.2.40]:39278) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g6J6b-0005jW-K4 for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:37 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTP id 409103F60E; Sat, 29 Sep 2018 19:32:35 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se X-Amavis-Alert: BAD HEADER SECTION, Non-encoded 8-bit data (char C3 hex): To: ...>, \n \tPhilippe Mathieu-Daud\303\203\302\251 Received: from pio-pvt-msa1.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa1.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zOuZW3e-DhSL; Sat, 29 Sep 2018 19:32:31 +0200 (CEST) Received: from localhost (h-155-4-135-114.NA.cust.bahnhof.se [155.4.135.114]) (Authenticated sender: mb547485) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTPA id 1EBC63F5BA; Sat, 29 Sep 2018 19:32:31 +0200 (CEST) X-Mailbox-Line: From ff4721b7a1049a96a054bd215542a8e6633ceafd Mon Sep 17 00:00:00 2001 Message-Id: In-Reply-To: References: From: Fredrik Noring Date: Fri, 7 Sep 2018 19:43:36 +0200 To: =?unknown-8bit?q?Aleksandar_Markovic_=3Camarkovic=40wavecomp=2Ecom=3E=2C?= =?unknown-8bit?q?_=22Maciej_W=2E_Rozycki=22_=3Cmacro=40linux-mips=2Eorg=3E?= =?unknown-8bit?q?=2C?= =?unknown-8bit?q?_Philippe_Mathieu-Daud=C3=A9_=3Cf4bug=40amsat=2Eorg=3E?= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.40 Subject: [Qemu-devel] [PATCH v6 1/7] target/mips: Define R5900 instructions and CPU preprocessor constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?unknown-8bit?q?Peter_Maydell_=3Cpeter=2Emaydell=40linaro=2Eorg=3E=2C_R?= =?unknown-8bit?q?ichard_Henderson_=3Crichard=2Ehenderson=40linaro=2Eorg=3E?= =?unknown-8bit?q?=2C_qemu-devel=40nongnu=2Eorg=2C_J=C3=BCrgen_Urban_=3CJuer?= =?unknown-8bit?q?genUrban=40gmx=2Ede=3E=2C_Petar_Jovanovic_=3Cpjovanovic=40?= =?unknown-8bit?q?wavecomp=2Ecom=3E=2C_Aurelien_Jarno_=3Caurelien=40aurel32?= =?unknown-8bit?q?=2Enet=3E?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The R5900 implements the 64-bit MIPS III instruction set except DMULT, DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV instructions MOVN, MOVZ and PREF are implemented. It has the R5900 specific three-operand instructions MADD, MADDU, MULT and MULTU as well as pipeline 1 versions MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1. A set of 93 128-bit multimedia instructions specific to the R5900 is also implemented. The Toshiba TX System RISC TX79 Core Architecture manual http://www.lukasz.dk/files/tx79architecture.pdf describes the C790 processor that is a follow-up to the R5900. There are a few notable differences in that the R5900 FPU - is not IEEE 754-1985 compliant, - does not implement double format, and - its machine code is nonstandard. Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index c8e99791ad..76550de2da 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -53,6 +53,7 @@ #define ASE_MSA 0x01000000 /* Chip specific instructions. */ +#define INSN_R5900 0x10000000 #define INSN_LOONGSON2E 0x20000000 #define INSN_LOONGSON2F 0x40000000 #define INSN_VR54XX 0x80000000 @@ -63,6 +64,7 @@ #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) +#define CPU_R5900 (CPU_MIPS3 | INSN_R5900) #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) From patchwork Sat Sep 15 09:25:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 10620907 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F026E15A6 for ; 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Sat, 29 Sep 2018 13:34:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6J6j-00062d-1E for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g6J6f-0005m9-SM for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:44 -0400 Received: from pio-pvt-msa3.bahnhof.se ([79.136.2.42]:35927) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g6J6f-0005lX-FY for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:41 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa3.bahnhof.se (Postfix) with ESMTP id 0BF503F952; Sat, 29 Sep 2018 19:32:40 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se X-Amavis-Alert: BAD HEADER SECTION, Non-encoded 8-bit data (char C3 hex): To: ...>, \n \tPhilippe Mathieu-Daud\303\203\302\251 Received: from pio-pvt-msa3.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa3.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cTF4JfJ7TW9f; Sat, 29 Sep 2018 19:32:33 +0200 (CEST) Received: from localhost (h-155-4-135-114.NA.cust.bahnhof.se [155.4.135.114]) (Authenticated sender: mb547485) by pio-pvt-msa3.bahnhof.se (Postfix) with ESMTPA id 7F6333F93B; Sat, 29 Sep 2018 19:32:33 +0200 (CEST) X-Mailbox-Line: From 7c1bbedaf6753f0a3906edf231503726197d2299 Mon Sep 17 00:00:00 2001 Message-Id: <7c1bbedaf6753f0a3906edf231503726197d2299.1538240994.git.noring@nocrew.org> In-Reply-To: References: From: Fredrik Noring Date: Sat, 15 Sep 2018 11:25:37 +0200 To: =?unknown-8bit?q?Aleksandar_Markovic_=3Camarkovic=40wavecomp=2Ecom=3E=2C?= =?unknown-8bit?q?_=22Maciej_W=2E_Rozycki=22_=3Cmacro=40linux-mips=2Eorg=3E?= =?unknown-8bit?q?=2C?= =?unknown-8bit?q?_Philippe_Mathieu-Daud=C3=A9_=3Cf4bug=40amsat=2Eorg=3E?= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.42 Subject: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?unknown-8bit?q?Peter_Maydell_=3Cpeter=2Emaydell=40linaro=2Eorg=3E=2C_R?= =?unknown-8bit?q?ichard_Henderson_=3Crichard=2Ehenderson=40linaro=2Eorg=3E?= =?unknown-8bit?q?=2C_qemu-devel=40nongnu=2Eorg=2C_J=C3=BCrgen_Urban_=3CJuer?= =?unknown-8bit?q?genUrban=40gmx=2Ede=3E=2C_Petar_Jovanovic_=3Cpjovanovic=40?= =?unknown-8bit?q?wavecomp=2Ecom=3E=2C_Aurelien_Jarno_=3Caurelien=40aurel32?= =?unknown-8bit?q?=2Enet=3E?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The three-operand MULT and MULTU are the only R5900 specific instructions emitted by GCC 7.3. The R5900 also implements the three- operand MADD and MADDU instructions, but they are omitted in QEMU for now since they are absent in programs compiled by current GCC versions. Likewise, the R5900 specific pipeline 1 instruction variants MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1 are omitted here as well. Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index ab16cdb911..7e18ec0d03 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3768,6 +3768,77 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); } +/* + * These MULT and MULTU instructions implemented in for example the + * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core + * architectures are special three-operand variants with the syntax + * + * MULT[U] rd, rs, rt + * + * such that + * + * (rd, LO, HI) <- rs * rt + * + * where the low-order 32-bits of the result is placed into both the + * GPR rd and the special register LO. The high-order 32-bits of the + * result is placed into the special register HI. + * + * If the GPR rd is omitted in assembly language, it is taken to be 0, + * which is the zero register that always reads as 0. + */ +static void gen_mul_txxx(DisasContext *ctx, uint32_t opc, + int acc, int rd, int rs, int rt) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + switch (opc) { + case OPC_MULT: + { + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_muls2_i32(t2, t3, t2, t3); + if (rd) { + tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); + } + tcg_gen_ext_i32_tl(cpu_LO[acc], t2); + tcg_gen_ext_i32_tl(cpu_HI[acc], t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + break; + case OPC_MULTU: + { + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_mulu2_i32(t2, t3, t2, t3); + if (rd) { + tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); + } + tcg_gen_ext_i32_tl(cpu_LO[acc], t2); + tcg_gen_ext_i32_tl(cpu_HI[acc], t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + break; + default: + MIPS_INVAL("mul R5900"); + generate_exception_end(ctx, EXCP_RI); + goto out; + } + + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { @@ -22378,6 +22449,8 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) check_insn(ctx, INSN_VR54XX); op1 = MASK_MUL_VR54XX(ctx->opcode); gen_mul_vr54xx(ctx, op1, rd, rs, rt); + } else if (ctx->insn_flags & INSN_R5900) { + gen_mul_txxx(ctx, op1, 0, rd, rs, rt); } else { gen_muldiv(ctx, op1, rd & 3, rs, rt); } From patchwork Sat Sep 15 08:43:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 10620913 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 65DD3A6A for ; Sat, 29 Sep 2018 17:38:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9240529D8D for ; Sat, 29 Sep 2018 17:38:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 82EC829D92; Sat, 29 Sep 2018 17:38:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=2.0 tests=BAYES_00,DATE_IN_PAST_96_XX, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2C00929D8D for ; Sat, 29 Sep 2018 17:38:13 +0000 (UTC) Received: from localhost ([::1]:51755 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6JC0-00028Y-JH for patchwork-qemu-devel@patchwork.kernel.org; Sat, 29 Sep 2018 13:38:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6J6t-0006XW-Tr for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g6J6o-00067d-K6 for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:53 -0400 Received: from pio-pvt-msa2.bahnhof.se ([79.136.2.41]:42898) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g6J6o-00066D-C6 for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:50 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTP id 4310F3F996; Sat, 29 Sep 2018 19:32:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se X-Amavis-Alert: BAD HEADER SECTION, Non-encoded 8-bit data (char C3 hex): To: ...>, \n \tPhilippe Mathieu-Daud\303\203\302\251 Received: from pio-pvt-msa2.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa2.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id u4WfWlYDwmYu; Sat, 29 Sep 2018 19:32:36 +0200 (CEST) Received: from localhost (h-155-4-135-114.NA.cust.bahnhof.se [155.4.135.114]) (Authenticated sender: mb547485) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTPA id DA4763F990; Sat, 29 Sep 2018 19:32:35 +0200 (CEST) X-Mailbox-Line: From 92d6ae7a3fd87b96b141f0fcc32fd933db5515d7 Mon Sep 17 00:00:00 2001 Message-Id: <92d6ae7a3fd87b96b141f0fcc32fd933db5515d7.1538240994.git.noring@nocrew.org> In-Reply-To: References: From: Fredrik Noring Date: Sat, 15 Sep 2018 10:43:26 +0200 To: =?unknown-8bit?q?Aleksandar_Markovic_=3Camarkovic=40wavecomp=2Ecom=3E=2C?= =?unknown-8bit?q?_=22Maciej_W=2E_Rozycki=22_=3Cmacro=40linux-mips=2Eorg=3E?= =?unknown-8bit?q?=2C?= =?unknown-8bit?q?_Philippe_Mathieu-Daud=C3=A9_=3Cf4bug=40amsat=2Eorg=3E?= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.41 Subject: [Qemu-devel] [PATCH v6 3/7] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?unknown-8bit?q?Peter_Maydell_=3Cpeter=2Emaydell=40linaro=2Eorg=3E=2C_R?= =?unknown-8bit?q?ichard_Henderson_=3Crichard=2Ehenderson=40linaro=2Eorg=3E?= =?unknown-8bit?q?=2C_qemu-devel=40nongnu=2Eorg=2C_J=C3=BCrgen_Urban_=3CJuer?= =?unknown-8bit?q?genUrban=40gmx=2Ede=3E=2C_Petar_Jovanovic_=3Cpjovanovic=40?= =?unknown-8bit?q?wavecomp=2Ecom=3E=2C_Aurelien_Jarno_=3Caurelien=40aurel32?= =?unknown-8bit?q?=2Enet=3E?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The R5900 is taken to be MIPS III with certain modifications. From MIPS IV it implements the instructions MOVN, MOVZ and PREF. Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 7e18ec0d03..0c445c11c5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -22422,7 +22422,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MOVN: /* Conditional move */ case OPC_MOVZ: check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | - INSN_LOONGSON2E | INSN_LOONGSON2F); + INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900); gen_cond_move(ctx, op1, rd, rs, rt); break; case OPC_MFHI: /* Move from HI/LO */ @@ -25006,7 +25006,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; case OPC_PREF: check_insn_opc_removed(ctx, ISA_MIPS32R6); - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | + INSN_R5900); /* Treat as NOP. */ break; From patchwork Sun Sep 16 15:13:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 10620911 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B94C6A6A for ; Sat, 29 Sep 2018 17:36:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A12AC29DE4 for ; Sat, 29 Sep 2018 17:36:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 94CAE29F18; Sat, 29 Sep 2018 17:36:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=2.0 tests=BAYES_00,DATE_IN_PAST_96_XX, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3350F29DE4 for ; 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Sat, 29 Sep 2018 19:32:38 +0200 (CEST) Received: from localhost (h-155-4-135-114.NA.cust.bahnhof.se [155.4.135.114]) (Authenticated sender: mb547485) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTPA id 49CEB3F5BA; Sat, 29 Sep 2018 19:32:38 +0200 (CEST) X-Mailbox-Line: From a866348933883001fbd64b3b41ff7d29717c00b6 Mon Sep 17 00:00:00 2001 Message-Id: In-Reply-To: References: From: Fredrik Noring Date: Sun, 16 Sep 2018 17:13:03 +0200 To: =?unknown-8bit?q?Aleksandar_Markovic_=3Camarkovic=40wavecomp=2Ecom=3E=2C?= =?unknown-8bit?q?_=22Maciej_W=2E_Rozycki=22_=3Cmacro=40linux-mips=2Eorg=3E?= =?unknown-8bit?q?=2C?= =?unknown-8bit?q?_Philippe_Mathieu-Daud=C3=A9_=3Cf4bug=40amsat=2Eorg=3E?= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.40 Subject: [Qemu-devel] [PATCH v6 4/7] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?unknown-8bit?q?Peter_Maydell_=3Cpeter=2Emaydell=40linaro=2Eorg=3E=2C_R?= =?unknown-8bit?q?ichard_Henderson_=3Crichard=2Ehenderson=40linaro=2Eorg=3E?= =?unknown-8bit?q?=2C_qemu-devel=40nongnu=2Eorg=2C_J=C3=BCrgen_Urban_=3CJuer?= =?unknown-8bit?q?genUrban=40gmx=2Ede=3E=2C_Petar_Jovanovic_=3Cpjovanovic=40?= =?unknown-8bit?q?wavecomp=2Ecom=3E=2C_Aurelien_Jarno_=3Caurelien=40aurel32?= =?unknown-8bit?q?=2Enet=3E?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The Linux kernel traps certain reserved instruction exceptions to emulate the corresponding instructions. QEMU is the kernel in user mode, so those traps are emulated by accepting the instructions. This change adds the function check_insn_opc_user_only to signal a reserved instruction exception for flagged CPUs in QEMU system mode. The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not implemented in R5900 hardware. They are trapped and emulated by the Linux kernel and, accordingly, therefore QEMU user only instructions. Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 0c445c11c5..5a5021fe36 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1887,6 +1887,21 @@ static inline void check_insn_opc_removed(DisasContext *ctx, int flags) } } +/* + * The Linux kernel traps certain reserved instruction exceptions to + * emulate the corresponding instructions. QEMU is the kernel in user + * mode, so those traps are emulated by accepting the instructions. + * + * A reserved instruction exception is generated for flagged CPUs if + * QEMU runs in system mode. + */ +static inline void check_insn_opc_user_only(DisasContext *ctx, int flags) +{ +#ifndef CONFIG_USER_ONLY + check_insn_opc_removed(ctx, flags); +#endif +} + /* This code generates a "reserved instruction" exception if the CPU does not support 64-bit paired-single (PS) floating point data type */ static inline void check_ps(DisasContext *ctx) @@ -22465,6 +22480,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_DDIV: case OPC_DDIVU: check_insn(ctx, ISA_MIPS3); + check_insn_opc_user_only(ctx, INSN_R5900); check_mips_64(ctx); gen_muldiv(ctx, op1, 0, rs, rt); break; @@ -24968,6 +24984,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; case OPC_LL: /* Load and stores */ check_insn(ctx, ISA_MIPS2); + check_insn_opc_user_only(ctx, INSN_R5900); /* Fallthrough */ case OPC_LWL: case OPC_LWR: @@ -24993,6 +25010,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) case OPC_SC: check_insn(ctx, ISA_MIPS2); check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_user_only(ctx, INSN_R5900); gen_st_cond(ctx, op, rt, rs, imm); break; case OPC_CACHE: @@ -25259,9 +25277,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) #if defined(TARGET_MIPS64) /* MIPS64 opcodes */ + case OPC_LLD: + check_insn_opc_user_only(ctx, INSN_R5900); + /* fall through */ case OPC_LDL: case OPC_LDR: - case OPC_LLD: check_insn_opc_removed(ctx, ISA_MIPS32R6); /* fall through */ case OPC_LWU: @@ -25282,6 +25302,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) case OPC_SCD: check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn(ctx, ISA_MIPS3); + check_insn_opc_user_only(ctx, INSN_R5900); check_mips_64(ctx); gen_st_cond(ctx, op, rt, rs, imm); break; From patchwork Sat Sep 15 09:50:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 10620909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96DCCA6A for ; Sat, 29 Sep 2018 17:36:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71EDB29DE4 for ; Sat, 29 Sep 2018 17:36:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6230829F18; Sat, 29 Sep 2018 17:36:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=2.0 tests=BAYES_00,DATE_IN_PAST_96_XX, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A79F129DE4 for ; Sat, 29 Sep 2018 17:36:25 +0000 (UTC) Received: from localhost ([::1]:51749 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6JAG-0000ME-T6 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 29 Sep 2018 13:36:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59274) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6J6n-0006D4-RH for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g6J6k-0005us-LN for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:49 -0400 Received: from pio-pvt-msa1.bahnhof.se ([79.136.2.40]:39296) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g6J6k-0005u2-9K for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:46 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTP id D387F3F5BA; Sat, 29 Sep 2018 19:32:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se X-Amavis-Alert: BAD HEADER SECTION, Non-encoded 8-bit data (char C3 hex): To: ..., \n \tPhilippe Mathieu-Daud\303\203\302\251 In-Reply-To: References: From: Fredrik Noring Date: Sat, 15 Sep 2018 11:50:32 +0200 To: =?unknown-8bit?q?Aleksandar_Markovic_=3Camarkovic=40wavecomp=2Ecom=3E=2C?= =?unknown-8bit?q?_=22Maciej_W=2E_Rozycki=22_=3Cmacro=40linux-mips=2Eorg=3E?= =?unknown-8bit?q?=2C?= =?unknown-8bit?q?_Philippe_Mathieu-Daud=C3=A9_=3Cf4bug=40amsat=2Eorg=3E=2C?= =?unknown-8bit?q?_Laurent_Vivier_=3Claurent=40vivier=2Eeu=3E?= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.40 Subject: [Qemu-devel] [PATCH v6 5/7] target/mips: Define the R5900 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?unknown-8bit?q?Peter_Maydell_=3Cpeter=2Emaydell=40linaro=2Eorg=3E=2C_R?= =?unknown-8bit?q?ichard_Henderson_=3Crichard=2Ehenderson=40linaro=2Eorg=3E?= =?unknown-8bit?q?=2C_qemu-devel=40nongnu=2Eorg=2C_J=C3=BCrgen_Urban_=3CJuer?= =?unknown-8bit?q?genUrban=40gmx=2Ede=3E=2C_Petar_Jovanovic_=3Cpjovanovic=40?= =?unknown-8bit?q?wavecomp=2Ecom=3E=2C_Aurelien_Jarno_=3Caurelien=40aurel32?= =?unknown-8bit?q?=2Enet=3E?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The primary purpose of this change is to support programs compiled by GCC for the R5900 target and thereby run R5900 Linux distributions, for example Gentoo. GCC in version 7.3, by itself, by inspection of the GCC source code and inspection of the generated machine code, for the R5900 target, only emits two instructions that are specific to the R5900: the three- operand MULT and MULTU. GCC and libc also emit certain MIPS III instructions that are not part of the R5900 ISA. They are normally trapped and emulated by the Linux kernel, and therefore need to be treated accordingly by QEMU. A program compiled by GCC is taken to mean source code compiled by GCC under the restrictions above. One can, with the apparent limitations, with a bit of effort obtain a fully functioning operating system such as R5900 Gentoo. Strictly speaking, programs need not be compiled by GCC to make use of this change. Instructions and other facilities of the R5900 not implemented by this change are intended to signal provisional exceptions. One such example is the FPU that is not compliant with IEEE 754-1985 in system mode. It is therefore provisionally disabled. In user space the FPU is trapped and emulated by IEEE 754-1985 compliant software in the kernel, and this is handled accordingly by QEMU. Another example is the 93 multimedia instructions specific to the R5900 that generate provisional reserved instruction exception signals. One of the benefits of running a Linux distribution under QEMU is that programs can be compiled with a native compiler, where the host and target are the same, as opposed to a cross-compiler, where they are not the same. This is especially important in cases where the target hardware does not have the resources to run a native compiler. Problems with cross-compilation are often related to host and target differences in integer sizes, pointer sizes, endianness, machine code, ABI, etc. Sometimes cross-compilation is not even supported by the build script for a given package. One effective way to avoid those problems is to replace the cross-compiler with a native compiler. This change of compilation methods does not resolve the inherent problems with cross-compilation. The native compiler naturally replaces the cross-compiler, because one typically uses one or the other, and preferably the native compiler when the circumstances admit this. The native compiler is also a good test case for the R5900 QEMU user mode. Additionally, Gentoo is well- known for compiling and installing its packages from sources. This change has been tested with Gentoo compiled for R5900, including native compilation of several packages under QEMU. Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daudé --- target/mips/translate_init.inc.c | 59 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index b3320b9dc7..b5dacf4ffe 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -410,6 +410,65 @@ const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32R5 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, + { + /* + * The Toshiba TX System RISC TX79 Core Architecture manual + * + * http://www.lukasz.dk/files/tx79architecture.pdf + * + * describes the C790 processor that is a follow-up to the R5900. + * There are a few notable differences in that the R5900 FPU + * + * - is not IEEE 754-1985 compliant, + * - does not implement double format, and + * - its machine code is nonstandard. + */ + .name = "R5900", + .CP0_PRid = 0x00002E00, + /* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */ + .CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0), + .CP0_Status_rw_bitmask = 0xF4C79C1F, +#ifdef CONFIG_USER_ONLY + /* + * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC + * emulation. For user only, QEMU is the kernel, so we emulate the traps + * by simply emulating the instructions directly. + * + * Note: Config1 is only used internally, the R5900 has only Config0. + */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, + .CP0_LLAddr_shift = 4, + .CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0x0183FFFF, +#else + /* + * The R5900 COP1 FPU implements single-precision floating-point + * operations but is not entirely IEEE 754-1985 compatible. In + * particular, + * + * - NaN (not a number) and +/- infinities are not supported; + * - exception mechanisms are not fully supported; + * - denormalized numbers are not supported; + * - rounding towards nearest and +/- infinities are not supported; + * - computed results usually differs in the least significant bit; + * - saturations can differ more than the least significant bit. + * + * Since only rounding towards zero is supported, the two least + * significant bits of FCR31 are hardwired to 01. + * + * FPU emulation is disabled here until it is implemented. + * + * Note: Config1 is only used internally, the R5900 has only Config0. + */ + .CP0_Config1 = (47 << CP0C1_MMU), +#endif /* !CONFIG_USER_ONLY */ + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_R5900, + .mmu_type = MMU_TYPE_R4000, + }, { /* A generic CPU supporting MIPS32 Release 6 ISA. FIXME: Support IEEE 754-2008 FP. From patchwork Sat Sep 15 09:08:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 10620919 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C5CE315E8 for ; Sat, 29 Sep 2018 17:41:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF94B29E2D for ; Sat, 29 Sep 2018 17:41:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A287229E35; Sat, 29 Sep 2018 17:41:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=2.0 tests=BAYES_00,DATE_IN_PAST_96_XX, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 433BB29E2D for ; Sat, 29 Sep 2018 17:41:00 +0000 (UTC) Received: from localhost ([::1]:51769 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6JEh-0003ZW-Mb for patchwork-qemu-devel@patchwork.kernel.org; Sat, 29 Sep 2018 13:40:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59316) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6J73-0006ek-78 for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:33:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g6J70-0006EX-2I for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:33:05 -0400 Received: from pio-pvt-msa2.bahnhof.se ([79.136.2.41]:42909) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g6J6z-0006Dx-QI for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:33:01 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTP id AA4783F990; Sat, 29 Sep 2018 19:32:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se X-Amavis-Alert: BAD HEADER SECTION, Non-encoded 8-bit data (char C3 hex): To: ...>, \n \tPhilippe Mathieu-Daud\303\203\302\251 Received: from pio-pvt-msa2.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa2.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xKxsZZRDexgF; Sat, 29 Sep 2018 19:32:43 +0200 (CEST) Received: from localhost (h-155-4-135-114.NA.cust.bahnhof.se [155.4.135.114]) (Authenticated sender: mb547485) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTPA id 27C723F988; Sat, 29 Sep 2018 19:32:43 +0200 (CEST) X-Mailbox-Line: From f76eac5d801c6d7149da4ef84cade5e1caa4792c Mon Sep 17 00:00:00 2001 Message-Id: In-Reply-To: References: From: Fredrik Noring Date: Sat, 15 Sep 2018 11:08:54 +0200 To: =?unknown-8bit?q?Aleksandar_Markovic_=3Camarkovic=40wavecomp=2Ecom=3E=2C?= =?unknown-8bit?q?_=22Maciej_W=2E_Rozycki=22_=3Cmacro=40linux-mips=2Eorg=3E?= =?unknown-8bit?q?=2C?= =?unknown-8bit?q?_Philippe_Mathieu-Daud=C3=A9_=3Cf4bug=40amsat=2Eorg=3E?= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.41 Subject: [Qemu-devel] [PATCH v6 6/7] linux-user/mips: Recognise the R5900 CPU model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?unknown-8bit?q?Peter_Maydell_=3Cpeter=2Emaydell=40linaro=2Eorg=3E=2C_R?= =?unknown-8bit?q?ichard_Henderson_=3Crichard=2Ehenderson=40linaro=2Eorg=3E?= =?unknown-8bit?q?=2C_qemu-devel=40nongnu=2Eorg=2C_J=C3=BCrgen_Urban_=3CJuer?= =?unknown-8bit?q?genUrban=40gmx=2Ede=3E=2C_Petar_Jovanovic_=3Cpjovanovic=40?= =?unknown-8bit?q?wavecomp=2Ecom=3E=2C_Aurelien_Jarno_=3Caurelien=40aurel32?= =?unknown-8bit?q?=2Enet=3E?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This kind of ELF for the R5900 relies on an IEEE 754-1985 compliant FPU. The R5900 FPU hardware is noncompliant and it is therefore emulated in software by the Linux kernel. QEMU emulates a compliant FPU accordingly. Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daudé --- linux-user/mips/target_elf.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/mips/target_elf.h b/linux-user/mips/target_elf.h index fa5d30bf99..a98c9bd6ad 100644 --- a/linux-user/mips/target_elf.h +++ b/linux-user/mips/target_elf.h @@ -12,6 +12,9 @@ static inline const char *cpu_get_model(uint32_t eflags) if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6) { return "mips32r6-generic"; } + if ((eflags & EF_MIPS_MACH) == EF_MIPS_MACH_5900) { + return "R5900"; + } return "24Kf"; } #endif From patchwork Sat Sep 15 10:28:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 10620917 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 637C5112B for ; Sat, 29 Sep 2018 17:39:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D59B29E2D for ; Sat, 29 Sep 2018 17:39:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41BF629E35; Sat, 29 Sep 2018 17:39:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=2.0 tests=BAYES_00,DATE_IN_PAST_96_XX, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 87C9329E2D for ; Sat, 29 Sep 2018 17:39:44 +0000 (UTC) Received: from localhost ([::1]:51761 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6JDT-0002uh-BE for patchwork-qemu-devel@patchwork.kernel.org; Sat, 29 Sep 2018 13:39:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6J73-0006ej-79 for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:33:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g6J70-0006Ij-R4 for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:33:05 -0400 Received: from pio-pvt-msa2.bahnhof.se ([79.136.2.41]:42931) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g6J70-0006EF-Ib for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:33:02 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTP id 8313E3F988; Sat, 29 Sep 2018 19:32:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se X-Amavis-Alert: BAD HEADER SECTION, Non-encoded 8-bit data (char C3 hex): To: ...>, \n \tPhilippe Mathieu-Daud\303\203\302\251 Received: from pio-pvt-msa2.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa2.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id b_tWVjbBs7MI; Sat, 29 Sep 2018 19:32:45 +0200 (CEST) Received: from localhost (h-155-4-135-114.NA.cust.bahnhof.se [155.4.135.114]) (Authenticated sender: mb547485) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTPA id 77CB73F991; Sat, 29 Sep 2018 19:32:45 +0200 (CEST) X-Mailbox-Line: From 720b8bd87e943547bcc4b70d20889f99a67420b5 Mon Sep 17 00:00:00 2001 Message-Id: <720b8bd87e943547bcc4b70d20889f99a67420b5.1538240994.git.noring@nocrew.org> In-Reply-To: References: From: Fredrik Noring Date: Sat, 15 Sep 2018 12:28:05 +0200 To: =?unknown-8bit?q?Aleksandar_Markovic_=3Camarkovic=40wavecomp=2Ecom=3E=2C?= =?unknown-8bit?q?_=22Maciej_W=2E_Rozycki=22_=3Cmacro=40linux-mips=2Eorg=3E?= =?unknown-8bit?q?=2C?= =?unknown-8bit?q?_Philippe_Mathieu-Daud=C3=A9_=3Cf4bug=40amsat=2Eorg=3E?= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.41 Subject: [Qemu-devel] [PATCH v6 7/7] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?unknown-8bit?q?Peter_Maydell_=3Cpeter=2Emaydell=40linaro=2Eorg=3E=2C_R?= =?unknown-8bit?q?ichard_Henderson_=3Crichard=2Ehenderson=40linaro=2Eorg=3E?= =?unknown-8bit?q?=2C_qemu-devel=40nongnu=2Eorg=2C_J=C3=BCrgen_Urban_=3CJuer?= =?unknown-8bit?q?genUrban=40gmx=2Ede=3E=2C_Petar_Jovanovic_=3Cpjovanovic=40?= =?unknown-8bit?q?wavecomp=2Ecom=3E=2C_Aurelien_Jarno_=3Caurelien=40aurel32?= =?unknown-8bit?q?=2Enet=3E?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Sources [1][2] indicate that the Emotion Engine was designed by Toshiba and licensed to Sony. Others [3][4][5] claim it was a joint effort. It therefore makes sense to refer to the CPU as "Toshiba/Sony R5900". [1] http://cs.nyu.edu/courses/spring02/V22.0480-002/projects/aldrich/emotionengine.ppt [2] http://archive.arstechnica.com/reviews/1q00/playstation2/m-ee-3.html [3] http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/emotionengine%20(mpr).pdf [4] http://www.eetimes.com/document.asp?doc_id=1144055 [5] https://www.toshiba.co.jp/about/press/2001_09/pr2701.htm Reported-by: Maciej W. Rozycki Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daudé --- include/elf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/elf.h b/include/elf.h index 312f68af81..2510fc7be4 100644 --- a/include/elf.h +++ b/include/elf.h @@ -76,7 +76,7 @@ typedef int64_t Elf64_Sxword; #define EF_MIPS_MACH_OCTEON2 0x008d0000 /* Cavium Networks Octeon2 */ #define EF_MIPS_MACH_OCTEON3 0x008e0000 /* Cavium Networks Octeon3 */ #define EF_MIPS_MACH_5400 0x00910000 /* NEC VR5400 */ -#define EF_MIPS_MACH_5900 0x00920000 /* MIPS R5900 */ +#define EF_MIPS_MACH_5900 0x00920000 /* Toshiba/Sony R5900 */ #define EF_MIPS_MACH_5500 0x00980000 /* NEC VR5500 */ #define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra's RM9000 */ #define EF_MIPS_MACH_LS2E 0x00a00000 /* ST Microelectronics Loongson 2E */