From patchwork Sat Sep 29 20:34:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 10621005 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A60C16B1 for ; Sat, 29 Sep 2018 20:35:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F3AD629C59 for ; Sat, 29 Sep 2018 20:35:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E568329C99; Sat, 29 Sep 2018 20:35:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 765D429C59 for ; Sat, 29 Sep 2018 20:35:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727746AbeI3DEx (ORCPT ); Sat, 29 Sep 2018 23:04:53 -0400 Received: from simcoe208srvr.owm.bell.net ([184.150.200.208]:35697 "EHLO torfep02.bell.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727744AbeI3DEx (ORCPT ); Sat, 29 Sep 2018 23:04:53 -0400 Received: from bell.net torfep02 184.150.200.158 by torfep02.bell.net with ESMTP id <20180929203502.QPNN23720.torfep02.bell.net@torspm02.bell.net> for ; Sat, 29 Sep 2018 16:35:02 -0400 Received: from mx3210.localdomain ([70.53.62.196]) by torspm02.bell.net with ESMTP id <20180929203502.FJNH19016.torspm02.bell.net@mx3210.localdomain>; Sat, 29 Sep 2018 16:35:02 -0400 Received: by mx3210.localdomain (Postfix, from userid 1000) id C09AF2200ED; Sat, 29 Sep 2018 16:35:00 -0400 (EDT) Date: Sat, 29 Sep 2018 16:34:59 -0400 From: John David Anglin To: linux-parisc@vger.kernel.org Cc: deller@gmx.de, James.Bottomley@HansenPartnership.com Subject: [PATCH v3] parisc: Remove PTE load and fault check from L2_ptep macro Message-ID: <20180929203459.GA6371@mx3210.localdomain> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-Cloudmark-Analysis: v=2.2 cv=GK/nKqFK c=1 sm=0 tr=0 a=Zvhif4XNTjWcJyJCfFIh1A==:17 a=JBFolyDoGHsA:10 a=FBHGMhGWAAAA:8 a=X_kleiPrgWBBkIDFCHIA:9 a=CjuIK1q_8ugA:10 a=8fia1xhq9Guoo-auPtgA:9 a=ONNS8QRKHyMA:10 a=9gvnlMMaQFpL9xblJ6ne:22 Sender: linux-parisc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change removes the PTE load and present check from the L2_ptep macro. The load and check for kernel pages is now done in the tlb_lock macro. This avoids a double load and check for user pages. The load and check for user pages is now done inside the lock so the fault handler can't be called while the entry is being updated. This version uses an ordered store to release the lock when the page table entry isn't present. It also corrects the check in the non SMP case. Signed-off-by: John David Anglin diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index 242c5ab65611..e5977187dee7 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -431,8 +431,6 @@ extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */ shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */ - LDREG %r0(\pmd),\pte - bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault .endm /* Look up PTE in a 3-Level scheme. @@ -463,7 +461,7 @@ L2_ptep \pgd,\pte,\index,\va,\fault .endm - /* Acquire pa_tlb_lock lock and recheck page is still present. */ + /* Acquire pa_tlb_lock lock and check page is present. */ .macro tlb_lock spc,ptp,pte,tmp,tmp1,fault #ifdef CONFIG_SMP cmpib,COND(=),n 0,\spc,2f @@ -472,11 +470,13 @@ cmpib,COND(=) 0,\tmp1,1b nop LDREG 0(\ptp),\pte - bb,<,n \pte,_PAGE_PRESENT_BIT,2f + bb,<,n \pte,_PAGE_PRESENT_BIT,3f b \fault - stw \spc,0(\tmp) -2: + stw,ma \spc,0(\tmp) #endif +2: LDREG 0(\ptp),\pte + bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault +3: .endm /* Release pa_tlb_lock lock without reloading lock address. */