From patchwork Fri Jul 27 14:11:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Bartminski, Jakub" X-Patchwork-Id: 10547219 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 00E9714E0 for ; Fri, 27 Jul 2018 14:12:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E45722BCA6 for ; Fri, 27 Jul 2018 14:12:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D87852BCB6; Fri, 27 Jul 2018 14:12:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6A5DE2BCA6 for ; Fri, 27 Jul 2018 14:12:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D139D6EAC1; Fri, 27 Jul 2018 14:12:27 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97F466EABE for ; Fri, 27 Jul 2018 14:12:26 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jul 2018 07:12:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,409,1526367600"; d="scan'208";a="219631451" Received: from jbartmin-desk.igk.intel.com ([172.28.181.141]) by orsmga004.jf.intel.com with ESMTP; 27 Jul 2018 07:12:23 -0700 From: =?utf-8?q?Jakub_Bartmi=C5=84ski?= To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Jul 2018 16:11:43 +0200 Message-Id: <20180727141148.30874-1-jakub.bartminski@intel.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP It would appear that the calculated GuC pin bias was larger than it should be, as the GuC address space does NOT contain the "HW contexts RSVD" part of the WOPCM. Thus, the GuC pin bias is simply the GuC WOPCM size. v5: Clarify the diagram to better represent the GuC address space. Since we now don't use guc.base for the pin bias there's no need to validate it. It also has already been verified in WOPCM init. Bspec: 1180 Signed-off-by: Jakub Bartmiński Cc: Chris Wilson Cc: Michał Winiarski Cc: Michal Wajdeczko Reviewed-by: Michał Winiarski Reviewed-by: Michal Wajdeczko --- drivers/gpu/drm/i915/intel_guc.c | 49 +++++++++++++------------------- 1 file changed, 20 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 97460982985c..deb6a2053eaf 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -585,50 +585,41 @@ int intel_guc_resume(struct intel_guc *guc) * * :: * - * +==============> +====================+ <== GUC_GGTT_TOP - * ^ | | - * | | | - * | | DRAM | - * | | Memory | - * | | | - * GuC | | - * Address +========> +====================+ <== WOPCM Top - * Space ^ | HW contexts RSVD | - * | | | WOPCM | - * | | +==> +--------------------+ <== GuC WOPCM Top - * | GuC ^ | | - * | GGTT | | | - * | Pin GuC | GuC | - * | Bias WOPCM | WOPCM | - * | | Size | | - * | | | | | - * v v v | | - * +=====+=====+==> +====================+ <== GuC WOPCM Base - * | Non-GuC WOPCM | - * | (HuC/Reserved) | - * +====================+ <== WOPCM Base + * +===========> +====================+ <== FFFF_FFFF + * ^ | Reserved | + * | +====================+ <== GUC_GGTT_TOP + * | | | + * | | DRAM | + * GuC | | + * Address +===> +====================+ <== GuC ggtt_pin_bias + * Space ^ | | + * | | | | + * | GuC | GuC | + * | WOPCM | WOPCM | + * | Size | | + * | | | | + * v v | | + * +=======+===> +====================+ <== 0000_0000 * - * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM + * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped - * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and - * actual GuC WOPCM size. + * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size. */ /** * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value. * @guc: intel_guc structure. * - * This function will calculate and initialize the ggtt_pin_bias value based on - * overall WOPCM size and GuC WOPCM size. + * This function will calculate and initialize the ggtt_pin_bias value + * based on the GuC WOPCM size. */ static void guc_init_ggtt_pin_bias(struct intel_guc *guc) { struct drm_i915_private *i915 = guc_to_i915(guc); GEM_BUG_ON(!i915->wopcm.size); - GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base); - guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base; + guc->ggtt_pin_bias = i915->wopcm.guc.size; } /** From patchwork Fri Jul 27 14:11:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Bartminski, Jakub" X-Patchwork-Id: 10547223 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3507414BC for ; Fri, 27 Jul 2018 14:12:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25EC62BCA6 for ; Fri, 27 Jul 2018 14:12:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A6F82BCB6; Fri, 27 Jul 2018 14:12:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C91032BCA6 for ; Fri, 27 Jul 2018 14:12:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D8EED6EAC6; Fri, 27 Jul 2018 14:12:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id F1D036EAC2 for ; Fri, 27 Jul 2018 14:12:28 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jul 2018 07:12:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,409,1526367600"; d="scan'208";a="219631460" Received: from jbartmin-desk.igk.intel.com ([172.28.181.141]) by orsmga004.jf.intel.com with ESMTP; 27 Jul 2018 07:12:26 -0700 From: =?utf-8?q?Jakub_Bartmi=C5=84ski?= To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Jul 2018 16:11:44 +0200 Message-Id: <20180727141148.30874-2-jakub.bartminski@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180727141148.30874-1-jakub.bartminski@intel.com> References: <20180727141148.30874-1-jakub.bartminski@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP There seems to be no reason for doing extra work on WOPCM partitioning in the case GuC is not used, as the partitioning will not be used by the intel_wopcm_init_hw function anyway. Signed-off-by: Jakub Bartmiński Cc: Chris Wilson Cc: Michał Winiarski Cc: Michal Wajdeczko Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_wopcm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 74bf76f3fddc..09cc62b0d7ca 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -163,6 +163,9 @@ int intel_wopcm_init(struct intel_wopcm *wopcm) u32 guc_wopcm_rsvd; int err; + if (!USES_GUC(dev_priv)) + return 0; + GEM_BUG_ON(!wopcm->size); if (guc_fw_size >= wopcm->size) { From patchwork Fri Jul 27 14:11:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Bartminski, Jakub" X-Patchwork-Id: 10547221 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94DF314BC for ; Fri, 27 Jul 2018 14:12:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 81F4D2BCA6 for ; Fri, 27 Jul 2018 14:12:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 763572BCB6; Fri, 27 Jul 2018 14:12:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BCFA12BCA6 for ; Fri, 27 Jul 2018 14:12:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B8CC26EAC3; Fri, 27 Jul 2018 14:12:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id D4B756EAC3 for ; Fri, 27 Jul 2018 14:12:31 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jul 2018 07:12:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,409,1526367600"; d="scan'208";a="219631470" Received: from jbartmin-desk.igk.intel.com ([172.28.181.141]) by orsmga004.jf.intel.com with ESMTP; 27 Jul 2018 07:12:29 -0700 From: =?utf-8?q?Jakub_Bartmi=C5=84ski?= To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Jul 2018 16:11:45 +0200 Message-Id: <20180727141148.30874-3-jakub.bartminski@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180727141148.30874-1-jakub.bartminski@intel.com> References: <20180727141148.30874-1-jakub.bartminski@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Removing the pin bias from GuC allows us to not check for GuC every time we pin a context, which fixes the assertion error on unresolved GuC platform default in mock contexts selftest. It also seems that we were using uninitialized WOPCM variables when setting the GuC pin bias. The pin bias has to be set after the WOPCM, but before the call to i915_gem_contexts_init where the first contexts are pinned. v2: This also makes it so that there's no need to set GuC variables from within the WOPCM init function or to move the WOPCM init, while keeping the correct initialization order. Also for mock tests the pin bias is left at 0 and we make sure that the pin bias with GuC will not be smaller than without GuC. v3: Avoid unused i915 in intel_guc_ggtt_offset if debug is disabled. v4: Squash with WOPCM init reordering. Moved the i915_ggtt_pin_bias helper to this patch, and made some functions use it instead of directly dereferencing i915->ggtt. v5: Since we now don't use wopcm.guc.base for the pin bias there's no need to validate it. It also has already been verified in WOPCM init. v6: Deleted the now unnecessarily introduced includes from previous versions. Dropped naming changes from dev_priv to i915 for better patch readability. v7: Changed some comments to make more sense in the context they're in. v8: Moved and renamed the function which now returns the wopcm.guc.size to intel_guc.c:intel_guc_reserved_gtt_size to avoid any possible confusion with the pin_bias in ggtt, which should be used for pinning. Fixed patch not applying or the most recent upstream. Fixes: f7dc0157e4b5 ("drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init") Testcase: igt/drv_selftest/mock_contexts #GuC Signed-off-by: Jakub Bartmiński Cc: Chris Wilson Cc: Michał Winiarski Cc: Michal Wajdeczko Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c | 10 +----- drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++ drivers/gpu/drm/i915/i915_vma.h | 5 +++ drivers/gpu/drm/i915/intel_guc.c | 42 ++++++++++++------------- drivers/gpu/drm/i915/intel_guc.h | 12 +++---- drivers/gpu/drm/i915/intel_huc.c | 2 +- drivers/gpu/drm/i915/intel_uc_fw.c | 2 +- 8 files changed, 44 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index b10770cfccd2..32f96b8cd9c4 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -329,15 +329,7 @@ __create_hw_context(struct drm_i915_private *dev_priv, ctx->desc_template = default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt); - /* - * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not - * present or not in use we still need a small bias as ring wraparound - * at offset 0 sometimes hangs. No idea why. - */ - if (USES_GUC(dev_priv)) - ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias; - else - ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE; + ctx->ggtt_offset_bias = dev_priv->ggtt.pin_bias; return ctx; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 1b476423bfab..87219870d559 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2929,6 +2929,15 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) struct drm_mm_node *entry; int ret; + /* + * GuC requires all resources that we're sharing with it to be placed in + * non-WOPCM memory. If GuC is not present or not in use we still need a + * small bias as ring wraparound at offset 0 sometimes hangs. No idea + * why. + */ + ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE, + intel_guc_reserved_gtt_size(&dev_priv->guc)); + ret = intel_vgt_balloon(dev_priv); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 2a116a91420b..ce945bf78a89 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -401,6 +401,8 @@ struct i915_ggtt { int mtrr; + u32 pin_bias; + struct drm_mm_node error_capture; }; diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index af5296b015f5..f1ba40bbe6f9 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -208,6 +208,11 @@ static inline u32 i915_ggtt_offset(const struct i915_vma *vma) return lower_32_bits(vma->node.start); } +static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma) +{ + return i915_vm_to_ggtt(vma->vm)->pin_bias; +} + static inline struct i915_vma *i915_vma_get(struct i915_vma *vma) { i915_gem_object_get(vma->obj); diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index deb6a2053eaf..230aea69385d 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -27,8 +27,6 @@ #include "intel_guc_submission.h" #include "i915_drv.h" -static void guc_init_ggtt_pin_bias(struct intel_guc *guc); - static void gen8_guc_raise_irq(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); @@ -144,8 +142,6 @@ int intel_guc_init_misc(struct intel_guc *guc) struct drm_i915_private *i915 = guc_to_i915(guc); int ret; - guc_init_ggtt_pin_bias(guc); - ret = guc_init_wq(guc); if (ret) return ret; @@ -606,22 +602,6 @@ int intel_guc_resume(struct intel_guc *guc) * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size. */ -/** - * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value. - * @guc: intel_guc structure. - * - * This function will calculate and initialize the ggtt_pin_bias value - * based on the GuC WOPCM size. - */ -static void guc_init_ggtt_pin_bias(struct intel_guc *guc) -{ - struct drm_i915_private *i915 = guc_to_i915(guc); - - GEM_BUG_ON(!i915->wopcm.size); - - guc->ggtt_pin_bias = i915->wopcm.guc.size; -} - /** * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage * @guc: the guc @@ -640,6 +620,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) struct drm_i915_private *dev_priv = guc_to_i915(guc); struct drm_i915_gem_object *obj; struct i915_vma *vma; + u64 flags; int ret; obj = i915_gem_object_create(dev_priv, size); @@ -650,8 +631,8 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) if (IS_ERR(vma)) goto err; - ret = i915_vma_pin(vma, 0, 0, - PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias); + flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); + ret = i915_vma_pin(vma, 0, 0, flags); if (ret) { vma = ERR_PTR(ret); goto err; @@ -663,3 +644,20 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) i915_gem_object_put(obj); return vma; } + +/** + * intel_guc_reserved_gtt_size() + * @guc: intel_guc structure + * + * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we are using + * GuC we can't have any objects pinned in that region. This function returns + * the size of the shadowed region. + * + * Returns: + * 0 if GuC is not present or not in use. + * Otherwise, the GuC WOPCM size. + */ +u32 intel_guc_reserved_gtt_size(struct intel_guc *guc) +{ + return guc_to_i915(guc)->wopcm.guc.size; +} diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 4121928a495e..ad42faf48c46 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -49,9 +49,6 @@ struct intel_guc { struct intel_guc_log log; struct intel_guc_ct ct; - /* Offset where Non-WOPCM memory starts. */ - u32 ggtt_pin_bias; - /* Log snapshot if GuC errors during load */ struct drm_i915_gem_object *load_err_log; @@ -130,10 +127,10 @@ static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) * @vma: i915 graphics virtual memory area. * * GuC does not allow any gfx GGTT address that falls into range - * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. - * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from + * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. + * Currently, in order to exclude [0, ggtt.pin_bias) address space from * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() - * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias. + * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. * * Return: GGTT offset of the @vma. */ @@ -142,7 +139,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc, { u32 offset = i915_ggtt_offset(vma); - GEM_BUG_ON(offset < guc->ggtt_pin_bias); + GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma)); GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); return offset; @@ -168,6 +165,7 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); int intel_guc_suspend(struct intel_guc *guc); int intel_guc_resume(struct intel_guc *guc); struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); +u32 intel_guc_reserved_gtt_size(struct intel_guc *guc); static inline int intel_guc_sanitize(struct intel_guc *guc) { diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index ffcad5fad6a7..37ef540dd280 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -63,7 +63,7 @@ int intel_huc_auth(struct intel_huc *huc) return -ENOEXEC; vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, - PIN_OFFSET_BIAS | guc->ggtt_pin_bias); + PIN_OFFSET_BIAS | i915->ggtt.pin_bias); if (IS_ERR(vma)) { ret = PTR_ERR(vma); DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret); diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c index 6e8e0b546743..fd496416087c 100644 --- a/drivers/gpu/drm/i915/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/intel_uc_fw.c @@ -222,7 +222,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, goto fail; } - ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->guc.ggtt_pin_bias; + ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->ggtt.pin_bias; vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0, PIN_OFFSET_BIAS | ggtt_pin_bias); if (IS_ERR(vma)) { From patchwork Fri Jul 27 14:11:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Bartminski, Jakub" X-Patchwork-Id: 10547227 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CD36D14E0 for ; Fri, 27 Jul 2018 14:12:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BD2BB20246 for ; Fri, 27 Jul 2018 14:12:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B19DD27D29; Fri, 27 Jul 2018 14:12:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 48C2B20246 for ; Fri, 27 Jul 2018 14:12:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C02966EACC; Fri, 27 Jul 2018 14:12:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8AD386EAC9 for ; Fri, 27 Jul 2018 14:12:34 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jul 2018 07:12:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,409,1526367600"; d="scan'208";a="219631476" Received: from jbartmin-desk.igk.intel.com ([172.28.181.141]) by orsmga004.jf.intel.com with ESMTP; 27 Jul 2018 07:12:31 -0700 From: =?utf-8?q?Jakub_Bartmi=C5=84ski?= To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Jul 2018 16:11:46 +0200 Message-Id: <20180727141148.30874-4-jakub.bartminski@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180727141148.30874-1-jakub.bartminski@intel.com> References: <20180727141148.30874-1-jakub.bartminski@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 4/6] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Since ggtt_offset_bias is now stored in ggtt.pin_bias, it is duplicated inside i915_gem_context, and can instead be accessed directly from ggtt. v3: Added a helper function to retrieve the ggtt.pin_bias from the vma. v4: Moved the helper function to the previous patch in the series. Dropped the bias from intel_ring_pin. This introduces a slight functional change since we are always pinning the ring a bit higher if GuC is present even though we don't really need to. v8: Fixed patch not applying on the most recent upstream. Signed-off-by: Jakub Bartmiński Cc: Chris Wilson Cc: Michał Winiarski Cc: Michal Wajdeczko Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c | 2 -- drivers/gpu/drm/i915/i915_gem_context.h | 3 --- drivers/gpu/drm/i915/intel_lrc.c | 6 ++---- drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++++++-------- drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +--- 5 files changed, 9 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 32f96b8cd9c4..f15a039772db 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -329,8 +329,6 @@ __create_hw_context(struct drm_i915_private *dev_priv, ctx->desc_template = default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt); - ctx->ggtt_offset_bias = dev_priv->ggtt.pin_bias; - return ctx; err_pid: diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index b116e4942c10..851dad6decd7 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -147,9 +147,6 @@ struct i915_gem_context { struct i915_sched_attr sched; - /** ggtt_offset_bias: placement restriction for context objects */ - u32 ggtt_offset_bias; - /** engine: per-engine logical HW state */ struct intel_context { struct i915_gem_context *gem_context; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 66c7252526f3..9b97278c7c00 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1303,9 +1303,7 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma) } flags = PIN_GLOBAL | PIN_HIGH; - if (ctx->ggtt_offset_bias) - flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias; - + flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); return i915_vma_pin(vma, 0, 0, flags); } @@ -1332,7 +1330,7 @@ __execlists_context_pin(struct intel_engine_cs *engine, goto unpin_vma; } - ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias); + ret = intel_ring_pin(ce->ring, ctx->i915); if (ret) goto unpin_map; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 27b24000412f..7e952173d0c0 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1005,9 +1005,7 @@ i915_emit_bb_start(struct i915_request *rq, -int intel_ring_pin(struct intel_ring *ring, - struct drm_i915_private *i915, - unsigned int offset_bias) +int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private *i915) { enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; struct i915_vma *vma = ring->vma; @@ -1017,10 +1015,11 @@ int intel_ring_pin(struct intel_ring *ring, GEM_BUG_ON(ring->vaddr); - flags = PIN_GLOBAL; - if (offset_bias) - flags |= PIN_OFFSET_BIAS | offset_bias; + + /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ + flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); + if (vma->obj->stolen) flags |= PIN_MAPPABLE; else @@ -1408,8 +1407,7 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine) goto err; } - /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ - err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE); + err = intel_ring_pin(ring, engine->i915); if (err) goto err_ring; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index f5ffa6d31e82..399ec58d1f9d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -797,9 +797,7 @@ struct intel_ring * intel_engine_create_ring(struct intel_engine_cs *engine, struct i915_timeline *timeline, int size); -int intel_ring_pin(struct intel_ring *ring, - struct drm_i915_private *i915, - unsigned int offset_bias); +int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private *i915); void intel_ring_reset(struct intel_ring *ring, u32 tail); unsigned int intel_ring_update_space(struct intel_ring *ring); void intel_ring_unpin(struct intel_ring *ring); From patchwork Fri Jul 27 14:11:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Bartminski, Jakub" X-Patchwork-Id: 10547225 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EECC614E0 for ; Fri, 27 Jul 2018 14:12:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DCE4620246 for ; Fri, 27 Jul 2018 14:12:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CEEC127D29; Fri, 27 Jul 2018 14:12:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 88B1020246 for ; Fri, 27 Jul 2018 14:12:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 162E56EAC9; Fri, 27 Jul 2018 14:12:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 536F26EAC9 for ; Fri, 27 Jul 2018 14:12:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jul 2018 07:12:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,409,1526367600"; d="scan'208";a="219631483" Received: from jbartmin-desk.igk.intel.com ([172.28.181.141]) by orsmga004.jf.intel.com with ESMTP; 27 Jul 2018 07:12:34 -0700 From: =?utf-8?q?Jakub_Bartmi=C5=84ski?= To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Jul 2018 16:11:47 +0200 Message-Id: <20180727141148.30874-5-jakub.bartminski@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180727141148.30874-1-jakub.bartminski@intel.com> References: <20180727141148.30874-1-jakub.bartminski@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 5/6] drm/i915: Add a fault injection point to WOPCM init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add a fault injection point in the WOPCM initialization path. v4: Move the injection inside the WOPCM init function. Signed-off-by: Jakub Bartmiński Cc: Chris Wilson Cc: Michał Winiarski Cc: Michal Wajdeczko Reviewed-by: Michal Wajdeczko Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_wopcm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 09cc62b0d7ca..92cb82dd0c07 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -168,6 +168,9 @@ int intel_wopcm_init(struct intel_wopcm *wopcm) GEM_BUG_ON(!wopcm->size); + if (i915_inject_load_failure()) + return -E2BIG; + if (guc_fw_size >= wopcm->size) { DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.", guc_fw_size / 1024); From patchwork Fri Jul 27 14:11:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bartminski, Jakub" X-Patchwork-Id: 10547229 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE6E114BC for ; Fri, 27 Jul 2018 14:12:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC7B620246 for ; Fri, 27 Jul 2018 14:12:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D115D27D29; Fri, 27 Jul 2018 14:12:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9E66820246 for ; Fri, 27 Jul 2018 14:12:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 081D06EACD; Fri, 27 Jul 2018 14:12:41 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id CADCC6EAC9 for ; Fri, 27 Jul 2018 14:12:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jul 2018 07:12:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,409,1526367600"; d="scan'208";a="219631490" Received: from jbartmin-desk.igk.intel.com ([172.28.181.141]) by orsmga004.jf.intel.com with ESMTP; 27 Jul 2018 07:12:37 -0700 From: =?utf-8?q?Jakub_Bartmi=C5=84ski?= To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Jul 2018 16:11:48 +0200 Message-Id: <20180727141148.30874-6-jakub.bartminski@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180727141148.30874-1-jakub.bartminski@intel.com> References: <20180727141148.30874-1-jakub.bartminski@intel.com> Subject: [Intel-gfx] [PATCH v8 6/6] HAX enable GuC for CI X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Michal Wajdeczko Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 6c4d4a21474b..323fdc258c6a 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -46,7 +46,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, -1) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \