From patchwork Fri Feb 28 16:00:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11412713 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D2A9C138D for ; Fri, 28 Feb 2020 16:01:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B195E2064A for ; Fri, 28 Feb 2020 16:01:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="aP2Yl7o9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727309AbgB1QBQ (ORCPT ); Fri, 28 Feb 2020 11:01:16 -0500 Received: from mo4-p02-ob.smtp.rzone.de ([85.215.255.84]:27198 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727175AbgB1QBD (ORCPT ); Fri, 28 Feb 2020 11:01:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582905660; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=Lg2vjJyPeK3SdOkL22G/V755a2Cx89sCodyhANXZ7FE=; b=aP2Yl7o9i8jYXO4vql6HpjmZAO9iOUuwttOuSkFp6OZxHk3DTa1Hnb57M4Ut7AFayS jCKmhdUbGuLrLO1jSNUrGBfTsHnK2KYYdtxkcUysPWhqzUYFfC0L95A9T0HAIIjuodA9 DgxRR34Yd+uZRBuHV0Gpygk14hKljyy7Fs7CGww46STL1+Q4Fe33WRR/tgMT5d+HDwRp R7vxZ3LPPcKOtrBV0m8lFqo1TzNV9xUzVFyN0iYSaKigatqAqX8URRyO2mjJ0zVDW2Y3 dmjUHBzx9WBhBYVq9RWdKkc4sJBLJYoAET14jVdnHmMVOwo3LUZ5kJ937aPMRcGCiKBE GyYg== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXH6G1+ULkA=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.2.0 DYNA|AUTH) with ESMTPSA id y0a02cw1SG0t1l5 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Fri, 28 Feb 2020 17:00:55 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v8 1/7] memory: jz4780_nemc: Only request IO memory the driver will use Date: Fri, 28 Feb 2020 17:00:47 +0100 Message-Id: <551a8560261543c1decb1d4d1671ec4b7fa52fdb.1582905653.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Paul Cercueil The driver only uses the registers up to offset 0x54. Since the EFUSE registers are in the middle of the NEMC registers, we only request the registers we will use for now - that way the EFUSE driver can probe too. Tested-by: H. Nikolaus Schaller Signed-off-by: Paul Cercueil --- drivers/memory/jz4780-nemc.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c index b232ed279fc3..647267ea8c63 100644 --- a/drivers/memory/jz4780-nemc.c +++ b/drivers/memory/jz4780-nemc.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -288,7 +289,19 @@ static int jz4780_nemc_probe(struct platform_device *pdev) nemc->dev = dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - nemc->base = devm_ioremap_resource(dev, res); + + /* + * The driver only uses the registers up to offset 0x54. Since the EFUSE + * registers are in the middle of the NEMC registers, we only request + * the registers we will use for now - that way the EFUSE driver can + * probe too. + */ + if (!devm_request_mem_region(dev, res->start, 0x54, dev_name(dev))) { + dev_err(dev, "unable to request I/O memory region\n"); + return -EBUSY; + } + + nemc->base = devm_ioremap(dev, res->start, resource_size(res)); if (IS_ERR(nemc->base)) { dev_err(dev, "failed to get I/O memory\n"); return PTR_ERR(nemc->base); From patchwork Fri Feb 28 16:00:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11412707 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8EFB7138D for ; Fri, 28 Feb 2020 16:01:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D60D246AF for ; Fri, 28 Feb 2020 16:01:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="PCOuu4Fq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727276AbgB1QBF (ORCPT ); Fri, 28 Feb 2020 11:01:05 -0500 Received: from mo4-p02-ob.smtp.rzone.de ([81.169.146.170]:13583 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727176AbgB1QBE (ORCPT ); Fri, 28 Feb 2020 11:01:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582905661; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=jznI9sgN3GlRGS/wVAf+ljIlUOIOh9zERGg8FW8emSw=; b=PCOuu4FqsMi/cMRqgvtIciSzCDnBZ/sKTiG1bJuX3NenCNiNObwLhXpDN3aY4Rmu5o P77jvqifgwviEnpXYaHuZ6lcdeWPYnrVV68i2pml0Dajgcxjdq3b+AQtggDkMPzHTP5N ZNFcCbvikGaOPXtAwTup74ibzRc/o3FSCI39gyw4Ur/wPqbTxMnm4YvmBvhS76x8SswE xFduqnCr9Tz6uWTTUyBWoXBmHQTa4wOeOsmJGx5kzuYrG9sugJFzSakVKoKkl0Z57wJ9 wxdotY3ZEA2khlwQ0g8RaahPSdjV1V0U0KrKVPaZxe+Zucg2msAnPR9R41v6ESlZLDaH Eu1g== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXH6G1+ULkA=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.2.0 DYNA|AUTH) with ESMTPSA id y0a02cw1SG0u1l6 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Fri, 28 Feb 2020 17:00:56 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v8 2/7] nvmem: add driver for JZ4780 efuse Date: Fri, 28 Feb 2020 17:00:48 +0100 Message-Id: <86886abd9493d0d3b7c9b2eba4e928c2aa4be5d7.1582905653.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and nvmem cells. To fetch for example the MAC address: dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1 skip=34 count=6 status=none | xxd Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre Signed-off-by: H. Nikolaus Schaller Signed-off-by: Paul Cercueil --- drivers/nvmem/Kconfig | 12 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/jz4780-efuse.c | 239 +++++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+) create mode 100644 drivers/nvmem/jz4780-efuse.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 35efab1ba8d9..d7b7f6d688e7 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -55,6 +55,18 @@ config NVMEM_IMX_OCOTP_SCU This is a driver for the SCU On-Chip OTP Controller (OCOTP) available on i.MX8 SoCs. +config JZ4780_EFUSE + tristate "JZ4780 EFUSE Memory Support" + depends on MACH_INGENIC || COMPILE_TEST + depends on HAS_IOMEM + depends on OF + select REGMAP_MMIO + help + Say Y here to include support for JZ4780 efuse memory found on + all JZ4780 SoC based devices. + To compile this driver as a module, choose M here: the module + will be called nvmem_jz4780_efuse. + config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6b466cd1427b..65a268d17807 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o +nvmem_jz4780_efuse-y := jz4780-efuse.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c new file mode 100644 index 000000000000..51d140980b1e --- /dev/null +++ b/drivers/nvmem/jz4780-efuse.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * JZ4780 EFUSE Memory Support driver + * + * Copyright (c) 2017 PrasannaKumar Muralidharan + * Copyright (c) 2020 H. Nikolaus Schaller + */ + +/* + * Currently supports JZ4780 efuse which has 8K programmable bit. + * Efuse is separated into seven segments as below: + * + * ----------------------------------------------------------------------- + * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit | + * ----------------------------------------------------------------------- + * + * The rom itself is accessed using a 9 bit address line and an 8 word wide bus + * which reads/writes based on strobes. The strobe is configured in the config + * register and is based on number of cycles of the bus clock. + * + * Driver supports read only as the writes are done in the Factory. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define JZ_EFUCTRL (0x0) /* Control Register */ +#define JZ_EFUCFG (0x4) /* Configure Register*/ +#define JZ_EFUSTATE (0x8) /* Status Register */ +#define JZ_EFUDATA(n) (0xC + (n) * 4) + +/* We read 32 byte chunks to avoid complexity in the driver. */ +#define JZ_EFU_READ_SIZE 32 + +#define EFUCTRL_ADDR_MASK 0x3FF +#define EFUCTRL_ADDR_SHIFT 21 +#define EFUCTRL_LEN_MASK 0x1F +#define EFUCTRL_LEN_SHIFT 16 +#define EFUCTRL_PG_EN BIT(15) +#define EFUCTRL_WR_EN BIT(1) +#define EFUCTRL_RD_EN BIT(0) + +#define EFUCFG_INT_EN BIT(31) +#define EFUCFG_RD_ADJ_MASK 0xF +#define EFUCFG_RD_ADJ_SHIFT 20 +#define EFUCFG_RD_STR_MASK 0xF +#define EFUCFG_RD_STR_SHIFT 16 +#define EFUCFG_WR_ADJ_MASK 0xF +#define EFUCFG_WR_ADJ_SHIFT 12 +#define EFUCFG_WR_STR_MASK 0xFFF +#define EFUCFG_WR_STR_SHIFT 0 + +#define EFUSTATE_WR_DONE BIT(1) +#define EFUSTATE_RD_DONE BIT(0) + +struct jz4780_efuse { + struct device *dev; + struct regmap *map; + struct clk *clk; +}; + +/* main entry point */ +static int jz4780_efuse_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct jz4780_efuse *efuse = context; + + while (bytes > 0) { + unsigned int start = offset & ~(JZ_EFU_READ_SIZE - 1); + unsigned int chunk = min(bytes, (start + JZ_EFU_READ_SIZE) + - offset); + char buf[JZ_EFU_READ_SIZE]; + unsigned int tmp; + u32 ctrl; + int ret; + + ctrl = (start << EFUCTRL_ADDR_SHIFT) + | ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT) + | EFUCTRL_RD_EN; + + regmap_update_bits(efuse->map, JZ_EFUCTRL, + (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) | + (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) | + EFUCTRL_PG_EN | EFUCTRL_WR_EN | + EFUCTRL_RD_EN, + ctrl); + + ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE, + tmp, tmp & EFUSTATE_RD_DONE, + 1 * MSEC_PER_SEC, + 50 * MSEC_PER_SEC); + if (ret < 0) { + dev_err(efuse->dev, "Time out while reading efuse data"); + return ret; + } + + ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0), + buf, JZ_EFU_READ_SIZE / sizeof(u32)); + if (ret < 0) + return ret; + + memcpy(val, &buf[offset - start], chunk); + + val += chunk; + offset += chunk; + bytes -= chunk; + } + + return 0; +} + +static struct nvmem_config jz4780_efuse_nvmem_config = { + .name = "jz4780-efuse", + .size = 1024, + .word_size = 1, + .stride = 1, + .owner = THIS_MODULE, + .reg_read = jz4780_efuse_read, +}; + +static const struct regmap_config jz4780_efuse_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = JZ_EFUDATA(7), +}; + +static void clk_disable_unprepare_helper(void *clock) +{ + clk_disable_unprepare(clock); +} + +static int jz4780_efuse_probe(struct platform_device *pdev) +{ + struct nvmem_device *nvmem; + struct jz4780_efuse *efuse; + struct nvmem_config cfg; + unsigned long clk_rate; + unsigned long rd_adj; + unsigned long rd_strobe; + struct device *dev = &pdev->dev; + void __iomem *regs; + int ret; + + efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); + if (!efuse) + return -ENOMEM; + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + efuse->map = devm_regmap_init_mmio(dev, regs, + &jz4780_efuse_regmap_config); + if (IS_ERR(efuse->map)) + return PTR_ERR(efuse->map); + + efuse->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(efuse->clk)) + return PTR_ERR(efuse->clk); + + ret = clk_prepare_enable(efuse->clk); + if (ret < 0) + return ret; + + ret = devm_add_action_or_reset(&pdev->dev, + clk_disable_unprepare_helper, + efuse->clk); + if (ret < 0) + return ret; + + clk_rate = clk_get_rate(efuse->clk); + + efuse->dev = dev; + + /* + * rd_adj and rd_strobe are 4 bit values + * conditions: + * bus clk_period * (rd_adj + 1) > 6.5ns + * bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns + * i.e. rd_adj >= 6.5ns / clk_period + * i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1 + * constants: + * 1 / 6.5ns == 153846154 Hz + * 1 / 35ns == 28571429 Hz + */ + + rd_adj = clk_rate / 153846154; + rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1; + + if (rd_adj > EFUCFG_RD_ADJ_MASK || + rd_strobe > EFUCFG_RD_STR_MASK) { + dev_err(&pdev->dev, "Cannot set clock configuration\n"); + return -EINVAL; + } + + regmap_update_bits(efuse->map, JZ_EFUCFG, + (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) | + (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT), + (rd_adj << EFUCFG_RD_ADJ_SHIFT) | + (rd_strobe << EFUCFG_RD_STR_SHIFT)); + + cfg = jz4780_efuse_nvmem_config; + cfg.dev = &pdev->dev; + cfg.priv = efuse; + + nvmem = devm_nvmem_register(dev, &cfg); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); + + return 0; +} + +static const struct of_device_id jz4780_efuse_match[] = { + { .compatible = "ingenic,jz4780-efuse" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, jz4780_efuse_match); + +static struct platform_driver jz4780_efuse_driver = { + .probe = jz4780_efuse_probe, + .driver = { + .name = "jz4780-efuse", + .of_match_table = jz4780_efuse_match, + }, +}; +module_platform_driver(jz4780_efuse_driver); + +MODULE_AUTHOR("PrasannaKumar Muralidharan "); +MODULE_AUTHOR("H. Nikolaus Schaller "); +MODULE_AUTHOR("Paul Cercueil "); +MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Feb 28 16:00:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11412721 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97ABC138D for ; Fri, 28 Feb 2020 16:01:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 742922064A for ; Fri, 28 Feb 2020 16:01:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="WlxMPV0I" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727206AbgB1QBD (ORCPT ); Fri, 28 Feb 2020 11:01:03 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.103]:33668 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727173AbgB1QBC (ORCPT ); Fri, 28 Feb 2020 11:01:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582905660; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=gbizeSabj1SA3R/yYEBCTuuOG7bMiftKSlGUj+fFwyY=; b=WlxMPV0ImmhxV2wlP9v+eCctIi14LDAECsmXnNMg+P37NefcgwjMROnDwCiLgciIQ6 hv4aH45xJ4VPkeftrb3x010LNmOcUIsxbFFm7jgdX1oRRbJnp553yf2W1/BSTN+CdKVj cDlo/7Zha1Dpisa/uoeph6pAEZK/mXKhZuJ1362+VPiht89Ty0IfI2CWMTIqAL+zILp+ v903J6rRfqr4pSVVDd6S8YnfLt7JWpju9c4ugnwkB33QrtdfhTlcAgC4dkqU86pzdiK9 YXOnA5SSZ2/qqjEbLV5Q0ymt2RoPjysKbKzEjVFs0qeD1UpdxaMP7YD3eS/J6UbHYEXS LHmw== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXH6G1+ULkA=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.2.0 DYNA|AUTH) with ESMTPSA id y0a02cw1SG0u1l9 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Fri, 28 Feb 2020 17:00:56 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v8 3/7] Bindings: nvmem: add bindings for JZ4780 efuse Date: Fri, 28 Feb 2020 17:00:49 +0100 Message-Id: <37d3b9e4c60692215fff0e75a78ac1e7792aaf75.1582905653.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre Signed-off-by: H. Nikolaus Schaller [converted to yaml] Signed-off-by: Andreas Kemnade Reviewed-by: Rob Herring --- .../bindings/nvmem/ingenic,jz4780-efuse.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml new file mode 100644 index 000000000000..1485d3fbabfd --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic JZ EFUSE driver bindings + +maintainers: + - PrasannaKumar Muralidharan + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - ingenic,jz4780-efuse + + reg: + maxItems: 1 + + clocks: + # Handle for the ahb for the efuse. + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + + efuse@134100d0 { + compatible = "ingenic,jz4780-efuse"; + reg = <0x134100d0 0x2c>; + + clocks = <&cgu JZ4780_CLK_AHB2>; + }; + +... From patchwork Fri Feb 28 16:00:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11412709 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA5EA17E0 for ; Fri, 28 Feb 2020 16:01:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9A85D246BF for ; Fri, 28 Feb 2020 16:01:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="EkQ5dMEO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727305AbgB1QBJ (ORCPT ); Fri, 28 Feb 2020 11:01:09 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.103]:33566 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727176AbgB1QBI (ORCPT ); Fri, 28 Feb 2020 11:01:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582905666; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=Ay31G7exAkSbg3PL1nOzfK8qqlNf1gmdrl8NmheHFD8=; b=EkQ5dMEOfGDQHO6gCTfYD/RC/vUI0V/6tQgBxMhJK9BCaWu+pUBJT533EFcMgguNw9 D5m7FoNNxXWw9EiD3382vG7sO72FeWynJObHctMNzF2P/KyycZxqf+eW9C/rvxykddQr dwtLaZjrLYnvORd2K+f5Ql+2ZWyFVhd91RvSwkugOCYkDCE7W5DKWD4mKZexI3RsezgD XyKfC4/o2lx34FCeYzoouXxxDRtQxMD8rNM9drWFO+WTG1sEZ+RvJnXpaOTWdrpRNFaK +595XDsTjCArILb1R7fQLZ56vZLfie+jopiZJC/qbSvn3hZ+d18U673x7reAuLygQZpR PSLw== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXH6G1+ULkA=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.2.0 DYNA|AUTH) with ESMTPSA id y0a02cw1SG0v1lB (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Fri, 28 Feb 2020 17:00:57 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v8 4/7] Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI Date: Fri, 28 Feb 2020 17:00:50 +0100 Message-Id: <08f3bb4e0fe5499907c4e07fa6751bfb2016f23d.1582905653.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre --- .../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse diff --git a/Documentation/ABI/testing/sysfs-driver-jz4780-efuse b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse new file mode 100644 index 000000000000..bb6f5d6ceea0 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse @@ -0,0 +1,16 @@ +What: /sys/devices/*//nvmem +Date: December 2017 +Contact: PrasannaKumar Muralidharan +Description: read-only access to the efuse on the Ingenic JZ4780 SoC + The SoC has a one time programmable 8K efuse that is + split into segments. The driver supports read only. + The segments are + 0x000 64 bit Random Number + 0x008 128 bit Ingenic Chip ID + 0x018 128 bit Customer ID + 0x028 3520 bit Reserved + 0x1E0 8 bit Protect Segment + 0x1E1 2296 bit HDMI Key + 0x300 2048 bit Security boot key +Users: any user space application which wants to read the Chip + and Customer ID From patchwork Fri Feb 28 16:00:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11412703 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B2AC314B4 for ; Fri, 28 Feb 2020 16:01:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 27E62246A0 for ; Fri, 28 Feb 2020 16:01:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="obx2pb6b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727180AbgB1QBC (ORCPT ); Fri, 28 Feb 2020 11:01:02 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([85.215.255.101]:23469 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727110AbgB1QBC (ORCPT ); Fri, 28 Feb 2020 11:01:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582905660; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=GELR2YwBhpj7Jht63ghsU23J1Jj6ZDwKHerFXjUqVS0=; b=obx2pb6bU3sA8mqJpwhQEkNdggSWf7bscJVmEtERntvmFeQo9MgN5VeTNdPGIwTaCk Axrtl3PesxJtGDx6MHmhLxndfH02B2UmQxZHxK+G8QE59bmxBC5AK2GvHMLFYjiRDse3 XgwVI4B4ig1fe3K8jFYx6WHJibdEYjR3sFx6CpVfR/EIqAb/oNpLe5padZSKAapOTp/L dU9ymzKqpB3CPqP67OG8Iyg4Om/Gr+ALtfCZuQ8hrFuUuZA1prujewW651vpVHzm+iW4 gqdsmB97iNJdru8oIGOwkvewfmTXK6a+lRtmoWe10IaYvLEwVBRnRJK7U53ZNFx1xsrD Axcw== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXH6G1+ULkA=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.2.0 DYNA|AUTH) with ESMTPSA id y0a02cw1SG0w1lD (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Fri, 28 Feb 2020 17:00:58 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v8 5/7] nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver Date: Fri, 28 Feb 2020 17:00:51 +0100 Message-Id: <39bcbaddd210e80e4a87d3f2a09565331ea8351e.1582905653.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fcd79fc38928..fcb8d89c2b2e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8271,6 +8271,11 @@ M: Zubair Lutfullah Kakakhel S: Maintained F: drivers/dma/dma-jz4780.c +INGENIC JZ4780 EFUSE Driver +M: PrasannaKumar Muralidharan +S: Maintained +F: drivers/nvmem/jz4780-efuse.c + INGENIC JZ4780 NAND DRIVER M: Harvey Hunt L: linux-mtd@lists.infradead.org From patchwork Fri Feb 28 16:00:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11412711 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7FA0B138D for ; Fri, 28 Feb 2020 16:01:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5EBB62064A for ; Fri, 28 Feb 2020 16:01:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="fitJY80O" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727331AbgB1QBK (ORCPT ); Fri, 28 Feb 2020 11:01:10 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.172]:16673 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727309AbgB1QBJ (ORCPT ); Fri, 28 Feb 2020 11:01:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582905667; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=JVyqpyxQobtq+JgSsD2shjOsk44PtbUGnvMUC7ptRTU=; b=fitJY80OxQpovYm6DD0f1l5ENhB4yOp8Nwq7vVYGCdkDry860RxUrcSsgXCCfXCNn1 O0p8lFHGGJMTUCbWFXyiiVmSV9KYn2sHViCoDSaxWydrijPwEM2RCBxa9wd1ndkagvs6 y95MFK3gQQCZ3SWCkt9URRedhP9Y/yNub7mwzuK53v4ePTN7otakm0aqKUqqP3eNbTuE pu0BTs8FUGOxUHS33lmGbsUm1ddxwEV36Rl6QFJNBzjQ3MvcbKaW0fb3qEFNwcgS3gKN c4jAGyI7/xUyWqkv+TH7FmwQMlSSpdgvYxOZt+8dWEi656JEvHnFkVOFX9ZNmHfgTuNf Fk4Q== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXH6G1+ULkA=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.2.0 DYNA|AUTH) with ESMTPSA id y0a02cw1SG0w1lF (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Fri, 28 Feb 2020 17:00:58 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v8 6/7] MIPS: DTS: JZ4780: define node for JZ4780 efuse Date: Fri, 28 Feb 2020 17:00:52 +0100 Message-Id: X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: PrasannaKumar Muralidharan This patch brings support for the JZ4780 efuse. Currently it only exposes a read only access to the entire 8K bits efuse memory and the ethernet mac address for the davicom dm9000 chip on the CI20 board. It also changes the nemc ranges definition to give the driver access to the efuse registers, which are in the middle of the nemc reg range. Tested-by: Mathieu Malaterre Signed-off-by: PrasannaKumar Muralidharan Signed-off-by: Mathieu Malaterre Signed-off-by: H. Nikolaus Schaller --- arch/mips/boot/dts/ingenic/jz4780.dtsi | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index f928329b034b..79f90a5b0415 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -357,11 +357,12 @@ }; nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; + compatible = "ingenic,jz4780-nemc", "simple-mfd"; reg = <0x13410000 0x10000>; #address-cells = <2>; #size-cells = <1>; - ranges = <1 0 0x1b000000 0x1000000 + ranges = <0 0 0x13410000 0x10000 + 1 0 0x1b000000 0x1000000 2 0 0x1a000000 0x1000000 3 0 0x19000000 0x1000000 4 0 0x18000000 0x1000000 @@ -371,6 +372,20 @@ clocks = <&cgu JZ4780_CLK_NEMC>; status = "disabled"; + + efuse: efuse@d0 { + reg = <0 0xd0 0x30>; + compatible = "ingenic,jz4780-efuse"; + + clocks = <&cgu JZ4780_CLK_AHB2>; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_addr: eth-mac-addr@0x22 { + reg = <0x22 0x6>; + }; + }; }; dma: dma@13420000 { From patchwork Fri Feb 28 16:00:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H. Nikolaus Schaller" X-Patchwork-Id: 11412715 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 069C5138D for ; Fri, 28 Feb 2020 16:01:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9DE2246AC for ; Fri, 28 Feb 2020 16:01:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="Nguqw9Ta" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727175AbgB1QBV (ORCPT ); Fri, 28 Feb 2020 11:01:21 -0500 Received: from mo4-p04-ob.smtp.rzone.de ([81.169.146.177]:31398 "EHLO mo4-p04-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727174AbgB1QBD (ORCPT ); Fri, 28 Feb 2020 11:01:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1582905661; s=strato-dkim-0002; d=goldelico.com; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=ex+tP/S3jJM/1n8mzovxtL99ooZIHpji+z8Ck9o3ixM=; b=Nguqw9TaMW/CZKCIE7/9KPe3sb3L0LODHrgZBYqQod2YID6ItUF9FhlCk3VnI7U0Qj DTBfmn/q3Syyw0UMpQRLJ0fJ3wROn477GX5I8aFGdyw8bPyHFl5p11XQqiywIJsKlHmA /8MVT59GtrwiIzrniBnf0nxUlAni5wCk6w+fstM81YAFEKDT/u2kYkOYAxx1aJTeTWDz 0tLMMv0aD+YiPA69wBpCJtrDo+mPWpcyaqgwi57BgFZsE8SalULgTeyK/vw3T8BF2Wxj pGfzeUr7PN3Ufm4oxAaPHSmk797UEbPn4BBMfDd8HOn7zA4P9UUGw55Qd5heBElhiZAH ZGlA== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o1mfYzBGHXH6G1+ULkA=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 46.2.0 DYNA|AUTH) with ESMTPSA id y0a02cw1SG0x1lH (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate); Fri, 28 Feb 2020 17:00:59 +0100 (CET) From: "H. Nikolaus Schaller" To: PrasannaKumar Muralidharan , Andreas Kemnade , Paul Cercueil , Mathieu Malaterre , Srinivas Kandagatla , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Jonathan Cameron , "H. Nikolaus Schaller" , Krzysztof Kozlowski , Kees Cook , Andi Kleen , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com Subject: [PATCH v8 7/7] MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the default MAC address Date: Fri, 28 Feb 2020 17:00:53 +0100 Message-Id: <1250f496a1f0bd51e89e5a1ba7a3e92a5570b27a.1582905653.git.hns@goldelico.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org There is a unique MAC address programmed into the eFuses of the JZ4780 chip in the CI20 factory. By using this for initializing the DM9000 Ethernet controller, every CI20 board has an individual - but stable - MAC address and DHCP can assign stable IP addresses. Signed-off-by: H. Nikolaus Schaller --- arch/mips/boot/dts/ingenic/ci20.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 37b93166bf22..6dc1f9eeff00 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -355,6 +355,9 @@ interrupt-parent = <&gpe>; interrupts = <19 4>; + + nvmem-cells = <ð0_addr>; + nvmem-cell-names = "mac-address"; }; };