From patchwork Mon Mar 2 00:19:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11414595 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E1131395 for ; Mon, 2 Mar 2020 00:20:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3D08E24697 for ; Mon, 2 Mar 2020 00:20:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UEYXrGzk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726875AbgCBAUM (ORCPT ); Sun, 1 Mar 2020 19:20:12 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:41998 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726621AbgCBAUM (ORCPT ); Sun, 1 Mar 2020 19:20:12 -0500 Received: by mail-wr1-f67.google.com with SMTP id z11so1583000wro.9; Sun, 01 Mar 2020 16:20:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jwhY+knTdQifg64CQcyFlmXWmsjzGep6/zqhcI9bJvM=; b=UEYXrGzkRs5DtYBt/rn6AQsmMC/2Z9xKSVunv1RGBVw6cAikyysRPrb65690a71+bs kWztWGQTn33hcIcRINH81JDbnieZvQ0r4aUruqit/laHDkzI1G203Pf4RQBnTx6Jbihd musKu5Lq4Ur7mkf3+urjMjin/dxeqbd9SEfrNp4cSXV3YikI3jrQ7sR2dkw89TxZdo68 o7wu2taZdQXEXPC1+QYjPKUkRMN03MCqWjcNW2UclCfnsQN8LX5139Eo9iALtz8IWeyl YKBNk4tinRBG3PTXOUDWSI9mIpqlmnBS7srQDebEfcZWG1xdaDwav3w2pVXt+9JQgrJZ xofA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jwhY+knTdQifg64CQcyFlmXWmsjzGep6/zqhcI9bJvM=; b=bI3osHsFzwpRMSJCWDnKNz/26KLuBk2cghUbIKZljCYffhQzt19rW5xrBD13damtai 44/3bUzgKAsIabo+5vL6adQ7w8Pvas1lGU75pKtN1Kvf0mvbi04FGoa68riCw8LDq8Bn hV/tM308gDCUjYT6dFmlNUcZR1+MLOOH9r8beGIwNyZ72Zeci0AVEfgmN81YN1jZIvv8 lRyR7p6UxpBSciuavh9VjdqGni3u+LgfSavEZBylOiOovKmzC5b3gQnmtnH2oEO8NW9/ 3tv17qtdG6YKD2ksV/eckQ4/ckQF3DtEOY+eujnMjoyo0Z0DZPNpWz2W2CosceNz7lfx fb+A== X-Gm-Message-State: APjAAAUvm47VvNZw1dKdZl7fODcurHI8uaCALAnavlHm25JM3VOBy/ME JhzuCmzD5pvpKNMNvCO/1BcF/2bM X-Google-Smtp-Source: APXvYqxv7k5QTum7D+PAa3XIZQelSvxMB/afGjTLGnBe6kljV+v8gm3/OqrURI0kfLQ52cz1sJg4Zg== X-Received: by 2002:adf:e9cc:: with SMTP id l12mr17152540wrn.131.1583108410561; Sun, 01 Mar 2020 16:20:10 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id k16sm25428417wrd.17.2020.03.01.16.20.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Mar 2020 16:20:10 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] doc: spi-fsl-dspi: Add specific compatibles for all Layerscape SoCs Date: Mon, 2 Mar 2020 02:19:53 +0200 Message-Id: <20200302001958.11105-2-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200302001958.11105-1-olteanv@gmail.com> References: <20200302001958.11105-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean Make the second compatible string optional for LS1012A, LS1088A and LS2080A. Old versions of the spi-fsl-dspi.c driver still need to probe on the old, generic compatible string for these controllers (such as "fsl,ls1021a-v1.0-dspi") which provides less functionality. Document the device tree bindings for LS1043A and LS1046A, whose bindings are already in use in fsl-ls1043a.dtsi and fsl-ls1046a.dtsi. Introduce new compatible strings for LS1028A and LX2160A. There will be no second compatible string for these. Signed-off-by: Vladimir Oltean --- .../devicetree/bindings/spi/spi-fsl-dspi.txt | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index 162e024b95a0..99b94cfe1623 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt @@ -1,12 +1,17 @@ ARM Freescale DSPI controller Required properties: -- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", - "fsl,ls2085a-dspi" - or - "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi" - "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi" - "fsl,ls1088a-dspi" followed by "fsl,ls1021a-v1.0-dspi" +- compatible : must be one of: + "fsl,vf610-dspi", + "fsl,ls1021a-v1.0-dspi", + "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), + "fsl,ls1028a-dspi", + "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), + "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), + "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), + "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"), + "fsl,ls2085a-dspi", + "fsl,lx2160a-dspi", - reg : Offset and length of the register set for the device - interrupts : Should contain SPI controller interrupt - clocks: from common clock binding: handle to dspi clock. From patchwork Mon Mar 2 00:19:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11414597 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2449D930 for ; Mon, 2 Mar 2020 00:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ED47E246B4 for ; Mon, 2 Mar 2020 00:20:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GNHTZs2u" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726918AbgCBAUR (ORCPT ); Sun, 1 Mar 2020 19:20:17 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:46425 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726562AbgCBAUO (ORCPT ); Sun, 1 Mar 2020 19:20:14 -0500 Received: by mail-wr1-f65.google.com with SMTP id j7so10260630wrp.13; Sun, 01 Mar 2020 16:20:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q/4hkXZDf7Y1E5NQ67SwQKMTujilQp/qfoqcDOmzaLU=; b=GNHTZs2ukLki4SQaZBCE/FutoDq8Fsii4TzuX4EujqDccxF0ZRgw445Zdr9QPhShfL C12xjV1YT2qaDiQXNBDfN9xWemQm336RFisfkdBm4Y/JwzJ8woxeaw/qoowoK6hj6A9J cDMQROwtd0CXcQw0MlULvGgdTg0UTJX0+qGPIu8ufwTV2xoUc8oj/1exzTFS3Lq+QwuY br8MFpHAWI5js4z5VC5kMVf0QWWjl9N+yctolxd+HuyLMCPYFDylxyvFJOGZm3ZJ/48W E04lSuWKhzYD9x5eizt7YPBTsnHgb+x1cMB0Zg/Kiy7m7e/XfONc2b2qOfOFF5PlsZnr MQcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q/4hkXZDf7Y1E5NQ67SwQKMTujilQp/qfoqcDOmzaLU=; b=r1zUxAOTkLLQQ0cW7+Nsu5LU17DV6Z2AUjEn1Fb3ieS9FRyxCsO5OzWyE1a7fxYBNc FYIJ7QbpgiVkmHrz22/YCzFa2ERj1If/dPGYOTY8xMB/K5+Sg4qtisVYHXdXo6brf2Zq lsvWKvuayr3QYZzBYwx3vLQEfMJXWp+QqWMff75GABbTAJdhzxJKFLKycXqvXPDqcviz OjlQmSoPk39IQIv5cYM+kiV5LLETDnsjvIltnBra0XH+LoqeBAv7jjFVZM4QfHZ+kkRK vNPMPU5XTWO/jWERa1q2eFBhfw5omN6EDKRgsWaYz+U0t9qJcQIOT0yL14xgI1K3A1c8 i4+w== X-Gm-Message-State: APjAAAU/VgU/cxp5PqriAusN+64zdnmOpCCkhOGaS7f6tah0ABam9Pkd ++PXh8DV8WCbO0V5lxyew9OgksMc X-Google-Smtp-Source: APXvYqxlhEO85aDLHrHAVDprxv1+3m5IUtOFLygycpVgyj4wi+Amnfr1rKl4h7KNy/bEnhX7rrExXw== X-Received: by 2002:adf:edd0:: with SMTP id v16mr19159284wro.357.1583108411767; Sun, 01 Mar 2020 16:20:11 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id k16sm25428417wrd.17.2020.03.01.16.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Mar 2020 16:20:11 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] spi: spi-fsl-dspi: Use specific compatible strings for all SoC instantiations Date: Mon, 2 Mar 2020 02:19:54 +0200 Message-Id: <20200302001958.11105-3-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200302001958.11105-1-olteanv@gmail.com> References: <20200302001958.11105-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean Currently, the device tree bindings submitted in mainline for Layerscape SoCs look like this: LS1021A: compatible = "fsl,ls1021a-v1.0-dspi"; LS1012A: compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; LS2085A: compatible = "fsl,ls2085a-dspi"; LS2088A: compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; LX2160A: compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; LS1043A: compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; LS1046A: compatible = "fsl,ls1021a-v1.0-dspi"; Due to a lack of a more specific compatible string, LS1012A, LS1043A and LS1046A will fall under the LS1021A umbrella, and LS2088A and LX2160A under the LS2085A umbrella. They do work in those modes, but there are slight differences in the hardware instantiations, mostly related to FIFO sizes (with the more specific compatible strings, the FIFO size can be increased properly). Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 108 +++++++++++++++++++++++++++++-------- 1 file changed, 85 insertions(+), 23 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 6ec2dcb8c57a..021c658886d4 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -133,27 +133,66 @@ struct fsl_dspi_devtype_data { bool xspi_mode; }; -static const struct fsl_dspi_devtype_data vf610_data = { - .trans_mode = DSPI_DMA_MODE, - .max_clock_factor = 2, +enum { + LS1021A, + LS1012A, + LS1043A, + LS1046A, + LS2080A, + LS2085A, + LX2160A, + MCF5441X, + VF610, }; -static const struct fsl_dspi_devtype_data ls1021a_v1_data = { - .trans_mode = DSPI_TCFQ_MODE, - .max_clock_factor = 8, - .ptp_sts_supported = true, - .xspi_mode = true, -}; - -static const struct fsl_dspi_devtype_data ls2085a_data = { - .trans_mode = DSPI_TCFQ_MODE, - .max_clock_factor = 8, - .ptp_sts_supported = true, -}; - -static const struct fsl_dspi_devtype_data coldfire_data = { - .trans_mode = DSPI_EOQ_MODE, - .max_clock_factor = 8, +static const struct fsl_dspi_devtype_data devtype_data[] = { + [VF610] = { + .trans_mode = DSPI_DMA_MODE, + .max_clock_factor = 2, + }, + [LS1021A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + .xspi_mode = true, + }, + [LS1012A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + .xspi_mode = true, + }, + [LS1043A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + .xspi_mode = true, + }, + [LS1046A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + .xspi_mode = true, + }, + [LS2080A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + }, + [LS2085A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + }, + [LX2160A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + }, + [MCF5441X] = { + .trans_mode = DSPI_EOQ_MODE, + .max_clock_factor = 8, + }, }; struct fsl_dspi_dma { @@ -909,9 +948,31 @@ static void dspi_cleanup(struct spi_device *spi) } static const struct of_device_id fsl_dspi_dt_ids[] = { - { .compatible = "fsl,vf610-dspi", .data = &vf610_data, }, - { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, }, - { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, }, + { + .compatible = "fsl,vf610-dspi", + .data = &devtype_data[VF610], + }, { + .compatible = "fsl,ls1021a-v1.0-dspi", + .data = &devtype_data[LS1021A], + }, { + .compatible = "fsl,ls1012a-dspi", + .data = &devtype_data[LS1012A], + }, { + .compatible = "fsl,ls1043a-dspi", + .data = &devtype_data[LS1043A], + }, { + .compatible = "fsl,ls1046a-dspi", + .data = &devtype_data[LS1046A], + }, { + .compatible = "fsl,ls2080a-dspi", + .data = &devtype_data[LS2080A], + }, { + .compatible = "fsl,ls2085a-dspi", + .data = &devtype_data[LS2085A], + }, { + .compatible = "fsl,lx2160a-dspi", + .data = &devtype_data[LX2160A], + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); @@ -1064,7 +1125,8 @@ static int dspi_probe(struct platform_device *pdev) ctlr->num_chipselect = pdata->cs_num; ctlr->bus_num = pdata->bus_num; - dspi->devtype_data = &coldfire_data; + /* Only Coldfire uses platform data */ + dspi->devtype_data = &devtype_data[MCF5441X]; } else { ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); From patchwork Mon Mar 2 00:19:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11414599 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6A58A17E0 for ; Mon, 2 Mar 2020 00:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4A7EF2469C for ; Mon, 2 Mar 2020 00:20:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AoQttv0F" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726928AbgCBAUR (ORCPT ); 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Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 48 ++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 021c658886d4..55ccb3d0f683 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -20,13 +20,6 @@ #define DRIVER_NAME "fsl-dspi" -#ifdef CONFIG_M5441x -#define DSPI_FIFO_SIZE 16 -#else -#define DSPI_FIFO_SIZE 4 -#endif -#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024) - #define SPI_MCR 0x00 #define SPI_MCR_MASTER BIT(31) #define SPI_MCR_PCSIS (0x3F << 16) @@ -131,6 +124,8 @@ struct fsl_dspi_devtype_data { u8 max_clock_factor; bool ptp_sts_supported; bool xspi_mode; + int fifo_size; + int dma_bufsize; }; enum { @@ -149,54 +144,64 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { [VF610] = { .trans_mode = DSPI_DMA_MODE, .max_clock_factor = 2, + .dma_bufsize = 4096, + .fifo_size = 4, }, [LS1021A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, .xspi_mode = true, + .fifo_size = 4, }, [LS1012A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, .xspi_mode = true, + .fifo_size = 16, }, [LS1043A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, .xspi_mode = true, + .fifo_size = 16, }, [LS1046A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, .xspi_mode = true, + .fifo_size = 16, }, [LS2080A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .fifo_size = 4, }, [LS2085A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .fifo_size = 4, }, [LX2160A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .fifo_size = 4, }, [MCF5441X] = { .trans_mode = DSPI_EOQ_MODE, .max_clock_factor = 8, + .fifo_size = 16, }, }; struct fsl_dspi_dma { - /* Length of transfer in words of DSPI_FIFO_SIZE */ + /* Length of transfer in words of dspi->fifo_size */ u32 curr_xfer_len; u32 *tx_dma_buf; @@ -397,7 +402,8 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi) int ret = 0; curr_remaining_bytes = dspi->len; - bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE; + bytes_per_buffer = dspi->devtype_data->dma_bufsize / + dspi->devtype_data->fifo_size; while (curr_remaining_bytes) { /* Check if current transfer fits the DMA buffer */ dma->curr_xfer_len = curr_remaining_bytes @@ -449,14 +455,14 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) goto err_tx_channel; } - dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, + dma->tx_dma_buf = dma_alloc_coherent(dev, dspi->devtype_data->dma_bufsize, &dma->tx_dma_phys, GFP_KERNEL); if (!dma->tx_dma_buf) { ret = -ENOMEM; goto err_tx_dma_buf; } - dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, + dma->rx_dma_buf = dma_alloc_coherent(dev, dspi->devtype_data->dma_bufsize, &dma->rx_dma_phys, GFP_KERNEL); if (!dma->rx_dma_buf) { ret = -ENOMEM; @@ -493,11 +499,11 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) return 0; err_slave_config: - dma_free_coherent(dev, DSPI_DMA_BUFSIZE, - dma->rx_dma_buf, dma->rx_dma_phys); + dma_free_coherent(dev, dspi->devtype_data->dma_bufsize, + dma->rx_dma_buf, dma->rx_dma_phys); err_rx_dma_buf: - dma_free_coherent(dev, DSPI_DMA_BUFSIZE, - dma->tx_dma_buf, dma->tx_dma_phys); + dma_free_coherent(dev, dspi->devtype_data->dma_bufsize, + dma->tx_dma_buf, dma->tx_dma_phys); err_tx_dma_buf: dma_release_channel(dma->chan_tx); err_tx_channel: @@ -519,13 +525,15 @@ static void dspi_release_dma(struct fsl_dspi *dspi) if (dma->chan_tx) { dma_unmap_single(dev, dma->tx_dma_phys, - DSPI_DMA_BUFSIZE, DMA_TO_DEVICE); + dspi->devtype_data->dma_bufsize, + DMA_TO_DEVICE); dma_release_channel(dma->chan_tx); } if (dma->chan_rx) { dma_unmap_single(dev, dma->rx_dma_phys, - DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE); + dspi->devtype_data->dma_bufsize, + DMA_FROM_DEVICE); dma_release_channel(dma->chan_rx); } } @@ -657,7 +665,7 @@ static void dspi_tcfq_read(struct fsl_dspi *dspi) static void dspi_eoq_write(struct fsl_dspi *dspi) { - int fifo_size = DSPI_FIFO_SIZE; + int fifo_size = dspi->devtype_data->fifo_size; u16 xfer_cmd = dspi->tx_cmd; /* Fill TX FIFO with as many transfers as possible */ @@ -667,7 +675,7 @@ static void dspi_eoq_write(struct fsl_dspi *dspi) if (dspi->len == dspi->bytes_per_word || fifo_size == 0) dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; /* Clear transfer count for first transfer in FIFO */ - if (fifo_size == (DSPI_FIFO_SIZE - 1)) + if (fifo_size == (dspi->devtype_data->fifo_size - 1)) dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; /* Write combined TX FIFO and CMD FIFO entry */ fifo_write(dspi); @@ -676,7 +684,7 @@ static void dspi_eoq_write(struct fsl_dspi *dspi) static void dspi_eoq_read(struct fsl_dspi *dspi) { - int fifo_size = DSPI_FIFO_SIZE; + int fifo_size = dspi->devtype_data->fifo_size; /* Read one FIFO entry and push to rx buffer */ while ((dspi->rx < dspi->rx_end) && fifo_size--) From patchwork Mon Mar 2 00:19:56 2020 Content-Type: text/plain; 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Sun, 01 Mar 2020 16:20:13 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id k16sm25428417wrd.17.2020.03.01.16.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Mar 2020 16:20:13 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] spi: spi-fsl-dspi: LS2080A and LX2160A support XSPI mode Date: Mon, 2 Mar 2020 02:19:56 +0200 Message-Id: <20200302001958.11105-5-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200302001958.11105-1-olteanv@gmail.com> References: <20200302001958.11105-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean XSPI allows for 2 extra features: - Command cycling (use a single TX command with more than 1 word in the TX FIFO). - Increased word size (from 16 bits to 32 bits) Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 55ccb3d0f683..d21cc5cdc8a4 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -179,6 +179,7 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .xspi_mode = true, .fifo_size = 4, }, [LS2085A] = { @@ -191,6 +192,7 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .xspi_mode = true, .fifo_size = 4, }, [MCF5441X] = { From patchwork Mon Mar 2 00:19:57 2020 Content-Type: text/plain; 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Sun, 01 Mar 2020 16:20:14 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id k16sm25428417wrd.17.2020.03.01.16.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Mar 2020 16:20:14 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] spi: spi-fsl-dspi: Support SPI software timestamping in all non-DMA modes Date: Mon, 2 Mar 2020 02:19:57 +0200 Message-Id: <20200302001958.11105-6-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200302001958.11105-1-olteanv@gmail.com> References: <20200302001958.11105-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean There's no reason to keep this .ptp_sts_supported property explicitly in devtype_data, since it can be deduced from the operating mode alone. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index d21cc5cdc8a4..c26a42f8ecbc 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -122,7 +122,6 @@ enum dspi_trans_mode { struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; - bool ptp_sts_supported; bool xspi_mode; int fifo_size; int dma_bufsize; @@ -150,48 +149,41 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { [LS1021A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 4, }, [LS1012A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 16, }, [LS1043A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 16, }, [LS1046A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 16, }, [LS2080A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 4, }, [LS2085A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .fifo_size = 4, }, [LX2160A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 4, }, @@ -1246,7 +1238,8 @@ static int dspi_probe(struct platform_device *pdev) ctlr->max_speed_hz = clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; - ctlr->ptp_sts_supported = dspi->devtype_data->ptp_sts_supported; + if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE) + ctlr->ptp_sts_supported = true; platform_set_drvdata(pdev, ctlr); From patchwork Mon Mar 2 00:19:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11414601 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD95B1395 for ; Mon, 2 Mar 2020 00:20:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8D24C24699 for ; Mon, 2 Mar 2020 00:20:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NBkqHx1v" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726728AbgCBAUb (ORCPT ); Sun, 1 Mar 2020 19:20:31 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33313 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726688AbgCBAUR (ORCPT ); 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Sun, 01 Mar 2020 16:20:15 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id k16sm25428417wrd.17.2020.03.01.16.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Mar 2020 16:20:15 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] spi: spi-fsl-dspi: Convert the instantiations that support it to DMA Date: Mon, 2 Mar 2020 02:19:58 +0200 Message-Id: <20200302001958.11105-7-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200302001958.11105-1-olteanv@gmail.com> References: <20200302001958.11105-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean The A-011218 eDMA/DSPI erratum affects most of the older Layerscape SoCs with DSPI, and its workaround is a bit intrusive. After this patch, there are no users of TCFQ mode that don't also support XSPI (previously there was LS2085A). Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index c26a42f8ecbc..c357c3247232 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -147,42 +147,49 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .fifo_size = 4, }, [LS1021A] = { + /* Has A-011218 DMA erratum */ .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 4, }, [LS1012A] = { + /* Has A-011218 DMA erratum */ .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 16, }, [LS1043A] = { + /* Has A-011218 DMA erratum */ .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 16, }, [LS1046A] = { + /* Has A-011218 DMA erratum */ .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 16, }, [LS2080A] = { - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_DMA_MODE, + .dma_bufsize = 8, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 4, }, [LS2085A] = { - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_DMA_MODE, + .dma_bufsize = 8, .max_clock_factor = 8, .fifo_size = 4, }, [LX2160A] = { - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_DMA_MODE, + .dma_bufsize = 8, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 4,