From patchwork Wed Mar 4 22:00:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420873 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 83A6A14BC for ; Wed, 4 Mar 2020 22:02:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 647C220866 for ; Wed, 4 Mar 2020 22:02:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JY1t4OZ9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388412AbgCDWCA (ORCPT ); Wed, 4 Mar 2020 17:02:00 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:44099 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727528AbgCDWB7 (ORCPT ); Wed, 4 Mar 2020 17:01:59 -0500 Received: by mail-wr1-f68.google.com with SMTP id n7so4411261wrt.11; Wed, 04 Mar 2020 14:01:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jKtUnbnCDPAHUPw1HurGDuA6lHZnQeUDjcK4VLHPbLM=; b=JY1t4OZ9N00wP7OviW2anDxcnO5bjGI1gHaeVVMg5PuqdkMibSlkP/OkrxbEEhRoL0 CvbE6Uyl6ZZcv34JaxE2uYSTI3wh4R8txNxN6oeSAEm8UUlnVEA99R6hFcqjhrzMnSOk gozg2lYI32u8NjFIZPfaDZW17hk+w8CnYc7DhsSgy96EZEHixgMTAxWpIVJ6Btlbicbu wR+peaRH46mCbjzpmHHAK8dP7aKSByFhT5b9XbHaNhzI6uI0QRkQQHYCDI397AMOxsAL iBN6bgNZ1jBY2hu3SZyKkjkbaTCHCXyiKUxzJMUabR6namwDTVaFWNZy4uJMTXzaSs13 gIkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jKtUnbnCDPAHUPw1HurGDuA6lHZnQeUDjcK4VLHPbLM=; b=Ue/SPFJD7lqZMHCGtV1CI855hblk2WYKMIbyC2rFrZJB1sjAW1M4AnlA2foLLMEqmy 4MWTUFq10Hs257vvpkfHAYIcXKzMHWJIAjrR6U2zFfxTdYOMWmjIQYYQzlragtPWnvOR DfBhWnP5bSwWcMHm4vwo+SXHZFxiYBxmXF3iWQGCryRbJiF3LWAzToayPZ8l80W+ahPs J3Kz/Jg4ab+5i4kd/CX+hK/z5tWNU3VnNeS+t4h9kqA6y5NgVqcjX9dGdR4QE5tTKeaF /1DUwYdRI/zzsrLy0s9oOJt0lWsT/DWUV0383qDinKQYMIn5OB9A3V2qXWF3jlThKrtq Tcjw== X-Gm-Message-State: ANhLgQ2WLDDmu5J04iSN9Aq7aHc3ArIEic1UqSL1gTlXnvgh7j5+Qdq+ rGZH9oM4KemHsnFKkLzU4CE= X-Google-Smtp-Source: ADFU+vvt8RSj6uUID0ESiDY4iOV6VEibME60xB1AZdc+Bn8U47ESEYs1gamcKtnt/xMrc9yozBiOjg== X-Received: by 2002:adf:b609:: with SMTP id f9mr5606100wre.380.1583359316058; Wed, 04 Mar 2020 14:01:56 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id z2sm36776402wrq.95.2020.03.04.14.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 14:01:55 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 01/12] spi: spi-fsl-dspi: Simplify bytes_per_word gymnastics Date: Thu, 5 Mar 2020 00:00:33 +0200 Message-Id: <20200304220044.11193-2-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean Reduce the if-then-else-if-then-else sequence to: - a simple division in the case of bytes_per_word calculation - a memcpy command with a variable size. The semantics of larger-than-8 xfer->bits_per_word is that those words are to be interpreted and transmitted in CPU native endianness. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index c357c3247232..896d7a0f45b0 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -252,12 +252,7 @@ static u32 dspi_pop_tx(struct fsl_dspi *dspi) u32 txdata = 0; if (dspi->tx) { - if (dspi->bytes_per_word == 1) - txdata = *(u8 *)dspi->tx; - else if (dspi->bytes_per_word == 2) - txdata = *(u16 *)dspi->tx; - else /* dspi->bytes_per_word == 4 */ - txdata = *(u32 *)dspi->tx; + memcpy(&txdata, dspi->tx, dspi->bytes_per_word); dspi->tx += dspi->bytes_per_word; } dspi->len -= dspi->bytes_per_word; @@ -284,12 +279,7 @@ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) /* Mask off undefined bits */ rxdata &= (1 << dspi->bits_per_word) - 1; - if (dspi->bytes_per_word == 1) - *(u8 *)dspi->rx = rxdata; - else if (dspi->bytes_per_word == 2) - *(u16 *)dspi->rx = rxdata; - else /* dspi->bytes_per_word == 4 */ - *(u32 *)dspi->rx = rxdata; + memcpy(dspi->rx, &rxdata, dspi->bytes_per_word); dspi->rx += dspi->bytes_per_word; } @@ -814,12 +804,7 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi->progress = 0; /* Validated transfer specific frame size (defaults applied) */ dspi->bits_per_word = transfer->bits_per_word; - if (transfer->bits_per_word <= 8) - dspi->bytes_per_word = 1; - else if (transfer->bits_per_word <= 16) - dspi->bytes_per_word = 2; - else - dspi->bytes_per_word = 4; + dspi->bytes_per_word = DIV_ROUND_UP(dspi->bits_per_word, 8); regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, From patchwork Wed Mar 4 22:00:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420871 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B639D14B7 for ; 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Wed, 04 Mar 2020 14:01:56 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 02/12] spi: spi-fsl-dspi: Remove unused chip->void_write_data Date: Thu, 5 Mar 2020 00:00:34 +0200 Message-Id: <20200304220044.11193-3-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean This variable has been present since the initial submission of the driver, and held, for some reason, the value of zero, to be sent on the wire in the case there wasn't any TX buffer for the current transfer. Since quite a while now, however, it isn't doing anything at all. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 896d7a0f45b0..63ec1d634d08 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -110,7 +110,6 @@ struct chip_data { u32 ctar_val; - u16 void_write_data; }; enum dspi_trans_mode { @@ -235,7 +234,6 @@ struct fsl_dspi { const void *tx; void *rx; void *rx_end; - u16 void_write_data; u16 tx_cmd; u8 bits_per_word; u8 bytes_per_word; @@ -795,8 +793,6 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; } - dspi->void_write_data = dspi->cur_chip->void_write_data; - dspi->tx = transfer->tx_buf; dspi->rx = transfer->rx_buf; dspi->rx_end = dspi->rx + transfer->len; @@ -897,8 +893,6 @@ static int dspi_setup(struct spi_device *spi) sck_cs_delay = pdata->sck_cs_delay; } - chip->void_write_data = 0; - clkrate = clk_get_rate(dspi->clk); hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); From patchwork Wed Mar 4 22:00:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B41421580 for ; Wed, 4 Mar 2020 22:02:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8BED820866 for ; Wed, 4 Mar 2020 22:02:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ulM5wJLA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388407AbgCDWCA (ORCPT ); Wed, 4 Mar 2020 17:02:00 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:51121 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730004AbgCDWB7 (ORCPT ); Wed, 4 Mar 2020 17:01:59 -0500 Received: by mail-wm1-f67.google.com with SMTP id a5so3980920wmb.0; Wed, 04 Mar 2020 14:01:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/fbHFCqGXzp5zp7EAhxlHDhB9irMcSYp+XI5eaxN2Bc=; b=ulM5wJLASu5uzGjV3eFR7KitNjjq/IKzwyJdEpOWHVcbsO2RLPvuHys5fjt77qMUc2 tOnlCf/SwWLppIJEWrRtqwHpqwuFcpPXg66LYNCmH6+apq0ao5dLADOjsGb/2ILnjAcE vDpeAltPaHGocWSkAjMZuhoI6CXGHd8wp/R6xBcB+78n/6gs/Izqme6Jj8GgTHNYGKPa pgdZNYOo/wMKG+51t9r+8hR9H5ylrZfawOEeIjcxPj1CAvde57KOga1Grl4hkh29vWNm SNvV44kjKr2tdG5CNARzWJ6QRUqeZhrJfuLzPxf4Q3WvseDmdL0kOd95lQCh5rQKeh9e 0oLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/fbHFCqGXzp5zp7EAhxlHDhB9irMcSYp+XI5eaxN2Bc=; b=rAWtj5CJmQXv1p6VLNFhJPi4tP+iDKmaBvd3YXTxA5x35eCR2NQhEQghy0I1DTsenJ XDAti+ruxmFkO4XgVjoKBcRG1Su5QwbCpJS8Cwsfv08ZngZr4X97BpfvkdKq7PowQczA EhIaWbELZzJLdG4yBQOBpAPxb8bGDJntXJX9FB5nPqQ9vbeg0jLZU+esJw/26HTOPM/f 4PyfLFmRI0uB9CJ2juNAST5mrRfJ+QyLzq3nm4nR6m2zX4+jg++yiAaYtnALwAAHkUEa 4LY/VJ3BNhtOXfBJ7J+HqW9pBl1Nq4qtgPh4nYjz/HuG7R0GOptTus+yw/E9M393csFt dtng== X-Gm-Message-State: ANhLgQ2j4sDUw3onw+Jlqq12J8y+qY9IN+v/elhLwj3/rTOq/D2jBXV4 oIgHkvdx34pxsO6PLNwoVcPVsqDj X-Google-Smtp-Source: ADFU+vv7HXNEhxsKZL9MYuxGEIhX/uXOWEpZ/tKRyn9GLAiHdrxsaUqW6Clz8SnIkQrUtKnR/HHuxA== X-Received: by 2002:a1c:5457:: with SMTP id p23mr5604944wmi.45.1583359318093; Wed, 04 Mar 2020 14:01:58 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id z2sm36776402wrq.95.2020.03.04.14.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 14:01:57 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 03/12] spi: spi-fsl-dspi: Don't mask off undefined bits Date: Thu, 5 Mar 2020 00:00:35 +0200 Message-Id: <20200304220044.11193-4-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean This is a useless operation, and if the driver needs to do that, there's something deeply wrong going on. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 63ec1d634d08..b92c2b84a94b 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -274,9 +274,6 @@ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) if (!dspi->rx) return; - /* Mask off undefined bits */ - rxdata &= (1 << dspi->bits_per_word) - 1; - memcpy(dspi->rx, &rxdata, dspi->bytes_per_word); dspi->rx += dspi->bytes_per_word; } From patchwork Wed Mar 4 22:00:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420869 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8520314B7 for ; Wed, 4 Mar 2020 22:02:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 665C920866 for ; Wed, 4 Mar 2020 22:02:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ajmDo6wH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388520AbgCDWCb (ORCPT ); Wed, 4 Mar 2020 17:02:31 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:51124 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388281AbgCDWCB (ORCPT ); Wed, 4 Mar 2020 17:02:01 -0500 Received: by mail-wm1-f66.google.com with SMTP id a5so3980974wmb.0; Wed, 04 Mar 2020 14:01:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T/l0focuCxU+0lWxK9yvmCbc/6KKaIJvq1+i8TBaK8g=; b=ajmDo6wH9aduuzFZRphrtOLa+jl30EGDPklWmmfDte8+9N+cSnNu0V7DXDBjipjMBU Nd+hvpvkn1ikWs6dL5YYPKKRhcNJ4B7S+cMKjXlpF9/0tDuyxPYOPbHaBKC5Ku8NSN7R /j/I8etoksIS3XMU9bB+6g6R04LcG62b6+mB/rN4OrBpSLONkvCnpRU2sI9jklPlfNJz ckPIRJZdoSWkhn4JfI+klM5119iY4HIBTUfmiGNSmEN6wlyueI8q65ykZ8Vfi0IrS/n2 oqGkDfc5IOqtG2W/Ja419uyC27HzUwnZwIewtxpYVR+lVjPx9SgSpDuL/MBwp5ccN/kd dYBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T/l0focuCxU+0lWxK9yvmCbc/6KKaIJvq1+i8TBaK8g=; b=WO++NQ3YIK2VpxoE+HwrrPIk1YBobRkENFOBhqHrhHnHt/mnnS8rZaLYsvdwgQtA0p VANK2Q4buTHUuD51sdbVYq5ycyKgoEX1CagYME6nKsRkvnUnnFx8VIs22vdAgYaiMxIJ CsqEi8W1gM3IbLG02tov/YLR35mSBNuioL3qpypwGqsSq7Vb2ZhYRTPHXf9JMEF2RLaY fWxgd7Nb04nMkSXUX6BTKgaDCU2Az2yXxCzWHdUjCle6BFo0oZDMX2jdTiK4G8kjZf5i nWcjR4jq8hq+mwztzD1GI/IUSNinKUG9uh3s6gX2GRn23/mZwvAPuVjlHjnuuhJGn/uK D72Q== X-Gm-Message-State: ANhLgQ0g3Ep8HQFy0rsZerCAXtKb5oNAzzhG1VIKsmC+Jb/wsUD2DGr4 sR+SlHaqzIkbNUdKeQr56X+00ayb X-Google-Smtp-Source: ADFU+vtLjzFP70YoMuO9LYP02avhUML631vsNZch4eudLOzu7eOEacvy5fJcyroV37UmvHxi6oDc+A== X-Received: by 2002:a1c:e206:: with SMTP id z6mr5184526wmg.141.1583359319182; Wed, 04 Mar 2020 14:01:59 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id z2sm36776402wrq.95.2020.03.04.14.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 14:01:58 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 04/12] spi: spi-fsl-dspi: Add comments around dspi_pop_tx and dspi_push_rx functions Date: Thu, 5 Mar 2020 00:00:36 +0200 Message-Id: <20200304220044.11193-5-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean Their names are confusing, since dspi_pop_tx prepares a word to be written to the PUSHR register, and dspi_push_rx gets a word from the POPR register. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index b92c2b84a94b..a8077d4903c7 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -245,6 +245,10 @@ struct fsl_dspi { struct fsl_dspi_dma *dma; }; +/* + * Pop one word from the TX buffer for pushing into the + * PUSHR register (TX FIFO) + */ static u32 dspi_pop_tx(struct fsl_dspi *dspi) { u32 txdata = 0; @@ -257,6 +261,7 @@ static u32 dspi_pop_tx(struct fsl_dspi *dspi) return txdata; } +/* Prepare one TX FIFO entry (txdata plus cmd) */ static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) { u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi); @@ -269,6 +274,7 @@ static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) return cmd << 16 | data; } +/* Push one word to the RX buffer from the POPR register (RX FIFO) */ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) { if (!dspi->rx) From patchwork Wed Mar 4 22:00:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420867 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B2C314B7 for ; Wed, 4 Mar 2020 22:02:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E0F002084E for ; Wed, 4 Mar 2020 22:02:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="J4SVbPYS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388503AbgCDWCC (ORCPT ); Wed, 4 Mar 2020 17:02:02 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:55887 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388483AbgCDWCB (ORCPT ); Wed, 4 Mar 2020 17:02:01 -0500 Received: by mail-wm1-f66.google.com with SMTP id 6so3981242wmi.5; Wed, 04 Mar 2020 14:02:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7usjeEtnLelRZFqfBWE5WZWkvf+bS5tSXzwRcAo6Mj8=; b=J4SVbPYSzmVam37DjyguQpOymuECa5BijnCH9xLTjm92LsrT3Bqp9T59mK4qpqEmpv NFipA1l0LfQhwwWZO8TNynkv4OeU18HB4lAi5DtMesOGeTxc9anMMw2+4TqyaV19XCv+ lRAKsQDzrkSZUJQPTbn25mll9LiIU9vKUySc0T7UcBuIDeQ1BrJ6hlLNumuXbFyDSpfO zlPKrAKhlVrZV4EuQIOvxvO+XiBU/wVv7kst3v6wO4tXsEGUYzC0SZPCQIgwWVpPQZon Rz5IFpVnSlbWMpoRFrINm/AmQvLUzagy395sQvEQjMy3a9XJjPAysaIDbQhfg1lEaq3o nz/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7usjeEtnLelRZFqfBWE5WZWkvf+bS5tSXzwRcAo6Mj8=; b=KRgkzD45FSBnOymw91q5C7n+/Y6RdX2Ii5HH4VrmKX+JCN/zMXDzt4Rj+dAbkcdAJb ctliom3/pZ+iXHTpIjBrNrcDzCptAYYJNNoXJpT5+4b+6lCkyXxtgW+MK75uyK7Wt2yq n0/UVB1xoAp9SOAEGHkHSCpFoeqlJq9y0p0ui5dL4d5X/WZpveK3A5l6oQctc4Cwm25Y 6vwe8w5vPvtTMM4Tnc9XqZCYhS6RYuQvQLnfsIetJNIypKpfJbQcRmbixl713EyOKspx AQ3yuoBBSbvM7VLU8Z4uZTEDDWiUwiOVybz2UL9p7ZwrEycW//cQGkkMqE/OA5lp1pZH IG5A== X-Gm-Message-State: ANhLgQ113RLmoCU3UviFpf9btiOa6RGZRuzi9Yg27CTA9b7qVjOyYu5A cxTT5XAuytrBHxkz6nMWfAw= X-Google-Smtp-Source: ADFU+vs6REbQIkGOj+OTlmaB4siXuM1v/v23pW3AjDLVW6ldBzqWTtmjYTqUJXJ912bqGN/BwDSPng== X-Received: by 2002:a1c:4805:: with SMTP id v5mr5575917wma.80.1583359320233; Wed, 04 Mar 2020 14:02:00 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id z2sm36776402wrq.95.2020.03.04.14.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 14:01:59 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 05/12] spi: spi-fsl-dspi: Rename fifo_{read,write} and {tx,cmd}_fifo_write Date: Thu, 5 Mar 2020 00:00:37 +0200 Message-Id: <20200304220044.11193-6-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean These function names are very generic and it is easy to get confused. Rename them after the hardware register that they are accessing. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index a8077d4903c7..f37090ad7ad1 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -601,12 +601,12 @@ static void ns_delay_scale(char *psc, char *sc, int delay_ns, } } -static void fifo_write(struct fsl_dspi *dspi) +static void dspi_pushr_write(struct fsl_dspi *dspi) { regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); } -static void cmd_fifo_write(struct fsl_dspi *dspi) +static void dspi_pushr_cmd_write(struct fsl_dspi *dspi) { u16 cmd = dspi->tx_cmd; @@ -615,7 +615,7 @@ static void cmd_fifo_write(struct fsl_dspi *dspi) regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); } -static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata) +static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) { regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); } @@ -631,18 +631,18 @@ static void dspi_tcfq_write(struct fsl_dspi *dspi) */ u32 data = dspi_pop_tx(dspi); - cmd_fifo_write(dspi); - tx_fifo_write(dspi, data & 0xFFFF); - tx_fifo_write(dspi, data >> 16); + dspi_pushr_cmd_write(dspi); + dspi_pushr_txdata_write(dspi, data & 0xFFFF); + dspi_pushr_txdata_write(dspi, data >> 16); } else { /* Write one entry to both TX FIFO and CMD FIFO * simultaneously. */ - fifo_write(dspi); + dspi_pushr_write(dspi); } } -static u32 fifo_read(struct fsl_dspi *dspi) +static u32 dspi_popr_read(struct fsl_dspi *dspi) { u32 rxdata = 0; @@ -652,7 +652,7 @@ static u32 fifo_read(struct fsl_dspi *dspi) static void dspi_tcfq_read(struct fsl_dspi *dspi) { - dspi_push_rx(dspi, fifo_read(dspi)); + dspi_push_rx(dspi, dspi_popr_read(dspi)); } static void dspi_eoq_write(struct fsl_dspi *dspi) @@ -670,7 +670,7 @@ static void dspi_eoq_write(struct fsl_dspi *dspi) if (fifo_size == (dspi->devtype_data->fifo_size - 1)) dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; /* Write combined TX FIFO and CMD FIFO entry */ - fifo_write(dspi); + dspi_pushr_write(dspi); } } @@ -680,7 +680,7 @@ static void dspi_eoq_read(struct fsl_dspi *dspi) /* Read one FIFO entry and push to rx buffer */ while ((dspi->rx < dspi->rx_end) && fifo_size--) - dspi_push_rx(dspi, fifo_read(dspi)); + dspi_push_rx(dspi, dspi_popr_read(dspi)); } static int dspi_rxtx(struct fsl_dspi *dspi) From patchwork Wed Mar 4 22:00:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420863 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3CCA214B7 for ; Wed, 4 Mar 2020 22:02:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1DDF12084E for ; Wed, 4 Mar 2020 22:02:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="q6JSMBlI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388519AbgCDWCF (ORCPT ); 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This operating mode is not ideal, but it is used for the DSPI instantiations where there is no other notification from the controller that the data in the FIFO has finished transmission. So in practice, it means that transmitting buffers larger than the FIFO size will yield unpredictable results. The only controller that operates in EOQ mode is MCF5441X (Coldfire). I would say that the way EOQ is used (and documented in the reference manual, too) on this chip is incorrect, and I would personally migrate it to TCFQ, but that's notably worse in terms of performance (it can only use 1 entry of the 16-deep FIFO) and if this limitation didn't bother any Coldfire DSPI user so far, it's likely that we just need to throw an error for larger buffers to make sure that callers are aware their transfers are getting truncated/split. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index f37090ad7ad1..158cb48c0f4a 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1084,6 +1084,22 @@ static int dspi_slave_abort(struct spi_master *master) return 0; } +/* + * EOQ mode will inevitably deassert its PCS signal on last word in a queue + * (hardware limitation), so we need to inform the spi_device that larger + * buffers than the FIFO size are going to have the chip select randomly + * toggling, so it has a chance to adapt its message sizes. + */ +static size_t dspi_max_message_size(struct spi_device *spi) +{ + struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller); + + if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) + return dspi->devtype_data->fifo_size; + + return SIZE_MAX; +} + static int dspi_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -1105,6 +1121,7 @@ static int dspi_probe(struct platform_device *pdev) ctlr->setup = dspi_setup; ctlr->transfer_one_message = dspi_transfer_one_message; + ctlr->max_message_size = dspi_max_message_size; ctlr->dev.of_node = pdev->dev.of_node; ctlr->cleanup = dspi_cleanup; From patchwork Wed Mar 4 22:00:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420865 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4EA11580 for ; Wed, 4 Mar 2020 22:02:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A59F12084E for ; Wed, 4 Mar 2020 22:02:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QHiaPdts" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388515AbgCDWCF (ORCPT ); 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This happens because the function currently expects to be called with the "progress" argument >= to what the peripheral has requested to be timestamped. But clearly there are cases when that isn't going to fly. And since we can't change the past when we realize that the opportunity to take a "pre" timestamp has just passed and there isn't going to be another one, the approach taken is to keep recording the "pre" timestamp on each call, overwriting the previously recorded one until the "post" timestamp is also taken. Signed-off-by: Vladimir Oltean --- drivers/spi/spi.c | 19 +++++++------------ include/linux/spi/spi.h | 3 +-- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index a8495fd3bb47..22baf204a09d 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1515,17 +1515,15 @@ void spi_take_timestamp_pre(struct spi_controller *ctlr, if (!xfer->ptp_sts) return; - if (xfer->timestamped_pre) + if (xfer->timestamped) return; - if (progress < xfer->ptp_sts_word_pre) + if (progress > xfer->ptp_sts_word_pre) return; /* Capture the resolution of the timestamp */ xfer->ptp_sts_word_pre = progress; - xfer->timestamped_pre = true; - if (irqs_off) { local_irq_save(ctlr->irq_flags); preempt_disable(); @@ -1554,7 +1552,7 @@ void spi_take_timestamp_post(struct spi_controller *ctlr, if (!xfer->ptp_sts) return; - if (xfer->timestamped_post) + if (xfer->timestamped) return; if (progress < xfer->ptp_sts_word_post) @@ -1570,7 +1568,7 @@ void spi_take_timestamp_post(struct spi_controller *ctlr, /* Capture the resolution of the timestamp */ xfer->ptp_sts_word_post = progress; - xfer->timestamped_post = true; + xfer->timestamped = true; } EXPORT_SYMBOL_GPL(spi_take_timestamp_post); @@ -1675,12 +1673,9 @@ void spi_finalize_current_message(struct spi_controller *ctlr) } } - if (unlikely(ctlr->ptp_sts_supported)) { - list_for_each_entry(xfer, &mesg->transfers, transfer_list) { - WARN_ON_ONCE(xfer->ptp_sts && !xfer->timestamped_pre); - WARN_ON_ONCE(xfer->ptp_sts && !xfer->timestamped_post); - } - } + if (unlikely(ctlr->ptp_sts_supported)) + list_for_each_entry(xfer, &mesg->transfers, transfer_list) + WARN_ON_ONCE(xfer->ptp_sts && !xfer->timestamped); spi_unmap_msg(ctlr, mesg); diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 600e3793303e..87105272879b 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -933,8 +933,7 @@ struct spi_transfer { struct ptp_system_timestamp *ptp_sts; - bool timestamped_pre; - bool timestamped_post; + bool timestamped; struct list_head transfer_list; }; From patchwork Wed Mar 4 22:00:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420861 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6734B1580 for ; Wed, 4 Mar 2020 22:02:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 379D62084E for ; Wed, 4 Mar 2020 22:02:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rghochqb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388572AbgCDWCT (ORCPT ); Wed, 4 Mar 2020 17:02:19 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:42576 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388523AbgCDWCG (ORCPT ); Wed, 4 Mar 2020 17:02:06 -0500 Received: by mail-wr1-f67.google.com with SMTP id v11so2482169wrm.9; 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Wed, 04 Mar 2020 14:02:03 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id z2sm36776402wrq.95.2020.03.04.14.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 14:02:03 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 08/12] spi: spi-fsl-dspi: Convert TCFQ users to XSPI FIFO mode Date: Thu, 5 Mar 2020 00:00:40 +0200 Message-Id: <20200304220044.11193-9-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean The Transfer Complete Flag (TCF) interrupt gets raised after each write to the TX FIFO (PUSHR) which means that it is not possible to devise a transfer procedure that makes full utilization of the FIFO depth (4 entries on most controllers, 16 entries on some). On the other hand, XSPI mode has a feature called "command cycling", which allows a single TX command to be run for a pre-specified number of TX words. When the command cycle ends, the Command Transfer Complete Flag bit asserts and raises an interrupt. The advantage in this mode is that the TX FIFO can be better utilized (more words can be batched at once). Other changes brought by this patch: - The dspi->rx_end variable has been removed, since now the dspi_fifo_write function sets up dspi->words_in_flight, so dspi_fifo_read knows how much to read without overrunning the RX buffer. - Stop using poll mode unconditionally for TCFQ mode, since XSPI mode is a little less efficient than that, and so, poll mode doesn't bring as many improvements for XSPI. - Stop relying on the hardware transfer counter (SPI_TCR_GET_TCNT) and instead increment the message->actual_length based on the newly introduced dspi->words_in_flight variable. - The CTARE register is now written in the hotpath instead of just at transfer init time, since it contains the DTCP field (transfer preload - the counter indicating how many txdata words will follow), which is a dynamic value. Due to the fact that the Chip Select toggling setting is part of the command written to the TX FIFO, the ending word of each buffer needs to be sent via its own TX command, so that we have a chance to emit a 1-word command with deasserted PCS. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 189 ++++++++++++++++++++----------------- 1 file changed, 101 insertions(+), 88 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 158cb48c0f4a..298c22def165 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -72,6 +72,7 @@ #define SPI_RSER 0x30 #define SPI_RSER_TCFQE BIT(31) #define SPI_RSER_EOQFE BIT(28) +#define SPI_RSER_CMDTCFE BIT(23) #define SPI_PUSHR 0x34 #define SPI_PUSHR_CMD_CONT BIT(15) @@ -114,14 +115,13 @@ struct chip_data { enum dspi_trans_mode { DSPI_EOQ_MODE = 0, - DSPI_TCFQ_MODE, + DSPI_XSPI_MODE, DSPI_DMA_MODE, }; struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; - bool xspi_mode; int fifo_size; int dma_bufsize; }; @@ -147,37 +147,32 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { }, [LS1021A] = { /* Has A-011218 DMA erratum */ - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 4, }, [LS1012A] = { /* Has A-011218 DMA erratum */ - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 16, }, [LS1043A] = { /* Has A-011218 DMA erratum */ - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 16, }, [LS1046A] = { /* Has A-011218 DMA erratum */ - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 16, }, [LS2080A] = { .trans_mode = DSPI_DMA_MODE, .dma_bufsize = 8, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 4, }, [LS2085A] = { @@ -190,7 +185,6 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .trans_mode = DSPI_DMA_MODE, .dma_bufsize = 8, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 4, }, [MCF5441X] = { @@ -233,7 +227,6 @@ struct fsl_dspi { size_t len; const void *tx; void *rx; - void *rx_end; u16 tx_cmd; u8 bits_per_word; u8 bytes_per_word; @@ -243,6 +236,8 @@ struct fsl_dspi { u32 waitflags; struct fsl_dspi_dma *dma; + + int words_in_flight; }; /* @@ -610,7 +605,17 @@ static void dspi_pushr_cmd_write(struct fsl_dspi *dspi) { u16 cmd = dspi->tx_cmd; - if (dspi->len > 0) + /* + * The only time when the PCS doesn't need continuation after this word + * is when it's last. We need to look ahead, because we actually call + * dspi_pop_tx (the function that decrements dspi->len) _after_ + * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One + * word is enough. If there's more to transmit than that, + * dspi_xspi_write will know to split the FIFO writes in 2, and + * generate a new PUSHR command with the final word that will have PCS + * deasserted (not continued) here. + */ + if (dspi->len > dspi->bytes_per_word) cmd |= SPI_PUSHR_CMD_CONT; regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); } @@ -620,93 +625,115 @@ static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); } -static void dspi_tcfq_write(struct fsl_dspi *dspi) +static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) { - /* Clear transfer count */ - dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; + regmap_write(dspi->regmap, SPI_CTARE(0), + SPI_FRAME_EBITS(dspi->bits_per_word) | + SPI_CTARE_DTCP(cnt)); - if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) { - /* Write the CMD FIFO entry first, and then the two - * corresponding TX FIFO entries. - */ + /* + * Write the CMD FIFO entry first, and then the two + * corresponding TX FIFO entries (or one...). + */ + dspi_pushr_cmd_write(dspi); + + /* Fill TX FIFO with as many transfers as possible */ + while (cnt--) { u32 data = dspi_pop_tx(dspi); - dspi_pushr_cmd_write(dspi); dspi_pushr_txdata_write(dspi, data & 0xFFFF); - dspi_pushr_txdata_write(dspi, data >> 16); - } else { - /* Write one entry to both TX FIFO and CMD FIFO - * simultaneously. - */ - dspi_pushr_write(dspi); + if (dspi->bits_per_word > 16) + dspi_pushr_txdata_write(dspi, data >> 16); } } -static u32 dspi_popr_read(struct fsl_dspi *dspi) +static void dspi_xspi_fifo_write(struct fsl_dspi *dspi) { - u32 rxdata = 0; + int num_fifo_entries = dspi->devtype_data->fifo_size; + int bytes_in_flight; - regmap_read(dspi->regmap, SPI_POPR, &rxdata); - return rxdata; -} + /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ + if (dspi->bits_per_word > 16) + num_fifo_entries /= 2; -static void dspi_tcfq_read(struct fsl_dspi *dspi) -{ - dspi_push_rx(dspi, dspi_popr_read(dspi)); + dspi->words_in_flight = dspi->len / dspi->bytes_per_word; + + if (dspi->words_in_flight > num_fifo_entries) + dspi->words_in_flight = num_fifo_entries; + + bytes_in_flight = dspi->words_in_flight * dspi->bytes_per_word; + + /* + * If the PCS needs to de-assert (i.e. we're at the end of the buffer + * and cs_change does not want the PCS to stay on), then we need a new + * PUSHR command, since this one (for the body of the buffer) + * necessarily has the CONT bit set. + * So send one word less during this go, to force a split and a command + * with a single word next time, when CONT will be unset. + */ + if (bytes_in_flight == dspi->len && dspi->words_in_flight > 1 && + !(dspi->tx_cmd & SPI_PUSHR_CMD_CONT)) + dspi->words_in_flight--; + + dspi_xspi_write(dspi, dspi->words_in_flight); } -static void dspi_eoq_write(struct fsl_dspi *dspi) +static void dspi_eoq_fifo_write(struct fsl_dspi *dspi) { - int fifo_size = dspi->devtype_data->fifo_size; + int num_fifo_entries = dspi->devtype_data->fifo_size; u16 xfer_cmd = dspi->tx_cmd; + dspi->words_in_flight = num_fifo_entries; + /* Fill TX FIFO with as many transfers as possible */ - while (dspi->len && fifo_size--) { + while (dspi->len && num_fifo_entries--) { dspi->tx_cmd = xfer_cmd; /* Request EOQF for last transfer in FIFO */ - if (dspi->len == dspi->bytes_per_word || fifo_size == 0) + if (dspi->len == dspi->bytes_per_word || num_fifo_entries == 0) dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; - /* Clear transfer count for first transfer in FIFO */ - if (fifo_size == (dspi->devtype_data->fifo_size - 1)) - dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; /* Write combined TX FIFO and CMD FIFO entry */ dspi_pushr_write(dspi); } } -static void dspi_eoq_read(struct fsl_dspi *dspi) +static u32 dspi_popr_read(struct fsl_dspi *dspi) { - int fifo_size = dspi->devtype_data->fifo_size; + u32 rxdata = 0; + regmap_read(dspi->regmap, SPI_POPR, &rxdata); + return rxdata; +} + +static void dspi_fifo_read(struct fsl_dspi *dspi) +{ /* Read one FIFO entry and push to rx buffer */ - while ((dspi->rx < dspi->rx_end) && fifo_size--) + while (dspi->words_in_flight--) dspi_push_rx(dspi, dspi_popr_read(dspi)); } +static void dspi_fifo_write(struct fsl_dspi *dspi) +{ + if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) + dspi_eoq_fifo_write(dspi); + else + dspi_xspi_fifo_write(dspi); +} + static int dspi_rxtx(struct fsl_dspi *dspi) { + struct spi_transfer *xfer = dspi->cur_transfer; struct spi_message *msg = dspi->cur_msg; - enum dspi_trans_mode trans_mode; - u16 spi_tcnt; - u32 spi_tcr; + int bytes_sent; + + /* Update total number of bytes that were transferred */ + bytes_sent = dspi->words_in_flight * dspi->bytes_per_word; + msg->actual_length += bytes_sent; + dspi->progress += bytes_sent / DIV_ROUND_UP(xfer->bits_per_word, 8); spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); - /* Get transfer counter (in number of SPI transfers). It was - * reset to 0 when transfer(s) were started. - */ - regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); - spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); - /* Update total number of bytes that were transferred */ - msg->actual_length += spi_tcnt * dspi->bytes_per_word; - dspi->progress += spi_tcnt; - - trans_mode = dspi->devtype_data->trans_mode; - if (trans_mode == DSPI_EOQ_MODE) - dspi_eoq_read(dspi); - else if (trans_mode == DSPI_TCFQ_MODE) - dspi_tcfq_read(dspi); + dspi_fifo_read(dspi); if (!dspi->len) /* Success! */ @@ -715,10 +742,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi) spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); - if (trans_mode == DSPI_EOQ_MODE) - dspi_eoq_write(dspi); - else if (trans_mode == DSPI_TCFQ_MODE) - dspi_tcfq_write(dspi); + dspi_fifo_write(dspi); return -EINPROGRESS; } @@ -732,7 +756,7 @@ static int dspi_poll(struct fsl_dspi *dspi) regmap_read(dspi->regmap, SPI_SR, &spi_sr); regmap_write(dspi->regmap, SPI_SR, spi_sr); - if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) + if (spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF)) break; } while (--tries); @@ -750,7 +774,7 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id) regmap_read(dspi->regmap, SPI_SR, &spi_sr); regmap_write(dspi->regmap, SPI_SR, spi_sr); - if (!(spi_sr & SPI_SR_EOQF)) + if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF))) return IRQ_NONE; if (dspi_rxtx(dspi) == 0) { @@ -798,7 +822,6 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi->tx = transfer->tx_buf; dspi->rx = transfer->rx_buf; - dspi->rx_end = dspi->rx + transfer->len; dspi->len = transfer->len; dspi->progress = 0; /* Validated transfer specific frame size (defaults applied) */ @@ -811,10 +834,6 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, regmap_write(dspi->regmap, SPI_CTAR(0), dspi->cur_chip->ctar_val | SPI_FRAME_BITS(transfer->bits_per_word)); - if (dspi->devtype_data->xspi_mode) - regmap_write(dspi->regmap, SPI_CTARE(0), - SPI_FRAME_EBITS(transfer->bits_per_word) | - SPI_CTARE_DTCP(1)); spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); @@ -823,11 +842,11 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, switch (trans_mode) { case DSPI_EOQ_MODE: regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); - dspi_eoq_write(dspi); + dspi_fifo_write(dspi); break; - case DSPI_TCFQ_MODE: - regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); - dspi_tcfq_write(dspi); + case DSPI_XSPI_MODE: + regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); + dspi_fifo_write(dspi); break; case DSPI_DMA_MODE: regmap_write(dspi->regmap, SPI_RSER, @@ -1053,16 +1072,13 @@ static void dspi_init(struct fsl_dspi *dspi) { unsigned int mcr = SPI_MCR_PCSIS; - if (dspi->devtype_data->xspi_mode) + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) mcr |= SPI_MCR_XSPI; if (!spi_controller_is_slave(dspi->ctlr)) mcr |= SPI_MCR_MASTER; regmap_write(dspi->regmap, SPI_MCR, mcr); regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); - if (dspi->devtype_data->xspi_mode) - regmap_write(dspi->regmap, SPI_CTARE(0), - SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1)); } static int dspi_slave_abort(struct spi_master *master) @@ -1162,7 +1178,7 @@ static int dspi_probe(struct platform_device *pdev) } } - if (dspi->devtype_data->xspi_mode) + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); else ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); @@ -1174,7 +1190,7 @@ static int dspi_probe(struct platform_device *pdev) goto out_ctlr_put; } - if (dspi->devtype_data->xspi_mode) + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) regmap_config = &dspi_xspi_regmap_config[0]; else regmap_config = &dspi_regmap_config; @@ -1186,7 +1202,7 @@ static int dspi_probe(struct platform_device *pdev) goto out_ctlr_put; } - if (dspi->devtype_data->xspi_mode) { + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) { dspi->regmap_pushr = devm_regmap_init_mmio( &pdev->dev, base + SPI_PUSHR, &dspi_xspi_regmap_config[1]); @@ -1211,9 +1227,6 @@ static int dspi_probe(struct platform_device *pdev) dspi_init(dspi); - if (dspi->devtype_data->trans_mode == DSPI_TCFQ_MODE) - goto poll_mode; - dspi->irq = platform_get_irq(pdev, 0); if (dspi->irq <= 0) { dev_info(&pdev->dev, From patchwork Wed Mar 4 22:00:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420859 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B17C514BC for ; Wed, 4 Mar 2020 22:02:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7FA8A2084E for ; Wed, 4 Mar 2020 22:02:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aLYXLLt2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388577AbgCDWCT (ORCPT ); Wed, 4 Mar 2020 17:02:19 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:45848 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388520AbgCDWCG (ORCPT ); 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Wed, 04 Mar 2020 14:02:04 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id z2sm36776402wrq.95.2020.03.04.14.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 14:02:04 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 09/12] spi: spi-fsl-dspi: Accelerate transfers using larger word size if possible Date: Thu, 5 Mar 2020 00:00:41 +0200 Message-Id: <20200304220044.11193-10-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean This patch adds logic in the driver to transmit SPI buffers that use bits_per_word=8 with a higher bits_per_word count (multiple of 8). Currently the following (most common) modes are implemented: - 8 bits_per_word on 32-bit capable controllers - 8 bits_per_word on 16-bit capable controllers - 16 bits_per_word on 32-bit capable controllers Transfers which are not accelerated are transferred with a hardware bits_per_word value equal to the one of the SPI transfer. The difference from just extending bits_per_word=32 at the spi_device driver level is that endianness is different - the SPI core wants to treat bits_per_word=32 buffers as arrays of u32 (i.e. words in host CPU endianness). So to preserve endianness when clumping 8x4 bits into 32-bit words, one must perform conversion between CPU and standard (big) endianness. All appearances (both on the wire as well as in the buffers presented to the peripheral driver) are preserved, just that accesses to the PUSHR and POPR registers are now more efficient, since the same number of reads/writes can now carry more data (2x more data on TX, 4x more data on RX). Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 160 +++++++++++++++++++++++++++++++------ 1 file changed, 135 insertions(+), 25 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 298c22def165..f5b802070d29 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -228,8 +228,6 @@ struct fsl_dspi { const void *tx; void *rx; u16 tx_cmd; - u8 bits_per_word; - u8 bytes_per_word; const struct fsl_dspi_devtype_data *devtype_data; wait_queue_head_t waitq; @@ -237,9 +235,70 @@ struct fsl_dspi { struct fsl_dspi_dma *dma; + int oper_word_size; + int oper_bits_per_word; + int words_in_flight; + + void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata); + void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); }; +static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) +{ + memcpy(txdata, dspi->tx, dspi->oper_word_size); + dspi->tx += dspi->oper_word_size; +} + +static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) +{ + memcpy(dspi->rx, &rxdata, dspi->oper_word_size); + dspi->rx += dspi->oper_word_size; +} + +static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) +{ + *txdata = cpu_to_be32(*(u32 *)dspi->tx); + dspi->tx += sizeof(u32); +} + +static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) +{ + *(u32 *)dspi->rx = be32_to_cpu(rxdata); + dspi->rx += sizeof(u32); +} + +static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) +{ + *txdata = cpu_to_be16(*(u16 *)dspi->tx); + dspi->tx += sizeof(u16); +} + +static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) +{ + *(u16 *)dspi->rx = be16_to_cpu(rxdata); + dspi->rx += sizeof(u16); +} + +static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) +{ + u16 hi = *(u16 *)dspi->tx; + u16 lo = *(u16 *)(dspi->tx + 2); + + *txdata = (u32)hi << 16 | lo; + dspi->tx += sizeof(u32); +} + +static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) +{ + u16 hi = rxdata & 0xffff; + u16 lo = rxdata >> 16; + + *(u16 *)dspi->rx = lo; + *(u16 *)(dspi->rx + 2) = hi; + dspi->rx += sizeof(u32); +} + /* * Pop one word from the TX buffer for pushing into the * PUSHR register (TX FIFO) @@ -248,11 +307,9 @@ static u32 dspi_pop_tx(struct fsl_dspi *dspi) { u32 txdata = 0; - if (dspi->tx) { - memcpy(&txdata, dspi->tx, dspi->bytes_per_word); - dspi->tx += dspi->bytes_per_word; - } - dspi->len -= dspi->bytes_per_word; + if (dspi->tx) + dspi->host_to_dev(dspi, &txdata); + dspi->len -= dspi->oper_word_size; return txdata; } @@ -274,9 +331,7 @@ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) { if (!dspi->rx) return; - - memcpy(dspi->rx, &rxdata, dspi->bytes_per_word); - dspi->rx += dspi->bytes_per_word; + dspi->dev_to_host(dspi, rxdata); } static void dspi_tx_dma_callback(void *arg) @@ -393,8 +448,8 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi) dspi->devtype_data->fifo_size; while (curr_remaining_bytes) { /* Check if current transfer fits the DMA buffer */ - dma->curr_xfer_len = curr_remaining_bytes - / dspi->bytes_per_word; + dma->curr_xfer_len = curr_remaining_bytes / + dspi->oper_word_size; if (dma->curr_xfer_len > bytes_per_buffer) dma->curr_xfer_len = bytes_per_buffer; @@ -404,8 +459,8 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi) goto exit; } else { - const int len = - dma->curr_xfer_len * dspi->bytes_per_word; + const int len = dma->curr_xfer_len * + dspi->oper_word_size; curr_remaining_bytes -= len; message->actual_length += len; if (curr_remaining_bytes < 0) @@ -615,7 +670,7 @@ static void dspi_pushr_cmd_write(struct fsl_dspi *dspi) * generate a new PUSHR command with the final word that will have PCS * deasserted (not continued) here. */ - if (dspi->len > dspi->bytes_per_word) + if (dspi->len > dspi->oper_word_size) cmd |= SPI_PUSHR_CMD_CONT; regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); } @@ -627,8 +682,9 @@ static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) { + /* Update CTARE */ regmap_write(dspi->regmap, SPI_CTARE(0), - SPI_FRAME_EBITS(dspi->bits_per_word) | + SPI_FRAME_EBITS(dspi->oper_bits_per_word) | SPI_CTARE_DTCP(cnt)); /* @@ -642,7 +698,7 @@ static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) u32 data = dspi_pop_tx(dspi); dspi_pushr_txdata_write(dspi, data & 0xFFFF); - if (dspi->bits_per_word > 16) + if (dspi->oper_bits_per_word > 16) dspi_pushr_txdata_write(dspi, data >> 16); } } @@ -653,15 +709,20 @@ static void dspi_xspi_fifo_write(struct fsl_dspi *dspi) int bytes_in_flight; /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ - if (dspi->bits_per_word > 16) + if (dspi->oper_word_size == 4) num_fifo_entries /= 2; - dspi->words_in_flight = dspi->len / dspi->bytes_per_word; + /* + * Integer division intentionally trims off odd (or non-multiple of 4) + * numbers of bytes at the end of the buffer, which will be sent next + * time using a smaller oper_word_size. + */ + dspi->words_in_flight = dspi->len / dspi->oper_word_size; if (dspi->words_in_flight > num_fifo_entries) dspi->words_in_flight = num_fifo_entries; - bytes_in_flight = dspi->words_in_flight * dspi->bytes_per_word; + bytes_in_flight = dspi->words_in_flight * dspi->oper_word_size; /* * If the PCS needs to de-assert (i.e. we're at the end of the buffer @@ -689,7 +750,7 @@ static void dspi_eoq_fifo_write(struct fsl_dspi *dspi) while (dspi->len && num_fifo_entries--) { dspi->tx_cmd = xfer_cmd; /* Request EOQF for last transfer in FIFO */ - if (dspi->len == dspi->bytes_per_word || num_fifo_entries == 0) + if (dspi->len == dspi->oper_word_size || num_fifo_entries == 0) dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; /* Write combined TX FIFO and CMD FIFO entry */ dspi_pushr_write(dspi); @@ -711,8 +772,56 @@ static void dspi_fifo_read(struct fsl_dspi *dspi) dspi_push_rx(dspi, dspi_popr_read(dspi)); } +static void dspi_setup_accel(struct fsl_dspi *dspi) +{ + struct spi_transfer *xfer = dspi->cur_transfer; + + /* Start off with maximum supported by hardware */ + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) + dspi->oper_bits_per_word = 32; + else + dspi->oper_bits_per_word = 16; + + /* And go down only if the buffer can't be sent with words this big */ + do { + if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8)) + break; + + dspi->oper_bits_per_word /= 2; + } while (dspi->oper_bits_per_word > 8); + + if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) { + dspi->dev_to_host = dspi_8on32_dev_to_host; + dspi->host_to_dev = dspi_8on32_host_to_dev; + } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) { + dspi->dev_to_host = dspi_8on16_dev_to_host; + dspi->host_to_dev = dspi_8on16_host_to_dev; + } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) { + dspi->dev_to_host = dspi_16on32_dev_to_host; + dspi->host_to_dev = dspi_16on32_host_to_dev; + } else { + /* No acceleration needed (8dev_to_host = dspi_native_dev_to_host; + dspi->host_to_dev = dspi_native_host_to_dev; + dspi->oper_bits_per_word = xfer->bits_per_word; + } + + dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8); + + /* + * Update CTAR here (code is common for both EOQ and XSPI modes). + * We will update CTARE in the portion specific to XSPI, when we + * also know the preload value (DTCP). + */ + regmap_write(dspi->regmap, SPI_CTAR(0), + dspi->cur_chip->ctar_val | + SPI_FRAME_BITS(dspi->oper_bits_per_word)); +} + static void dspi_fifo_write(struct fsl_dspi *dspi) { + dspi_setup_accel(dspi); + if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) dspi_eoq_fifo_write(dspi); else @@ -726,7 +835,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi) int bytes_sent; /* Update total number of bytes that were transferred */ - bytes_sent = dspi->words_in_flight * dspi->bytes_per_word; + bytes_sent = dspi->words_in_flight * dspi->oper_word_size; msg->actual_length += bytes_sent; dspi->progress += bytes_sent / DIV_ROUND_UP(xfer->bits_per_word, 8); @@ -824,13 +933,14 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi->rx = transfer->rx_buf; dspi->len = transfer->len; dspi->progress = 0; - /* Validated transfer specific frame size (defaults applied) */ - dspi->bits_per_word = transfer->bits_per_word; - dspi->bytes_per_word = DIV_ROUND_UP(dspi->bits_per_word, 8); regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); + /* + * Static CTAR setup for modes that don't dynamically adjust it + * via dspi_setup_accel (aka for DMA) + */ regmap_write(dspi->regmap, SPI_CTAR(0), dspi->cur_chip->ctar_val | SPI_FRAME_BITS(transfer->bits_per_word)); From patchwork Wed Mar 4 22:00:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420855 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A904B14B7 for ; Wed, 4 Mar 2020 22:02:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8178E2084E for ; Wed, 4 Mar 2020 22:02:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qpZa/IUe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388541AbgCDWCI (ORCPT ); Wed, 4 Mar 2020 17:02:08 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:36582 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388511AbgCDWCH (ORCPT ); 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Wed, 04 Mar 2020 14:02:05 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id z2sm36776402wrq.95.2020.03.04.14.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 14:02:05 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 10/12] spi: spi-fsl-dspi: Optimize dspi_setup_accel for lowest interrupt count Date: Thu, 5 Mar 2020 00:00:42 +0200 Message-Id: <20200304220044.11193-11-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean Currently, a SPI transfer that is not multiple of the highest supported word width (e.g. 4 bytes) will be transmitted as follows (assume a 30-byte buffer transmitted through a 32-bit wide FIFO that is 32 bytes deep): - First 28 bytes are sent as 7 words of 32 bits each - Last 2 bytes are sent as 1 word of 16 bits size But if the dspi_setup_accel function had decided to use a lower oper_bits_per_word value (16 instead of 32), there would have been enough space in the TX FIFO to fit the entire buffer in one go (15 words of 16 bits each). What we're actually trying to avoid is mixing word sizes within the same run with the TX FIFO, since there is an erratum surrounding this, and invalid data might get transmitted. So this patch adds special cases for when the remaining length of the buffer can be sent in one go as 8-bit or 16-bit words, otherwise it falls back to the standard logic of sending as many bytes as possible at the highest oper_bits_per_word value possible. The benefit is that there will be one less CMDFQ/EOQ interrupt to service when the entire buffer is transmitted during a single go, and that will improve the overall latency of the transfer. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index f5b802070d29..df4944353ed5 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -775,20 +775,34 @@ static void dspi_fifo_read(struct fsl_dspi *dspi) static void dspi_setup_accel(struct fsl_dspi *dspi) { struct spi_transfer *xfer = dspi->cur_transfer; + bool odd = !!(dspi->len & 1); - /* Start off with maximum supported by hardware */ - if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) - dspi->oper_bits_per_word = 32; - else + /* No accel for frames not multiple of 8 bits at the moment */ + if (xfer->bits_per_word % 8) + goto no_accel; + + if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) { dspi->oper_bits_per_word = 16; + } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) { + dspi->oper_bits_per_word = 8; + } else { + /* Start off with maximum supported by hardware */ + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) + dspi->oper_bits_per_word = 32; + else + dspi->oper_bits_per_word = 16; - /* And go down only if the buffer can't be sent with words this big */ - do { - if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8)) - break; + /* + * And go down only if the buffer can't be sent with + * words this big + */ + do { + if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8)) + break; - dspi->oper_bits_per_word /= 2; - } while (dspi->oper_bits_per_word > 8); + dspi->oper_bits_per_word /= 2; + } while (dspi->oper_bits_per_word > 8); + } if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) { dspi->dev_to_host = dspi_8on32_dev_to_host; @@ -800,7 +814,7 @@ static void dspi_setup_accel(struct fsl_dspi *dspi) dspi->dev_to_host = dspi_16on32_dev_to_host; dspi->host_to_dev = dspi_16on32_host_to_dev; } else { - /* No acceleration needed (8dev_to_host = dspi_native_dev_to_host; dspi->host_to_dev = dspi_native_host_to_dev; dspi->oper_bits_per_word = xfer->bits_per_word; From patchwork Wed Mar 4 22:00:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420853 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7887714BC for ; Wed, 4 Mar 2020 22:02:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 50FF32084E for ; Wed, 4 Mar 2020 22:02:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZowA7PC4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388546AbgCDWCJ (ORCPT ); Wed, 4 Mar 2020 17:02:09 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:36582 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388539AbgCDWCI (ORCPT ); Wed, 4 Mar 2020 17:02:08 -0500 Received: by mail-wm1-f66.google.com with SMTP id g83so3503989wme.1; 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Wed, 04 Mar 2020 14:02:06 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id z2sm36776402wrq.95.2020.03.04.14.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 14:02:06 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 11/12] spi: spi-fsl-dspi: Use EOQ for last word in buffer even for XSPI mode Date: Thu, 5 Mar 2020 00:00:43 +0200 Message-Id: <20200304220044.11193-12-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean The EOQ mode has a hardware limitation in that it stops the transmission (including the deassertion of the chip select signal) once the host CPU requests end-of-queue for a particular word in the TX FIFO. And XSPI mode has a limitation in that we need a separate CMD FIFO entry for the last byte in the buffer, where the chip select signal needs to be deasserted. It's not a functional limitation, but it's rather clunky and the fact that we need to halt the pipeline and write a single entry to the TX FIFO whenever a buffer ends brings the throughput down when transmitting small buffers. So the idea here is to use EOQ's limitation in our favor when using XSPI mode. Stop special-casing that final word in the buffer, and just kill the chip select signal by issuing an EOQ for that last word. Now it can be mixed in with all the other words in the current TX FIFO train. A small trick here is that we still keep using the XSPI-specific signaling via the CMDTCFQ interrupt in RSER, and not enabling the EOQ interrupt, in order to avoid hardware weirdness (potential races with separate interrupts being raised for CMDTCFQ and EOQ for what is in fact the end of the same transmission). That is just theoretical, but it's good to be cautious, and the EOQ interrupt isn't needed. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index df4944353ed5..d5983be32180 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -656,10 +656,8 @@ static void dspi_pushr_write(struct fsl_dspi *dspi) regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); } -static void dspi_pushr_cmd_write(struct fsl_dspi *dspi) +static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd) { - u16 cmd = dspi->tx_cmd; - /* * The only time when the PCS doesn't need continuation after this word * is when it's last. We need to look ahead, because we actually call @@ -680,8 +678,13 @@ static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); } -static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) +static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq) { + u16 tx_cmd = dspi->tx_cmd; + + if (eoq) + tx_cmd |= SPI_PUSHR_CMD_EOQ; + /* Update CTARE */ regmap_write(dspi->regmap, SPI_CTARE(0), SPI_FRAME_EBITS(dspi->oper_bits_per_word) | @@ -691,7 +694,7 @@ static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) * Write the CMD FIFO entry first, and then the two * corresponding TX FIFO entries (or one...). */ - dspi_pushr_cmd_write(dspi); + dspi_pushr_cmd_write(dspi, tx_cmd); /* Fill TX FIFO with as many transfers as possible */ while (cnt--) { @@ -707,6 +710,7 @@ static void dspi_xspi_fifo_write(struct fsl_dspi *dspi) { int num_fifo_entries = dspi->devtype_data->fifo_size; int bytes_in_flight; + bool eoq = false; /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ if (dspi->oper_word_size == 4) @@ -732,11 +736,11 @@ static void dspi_xspi_fifo_write(struct fsl_dspi *dspi) * So send one word less during this go, to force a split and a command * with a single word next time, when CONT will be unset. */ - if (bytes_in_flight == dspi->len && dspi->words_in_flight > 1 && - !(dspi->tx_cmd & SPI_PUSHR_CMD_CONT)) - dspi->words_in_flight--; + if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && + bytes_in_flight == dspi->len) + eoq = true; - dspi_xspi_write(dspi, dspi->words_in_flight); + dspi_xspi_write(dspi, dspi->words_in_flight, eoq); } static void dspi_eoq_fifo_write(struct fsl_dspi *dspi) From patchwork Wed Mar 4 22:00:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11420857 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D00BF1580 for ; Wed, 4 Mar 2020 22:02:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B17552084E for ; Wed, 4 Mar 2020 22:02:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DT74En0t" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388488AbgCDWCP (ORCPT ); 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bh=KdIcE5d8Uw19DbXJrimdSx5cb22qFvX6ysB7MYCKIMM=; b=SoFx1+n3gZcxdk7bsfdlWEcpbcxS5NLmGWsUJU6d660cDMh0cjB7iJh8QG+dRCggdV uY5wtN41qDKQ+Euy2Q3e+Io7wa19YwRwodvwOUYonZjHsm5QuXfCrR4rjuZgyskl0k7E wowIs9vmk7ePgPEYqkA4VyKo0D50FYrojoWBGNVnVXrwfkX5kBIj8SHTAYL/GOxeMuOh zquCxkabMNfyr71D6bmru+fWK089q0A9wzCLV6Of8bixO8pDiCJUFv21hpDqCsRPCtex 3EDYewkOZcnLPdhthl+9o3w7hvMcs83a0tf4Vef02Px9tEyXhY8/BGSHgG3wXUR0ucro e/7w== X-Gm-Message-State: ANhLgQ3+ypzmzKU+lN97DWXI0fY9RF42oK590Sps1E9Rw3/P32MGbL2W 2HYzeXuvLUgQz1JolVIHD7o= X-Google-Smtp-Source: ADFU+vs5VXV7lI5oAktJlLp9+JLzZTPIciZWhBuqWaMxv27GlCHOahYTOfLiGOWZ1UIwAfK67+gJWg== X-Received: by 2002:a7b:c204:: with SMTP id x4mr5516319wmi.20.1583359327911; Wed, 04 Mar 2020 14:02:07 -0800 (PST) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id z2sm36776402wrq.95.2020.03.04.14.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 14:02:07 -0800 (PST) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com Subject: [PATCH 12/12] spi: spi-fsl-dspi: Take software timestamp in dspi_fifo_write Date: Thu, 5 Mar 2020 00:00:44 +0200 Message-Id: <20200304220044.11193-13-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304220044.11193-1-olteanv@gmail.com> References: <20200304220044.11193-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean Although the SPI system timestamps are supposed to reflect the moment that the peripheral has received a word rather than the moment when the CPU has enqueued that word to the FIFO, in practice it is easier to just record the latter time than the former (with a smaller error). With the recent migration of TCFQ users from poll back to interrupt mode (this time for XSPI FIFO), it's wiser to keep the interrupt latency outside of the measurement of the PTP system timestamp itself. If there proves to be any constant offset that requires static compensation, that can always be added later. So far that does not appear to be the case at least on the LS1021A-TSN board, where testing shows that the phc2sys offset is able to remain within +/- 200 ns even after 68 hours of testing. Signed-off-by: Vladimir Oltean --- drivers/spi/spi-fsl-dspi.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index d5983be32180..b5ab0afbfa26 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -838,19 +838,18 @@ static void dspi_setup_accel(struct fsl_dspi *dspi) static void dspi_fifo_write(struct fsl_dspi *dspi) { + struct spi_transfer *xfer = dspi->cur_transfer; + struct spi_message *msg = dspi->cur_msg; + int bytes_sent; + dspi_setup_accel(dspi); + spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq); + if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) dspi_eoq_fifo_write(dspi); else dspi_xspi_fifo_write(dspi); -} - -static int dspi_rxtx(struct fsl_dspi *dspi) -{ - struct spi_transfer *xfer = dspi->cur_transfer; - struct spi_message *msg = dspi->cur_msg; - int bytes_sent; /* Update total number of bytes that were transferred */ bytes_sent = dspi->words_in_flight * dspi->oper_word_size; @@ -859,16 +858,16 @@ static int dspi_rxtx(struct fsl_dspi *dspi) spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); +} +static int dspi_rxtx(struct fsl_dspi *dspi) +{ dspi_fifo_read(dspi); if (!dspi->len) /* Success! */ return 0; - spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, - dspi->progress, !dspi->irq); - dspi_fifo_write(dspi); return -EINPROGRESS;