From patchwork Thu Mar 5 06:54:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pan Nengyuan X-Patchwork-Id: 11421225 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3342392A for ; Thu, 5 Mar 2020 06:39:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 14111208CD for ; Thu, 5 Mar 2020 06:39:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 14111208CD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:43918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j9kAl-00059o-65 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 05 Mar 2020 01:39:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60636) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j9kA8-0003lO-Gk for qemu-devel@nongnu.org; Thu, 05 Mar 2020 01:39:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j9kA5-0006S9-KH for qemu-devel@nongnu.org; Thu, 05 Mar 2020 01:39:16 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3260 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j9kA5-0006Q6-8m; Thu, 05 Mar 2020 01:39:13 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6AE6E71227B591FEA178; Thu, 5 Mar 2020 14:39:10 +0800 (CST) Received: from localhost.huawei.com (10.175.104.216) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 5 Mar 2020 14:39:03 +0800 From: Pan Nengyuan To: Subject: [PATCH v4 1/3] s390x: fix memleaks in cpu_finalize Date: Thu, 5 Mar 2020 14:54:20 +0800 Message-ID: <20200305065422.12707-2-pannengyuan@huawei.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200305065422.12707-1-pannengyuan@huawei.com> References: <20200305065422.12707-1-pannengyuan@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.104.216] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, zhang.zhanghailiang@huawei.com, David Hildenbrand , Cornelia Huck , Pan Nengyuan , qemu-s390x@nongnu.org, euler.robot@huawei.com, Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This patch fix memleaks when we call tests/qtest/cpu-plug-test on s390x. The leak stack is as follow: Direct leak of 48 byte(s) in 1 object(s) allocated from: #0 0x7fb43c7cd970 in __interceptor_calloc (/lib64/libasan.so.5+0xef970) #1 0x7fb43be2149d in g_malloc0 (/lib64/libglib-2.0.so.0+0x5249d) #2 0x558ba96da716 in timer_new_full /mnt/sdb/qemu-new/qemu/include/qemu/timer.h:530 #3 0x558ba96da716 in timer_new /mnt/sdb/qemu-new/qemu/include/qemu/timer.h:551 #4 0x558ba96da716 in timer_new_ns /mnt/sdb/qemu-new/qemu/include/qemu/timer.h:569 #5 0x558ba96da716 in s390_cpu_initfn /mnt/sdb/qemu-new/qemu/target/s390x/cpu.c:285 #6 0x558ba9c969ab in object_init_with_type /mnt/sdb/qemu-new/qemu/qom/object.c:372 #7 0x558ba9c9eb5f in object_initialize_with_type /mnt/sdb/qemu-new/qemu/qom/object.c:516 #8 0x558ba9c9f053 in object_new_with_type /mnt/sdb/qemu-new/qemu/qom/object.c:684 #9 0x558ba967ede6 in s390x_new_cpu /mnt/sdb/qemu-new/qemu/hw/s390x/s390-virtio-ccw.c:64 #10 0x558ba99764b3 in hmp_cpu_add /mnt/sdb/qemu-new/qemu/hw/core/machine-hmp-cmds.c:57 #11 0x558ba9b1c27f in handle_hmp_command /mnt/sdb/qemu-new/qemu/monitor/hmp.c:1082 #12 0x558ba96c1b02 in qmp_human_monitor_command /mnt/sdb/qemu-new/qemu/monitor/misc.c:142 Reported-by: Euler Robot Signed-off-by: Pan Nengyuan --- Cc: Richard Henderson Cc: David Hildenbrand Cc: Cornelia Huck Cc: qemu-s390x@nongnu.org --- v2->v1: - Similarly to other cleanups, move timer_new into realize(Suggested by Philippe Mathieu-Daudé) v3->v2: - Aslo do the timer_free in unrealize, it seems balanced. v4->v3: - Aslo do timer_free on the error path in realize() and fix some coding style. - Use device_class_set_parent_unrealize to declare unrealize. --- target/s390x/cpu-qom.h | 1 + target/s390x/cpu.c | 41 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 38 insertions(+), 4 deletions(-) diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index dbe5346ec9..af9ffed0d8 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -61,6 +61,7 @@ typedef struct S390CPUClass { const char *desc; DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; void (*parent_reset)(CPUState *cpu); void (*load_normal)(CPUState *cpu); void (*reset)(CPUState *cpu, cpu_reset_type type); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index cf84d307c6..80b987ff1b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -182,6 +182,12 @@ static void s390_cpu_realizefn(DeviceState *dev, Error **errp) #if !defined(CONFIG_USER_ONLY) MachineState *ms = MACHINE(qdev_get_machine()); unsigned int max_cpus = ms->smp.max_cpus; + + cpu->env.tod_timer = + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); + cpu->env.cpu_timer = + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); + if (cpu->env.core_id >= max_cpus) { error_setg(&err, "Unable to add CPU with core-id: %" PRIu32 ", maximum core-id: %d", cpu->env.core_id, @@ -224,9 +230,38 @@ static void s390_cpu_realizefn(DeviceState *dev, Error **errp) scc->parent_realize(dev, &err); out: + if (cpu->env.tod_timer) { + timer_del(cpu->env.tod_timer); + } + if (cpu->env.cpu_timer) { + timer_del(cpu->env.cpu_timer); + } + timer_free(cpu->env.tod_timer); + timer_free(cpu->env.cpu_timer); error_propagate(errp, err); } +static void s390_cpu_unrealizefn(DeviceState *dev, Error **errp) +{ + S390CPUClass *scc = S390_CPU_GET_CLASS(dev); + Error *err = NULL; + +#if !defined(CONFIG_USER_ONLY) + S390CPU *cpu = S390_CPU(dev); + + timer_del(cpu->env.tod_timer); + timer_del(cpu->env.cpu_timer); + timer_free(cpu->env.tod_timer); + timer_free(cpu->env.cpu_timer); +#endif + + scc->parent_unrealize(dev, &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } +} + static GuestPanicInformation *s390_cpu_get_crash_info(CPUState *cs) { GuestPanicInformation *panic_info; @@ -279,10 +314,6 @@ static void s390_cpu_initfn(Object *obj) s390_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL); s390_cpu_model_register_props(obj); #if !defined(CONFIG_USER_ONLY) - cpu->env.tod_timer = - timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); - cpu->env.cpu_timer = - timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); #endif } @@ -453,6 +484,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, s390_cpu_realizefn, &scc->parent_realize); + device_class_set_parent_unrealize(dc, s390_cpu_unrealizefn, + &scc->parent_unrealize); device_class_set_props(dc, s390x_cpu_properties); dc->user_creatable = true; From patchwork Thu Mar 5 06:54:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pan Nengyuan X-Patchwork-Id: 11421229 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCF6D14E3 for ; Thu, 5 Mar 2020 06:41:12 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AD7E7208CD for ; Thu, 5 Mar 2020 06:41:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AD7E7208CD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:43946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j9kBz-0007J1-St for patchwork-qemu-devel@patchwork.kernel.org; Thu, 05 Mar 2020 01:41:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60657) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j9kAB-0003oJ-Vc for qemu-devel@nongnu.org; Thu, 05 Mar 2020 01:39:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j9kAA-0006Ww-Mk for qemu-devel@nongnu.org; Thu, 05 Mar 2020 01:39:19 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:34374 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j9kAA-0006UO-BG for qemu-devel@nongnu.org; Thu, 05 Mar 2020 01:39:18 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 73CE7614AEAA49713910; Thu, 5 Mar 2020 14:39:15 +0800 (CST) Received: from localhost.huawei.com (10.175.104.216) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 5 Mar 2020 14:39:07 +0800 From: Pan Nengyuan To: Subject: [PATCH v4 2/3] mac_via: fix incorrect creation of mos6522 device in mac_via Date: Thu, 5 Mar 2020 14:54:21 +0800 Message-ID: <20200305065422.12707-3-pannengyuan@huawei.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200305065422.12707-1-pannengyuan@huawei.com> References: <20200305065422.12707-1-pannengyuan@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.104.216] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, zhang.zhanghailiang@huawei.com, Pan Nengyuan , Mark Cave-Ayland , Laurent Vivier , euler.robot@huawei.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This patch fix a bug in mac_via where it failed to actually realize devices it was using. And move the init codes which inits the mos6522 objects and properties on them from realize() into init(). However, we keep qdev_set_parent_bus in realize(), otherwise it will cause device-introspect-test test fail. Then do the realize mos6522 device in the mac_vir_realize. Signed-off-by: Pan Nengyuan Signed-off-by: Pan Nengyuan --- Cc: Laurent Vivier Cc: Mark Cave-Ayland --- v4->v3: - split v3 into two patches, this patch fix incorrect creation of mos6522, move inits and props from realize into init. The v3 is: https://patchwork.kernel.org/patch/11407635/ --- hw/misc/mac_via.c | 43 ++++++++++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index b7d0012794..4c5ad08805 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -868,24 +868,24 @@ static void mac_via_reset(DeviceState *dev) static void mac_via_realize(DeviceState *dev, Error **errp) { MacVIAState *m = MAC_VIA(dev); - MOS6522State *ms; struct tm tm; int ret; + Error *err = NULL; - /* Init VIAs 1 and 2 */ - sysbus_init_child_obj(OBJECT(dev), "via1", &m->mos6522_via1, - sizeof(m->mos6522_via1), TYPE_MOS6522_Q800_VIA1); + qdev_set_parent_bus(DEVICE(&m->mos6522_via1), sysbus_get_default()); + qdev_set_parent_bus(DEVICE(&m->mos6522_via2), sysbus_get_default()); - sysbus_init_child_obj(OBJECT(dev), "via2", &m->mos6522_via2, - sizeof(m->mos6522_via2), TYPE_MOS6522_Q800_VIA2); + object_property_set_bool(OBJECT(&m->mos6522_via1), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } - /* Pass through mos6522 output IRQs */ - ms = MOS6522(&m->mos6522_via1); - object_property_add_alias(OBJECT(dev), "irq[0]", OBJECT(ms), - SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort); - ms = MOS6522(&m->mos6522_via2); - object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms), - SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort); + object_property_set_bool(OBJECT(&m->mos6522_via2), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } /* Pass through mos6522 input IRQs */ qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq"); @@ -932,6 +932,7 @@ static void mac_via_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); MacVIAState *m = MAC_VIA(obj); + MOS6522State *ms; /* MMIO */ memory_region_init(&m->mmio, obj, "mac-via", 2 * VIA_SIZE); @@ -948,6 +949,22 @@ static void mac_via_init(Object *obj) /* ADB */ qbus_create_inplace((BusState *)&m->adb_bus, sizeof(m->adb_bus), TYPE_ADB_BUS, DEVICE(obj), "adb.0"); + + /* Init VIAs 1 and 2 */ + object_initialize_child(OBJECT(m), "via1", &m->mos6522_via1, + sizeof(m->mos6522_via1), TYPE_MOS6522_Q800_VIA1, + &error_abort, NULL); + object_initialize_child(OBJECT(m), "via2", &m->mos6522_via2, + sizeof(m->mos6522_via2), TYPE_MOS6522_Q800_VIA2, + &error_abort, NULL); + + /* Pass through mos6522 output IRQs */ + ms = MOS6522(&m->mos6522_via1); + object_property_add_alias(OBJECT(m), "irq[0]", OBJECT(ms), + SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort); + ms = MOS6522(&m->mos6522_via2); + object_property_add_alias(OBJECT(m), "irq[1]", OBJECT(ms), + SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort); } static void postload_update_cb(void *opaque, int running, RunState state) From patchwork Thu Mar 5 06:54:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pan Nengyuan X-Patchwork-Id: 11421227 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1880614BC for ; Thu, 5 Mar 2020 06:40:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EC425208CD for ; Thu, 5 Mar 2020 06:40:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EC425208CD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:43920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j9kAy-0005cB-5z for patchwork-qemu-devel@patchwork.kernel.org; Thu, 05 Mar 2020 01:40:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60671) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j9kAG-0003w0-1V for qemu-devel@nongnu.org; Thu, 05 Mar 2020 01:39:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j9kAE-0006be-VA for qemu-devel@nongnu.org; Thu, 05 Mar 2020 01:39:23 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3261 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j9kAE-0006Zo-Jx; Thu, 05 Mar 2020 01:39:22 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 80FCB12617C58EFDA6F7; Thu, 5 Mar 2020 14:39:20 +0800 (CST) Received: from localhost.huawei.com (10.175.104.216) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Thu, 5 Mar 2020 14:39:10 +0800 From: Pan Nengyuan To: Subject: [PATCH v4 3/3] hw/misc/mos6522: move timer_new from init() into realize() to avoid memleaks Date: Thu, 5 Mar 2020 14:54:22 +0800 Message-ID: <20200305065422.12707-4-pannengyuan@huawei.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200305065422.12707-1-pannengyuan@huawei.com> References: <20200305065422.12707-1-pannengyuan@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.104.216] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, zhang.zhanghailiang@huawei.com, Pan Nengyuan , Mark Cave-Ayland , Laurent Vivier , qemu-ppc@nongnu.org, euler.robot@huawei.com, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. Reported-by: Euler Robot Signed-off-by: Pan Nengyuan --- Cc: Laurent Vivier Cc: Mark Cave-Ayland Cc: David Gibson Cc: qemu-ppc@nongnu.org --- v2->v1: - no changes in this patch. v3->v2: - remove null check in reset, and add calls to mos6522_realize() in mac_via_realize to make this move to be valid. v4->v3: - split patch into two, this patch fix the memleaks. --- hw/misc/mos6522.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 19e154b870..c1cd154a84 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -485,6 +485,11 @@ static void mos6522_init(Object *obj) for (i = 0; i < ARRAY_SIZE(s->timers); i++) { s->timers[i].index = i; } +} + +static void mos6522_realize(DeviceState *dev, Error **errp) +{ + MOS6522State *s = MOS6522(dev); s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s); s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s); @@ -502,6 +507,7 @@ static void mos6522_class_init(ObjectClass *oc, void *data) dc->reset = mos6522_reset; dc->vmsd = &vmstate_mos6522; + dc->realize = mos6522_realize; device_class_set_props(dc, mos6522_properties); mdc->parent_reset = dc->reset; mdc->set_sr_int = mos6522_set_sr_int;