From patchwork Tue Mar 10 12:55:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11429329 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2FA321731 for ; Tue, 10 Mar 2020 13:26:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0FBF72071B for ; Tue, 10 Mar 2020 13:26:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PL1RRnyU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729590AbgCJMzz (ORCPT ); Tue, 10 Mar 2020 08:55:55 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:52102 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729577AbgCJMzy (ORCPT ); Tue, 10 Mar 2020 08:55:54 -0400 Received: by mail-wm1-f67.google.com with SMTP id a132so1283751wme.1; Tue, 10 Mar 2020 05:55:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3v9UPmq+Vv3cSCddZuyv3HLidzutYMcEu/49JcrOcIE=; b=PL1RRnyU8o1JjP4q4TIN9i5MglbS9kvc8FuTTvogHkYgVu1hjhA2kjZ/9gjjooSuTi gbW0LOkqH3Q7tNZhBpMniHLELwYo/PQpgO65YKE0KCs2VZePhPhebSbZI7kqbapSvvoq pbXONeKVT4dWeAulH2jxX2e0woTibV+rSCMFR8vZUi/V2bEPMUnLF6bjGCoM+L9nchwM 1FTKojKRH71p+gJj2d20yVvVXuJ9+tbtqg0JopB1c045k+lUnKT+w7UFoGD1WrIZHvcD K9VTtt2L6/XbjrA6L/MvmsLHTlbgLKcfCMOiNjOBu6edzBLwk4FSLyE0H/lVWwLUVx7h hytA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3v9UPmq+Vv3cSCddZuyv3HLidzutYMcEu/49JcrOcIE=; b=gTemCBAAMKRpxwfeuIDJ2CfpgeudlV+YuHJpnh55IMO4qujpTrZOUFs3BFLqJuF3Ur IqtYmYMJRmszgRU7G5Z/Rz37vetIs5L66rXGVZKjbJq7WCycx5tvwDur9RNG5JsLD6z+ xMlnOdKwWn3QnTlP1IIQYSUNQBoOKCkE0WXx0tWKscak89ojgRRp8bxqL5/qEJktBbOL 0CxI1zB6rj4MlOLvOpwaM8sxzr3IM73mpnHIbuOPFymvxdGIugTPk59dfqZynB/iAGd9 7aTqDg7eXXAFtZR4Gy/Pk5b7eljBS2NQErO1ebYPzBPJoUXrLOPefM69ixx7ITuaTk66 em7w== X-Gm-Message-State: ANhLgQ2kZ8ORKnb1HtUXnpuf6jYgqZY8LMMSgZMhtycokuZn6yRcm3a3 YlgxFnsRW4RAUAUqUEPpsgs= X-Google-Smtp-Source: ADFU+vtJvj9IRuqR/RlXga3fZvDzZE/RQZkdUuZqMDXj7+/VqIfX7CJZ55FZ1+ndPPbFbBGcsyi49A== X-Received: by 2002:a1c:68c2:: with SMTP id d185mr2116200wmc.150.1583844951394; Tue, 10 Mar 2020 05:55:51 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id t81sm4018594wmb.15.2020.03.10.05.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 05:55:50 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v3 1/7] spi: spi-fsl-dspi: Don't access reserved fields in SPI_MCR Date: Tue, 10 Mar 2020 14:55:36 +0200 Message-Id: <20200310125542.5939-2-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200310125542.5939-1-olteanv@gmail.com> References: <20200310125542.5939-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean The SPI_MCR_PCSIS macro assumes that the controller has a number of chip select signals equal to 6. That is not always the case, but actually is described through the driver-specific "spi-num-chipselects" device tree binding. LS1028A for example only has 4 chip selects. Don't write to the upper bits of the PCSIS field, which are reserved in the reference manual. Fixes: 349ad66c0ab0 ("spi:Add Freescale DSPI driver for Vybrid VF610 platform") Signed-off-by: Vladimir Oltean --- Changes in v3: None. Changes in v2: Remove duplicate phrase in commit message. drivers/spi/spi-fsl-dspi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 0683a3fbd48c..0ce26c1cbf62 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -22,7 +22,7 @@ #define SPI_MCR 0x00 #define SPI_MCR_MASTER BIT(31) -#define SPI_MCR_PCSIS (0x3F << 16) +#define SPI_MCR_PCSIS(x) ((x) << 16) #define SPI_MCR_CLR_TXF BIT(11) #define SPI_MCR_CLR_RXF BIT(10) #define SPI_MCR_XSPI BIT(3) @@ -1197,7 +1197,10 @@ static const struct regmap_config dspi_xspi_regmap_config[] = { static void dspi_init(struct fsl_dspi *dspi) { - unsigned int mcr = SPI_MCR_PCSIS; + unsigned int mcr; + + /* Set idle states for all chip select signals to high */ + mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->num_chipselect - 1, 0)); if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) mcr |= SPI_MCR_XSPI; From patchwork Tue Mar 10 12:55:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11429333 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96328924 for ; Tue, 10 Mar 2020 13:26:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 649BA24680 for ; Tue, 10 Mar 2020 13:26:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WpO99kUK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729508AbgCJN0g (ORCPT ); Tue, 10 Mar 2020 09:26:36 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:40517 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729573AbgCJMzy (ORCPT ); Tue, 10 Mar 2020 08:55:54 -0400 Received: by mail-wm1-f67.google.com with SMTP id e26so1219770wme.5; Tue, 10 Mar 2020 05:55:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tbjDWzq/l2jrbG3u5/MfQgZvvxeb8f+2VciawpYeynk=; b=WpO99kUK+qHBDl9If27BUE2QK4ZoFBlkwztaFleRDlker3+judsPEfNRIB30bRCzpS YQ9ev59erhyelVwVNajKwqsMpAGih7L4XXs7Ip9DLue9tYFELwulL93D0FqmZ9laUAdI I4FMuttFKHbsXP6HSeyRFVmSVmf4bVHOyFJkdiyZQVo5GA1ltZEldH9SLdvwqTJ+JH/O 8xDM93T22dw6p81RBVtJ/KkfyovX9do2FLGAGESKbZYU8fAMaHwDFzw+89rcBcbhEVG7 dHm7ClYsbVHw10KfBoy5ZZxeLIj86HdI/IVFT3RvvnDn3Ht+2Cou09wRcv9q8ClbfMh/ t0qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tbjDWzq/l2jrbG3u5/MfQgZvvxeb8f+2VciawpYeynk=; b=pasaA7mHN1Ok/K7OCJyN9adLQXE991ovNifc3U/lPUMUWtC/3iSAuBLOxDPFH+aIB6 SD+qW6GtrCmPFzmOxDFOiWyovsAsl1pi1uMl9ELcrFnxwHMUq1ULd2tcbg3dQkembfd4 cjD/fKV9vb9vl+XTdqV2euKDYeXc/urEZQkug8uGcIIHZsMQfNcRHPZUK+1TbkW6sSvX +rB/Q+KpCJKY4qSBEmVEkFax+y9Gbo4TkckbBC7r4aeFE89rojL9/m4ZVDUT6IEK6lmb Wy4RUpReyEHX55nQS22vfY7LloYybfVNUN4o795eLcvic/GAngAPBOTt0HolPD1omuf9 2NPw== X-Gm-Message-State: ANhLgQ2NZmdYjgRSwZvTrCSDiokGkrjy6djvDi4SkaMQlgh+bzGwWvpV cvB0/K19zQ0Xx31tfrVh27E= X-Google-Smtp-Source: ADFU+vtRTW6yZoQCw/OigJJYUmiKOWDql1rrP+JEaARjCYTnuygX2qybJCnS+3Q5Ctw6MKrfisAVEw== X-Received: by 2002:a1c:1fc9:: with SMTP id f192mr2181043wmf.4.1583844952793; Tue, 10 Mar 2020 05:55:52 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id t81sm4018594wmb.15.2020.03.10.05.55.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 05:55:52 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v3 2/7] spi: spi-fsl-dspi: Avoid use-after-free in interrupt mode Date: Tue, 10 Mar 2020 14:55:37 +0200 Message-Id: <20200310125542.5939-3-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200310125542.5939-1-olteanv@gmail.com> References: <20200310125542.5939-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean When the wait_event_interruptible call fails, there is still a chance that the dspi_interrupt may arrive (for example the kernel thread doing the SPI pump really is interrupted). In that case, dspi_transfer_one_message will return execution all the way to the spi_device driver, which may free the spi_message and spi_transfer structures. But when the interrupt arrives, the driver still accesses those structures, leading to use-after-free issues as can be seen below: hexdump -C /dev/mtd0 00000000 00 75 68 75 0a ff ff ff ff ff ff ff ff ff ff ff |.uhu............| 00000010 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * ^C[ 38.495955] fsl-dspi 2120000.spi: Waiting for transfer to complete failed! [ 38.503097] spi_master spi2: failed to transfer one message from queue [ 38.509729] Unable to handle kernel paging request at virtual address ffff800095ab3377 [ 38.517676] Mem abort info: [ 38.520474] ESR = 0x96000045 [ 38.523533] EC = 0x25: DABT (current EL), IL = 32 bits [ 38.528861] SET = 0, FnV = 0 [ 38.531921] EA = 0, S1PTW = 0 [ 38.535067] Data abort info: [ 38.537952] ISV = 0, ISS = 0x00000045 [ 38.541797] CM = 0, WnR = 1 [ 38.544771] swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000082621000 [ 38.551494] [ffff800095ab3377] pgd=00000020fffff003, p4d=00000020fffff003, pud=0000000000000000 [ 38.560229] Internal error: Oops: 96000045 [#1] PREEMPT SMP [ 38.565819] Modules linked in: [ 38.568882] CPU: 0 PID: 2729 Comm: hexdump Not tainted 5.6.0-rc4-next-20200306-00052-gd8730cdc8a0b-dirty #193 [ 38.578834] Hardware name: Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier (DT) [ 38.587129] pstate: 20000085 (nzCv daIf -PAN -UAO) [ 38.591941] pc : ktime_get_real_ts64+0x3c/0x110 [ 38.596487] lr : spi_take_timestamp_pre+0x40/0x90 [ 38.601203] sp : ffff800010003d90 [ 38.604525] x29: ffff800010003d90 x28: ffff80001200e000 [ 38.609854] x27: ffff800011da9000 x26: ffff002079c40400 [ 38.615184] x25: ffff8000117fe018 x24: ffff800011daa1a0 [ 38.620513] x23: ffff800015ab3860 x22: ffff800095ab3377 [ 38.625841] x21: 000000000000146e x20: ffff8000120c3000 [ 38.631170] x19: ffff0020795f6e80 x18: ffff800011da9948 [ 38.636498] x17: 0000000000000000 x16: 0000000000000000 [ 38.641826] x15: ffff800095ab3377 x14: 0720072007200720 [ 38.647155] x13: 0720072007200765 x12: 0775076507750771 [ 38.652483] x11: 0720076d076f0772 x10: 0000000000000040 [ 38.657812] x9 : ffff8000108e2100 x8 : ffff800011dcabe8 [ 38.663139] x7 : 0000000000000000 x6 : ffff800015ab3a60 [ 38.668468] x5 : 0000000007200720 x4 : ffff800095ab3377 [ 38.673796] x3 : 0000000000000000 x2 : 0000000000000ab0 [ 38.679125] x1 : ffff800011daa000 x0 : 0000000000000026 [ 38.684454] Call trace: [ 38.686905] ktime_get_real_ts64+0x3c/0x110 [ 38.691100] spi_take_timestamp_pre+0x40/0x90 [ 38.695470] dspi_fifo_write+0x58/0x2c0 [ 38.699315] dspi_interrupt+0xbc/0xd0 [ 38.702987] __handle_irq_event_percpu+0x78/0x2c0 [ 38.707706] handle_irq_event_percpu+0x3c/0x90 [ 38.712161] handle_irq_event+0x4c/0xd0 [ 38.716008] handle_fasteoi_irq+0xbc/0x170 [ 38.720115] generic_handle_irq+0x2c/0x40 [ 38.724135] __handle_domain_irq+0x68/0xc0 [ 38.728243] gic_handle_irq+0xc8/0x160 [ 38.732000] el1_irq+0xb8/0x180 [ 38.735149] spi_nor_spimem_read_data+0xe0/0x140 [ 38.739779] spi_nor_read+0xc4/0x120 [ 38.743364] mtd_read_oob+0xa8/0xc0 [ 38.746860] mtd_read+0x4c/0x80 [ 38.750007] mtdchar_read+0x108/0x2a0 [ 38.753679] __vfs_read+0x20/0x50 [ 38.757002] vfs_read+0xa4/0x190 [ 38.760237] ksys_read+0x6c/0xf0 [ 38.763471] __arm64_sys_read+0x20/0x30 [ 38.767319] el0_svc_common.constprop.3+0x90/0x160 [ 38.772125] do_el0_svc+0x28/0x90 [ 38.775449] el0_sync_handler+0x118/0x190 [ 38.779468] el0_sync+0x140/0x180 [ 38.782793] Code: 91000294 1400000f d50339bf f9405e80 (f90002c0) [ 38.788910] ---[ end trace 55da560db4d6bef7 ]--- [ 38.793540] Kernel panic - not syncing: Fatal exception in interrupt [ 38.799914] SMP: stopping secondary CPUs [ 38.803849] Kernel Offset: disabled [ 38.807344] CPU features: 0x10002,20006008 [ 38.811451] Memory Limit: none [ 38.814513] ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]--- The solution is to mask interrupts when we know we can't deal with them. Also, to make sure they won't bite when we enable them back, we clear the status register such that stale interrupt requests will just be lost (as is expected on timeout or wait interruption). Fixes: 349ad66c0ab0 ("spi:Add Freescale DSPI driver for Vybrid VF610 platform") Reported-by: Michael Walle Signed-off-by: Vladimir Oltean --- Changes in v3: Patch is new. drivers/spi/spi-fsl-dspi.c | 63 +++++++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 25 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 0ce26c1cbf62..f2ba0731aebe 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -911,15 +911,39 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } +static void dspi_enable_interrupts(struct fsl_dspi *dspi, bool on) +{ + u32 spi_rser = 0; + + if (on) { + switch (dspi->devtype_data->trans_mode) { + case DSPI_EOQ_MODE: + spi_rser = SPI_RSER_EOQFE; + break; + case DSPI_XSPI_MODE: + spi_rser = SPI_RSER_CMDTCFE; + break; + default: + /* Interrupts not necessary for DMA mode */ + return; + } + } + + regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); + regmap_write(dspi->regmap, SPI_RSER, spi_rser); +} + static int dspi_transfer_one_message(struct spi_controller *ctlr, struct spi_message *message) { struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); struct spi_device *spi = message->spi; - enum dspi_trans_mode trans_mode; struct spi_transfer *transfer; int status = 0; + if (dspi->irq) + dspi_enable_interrupts(dspi, true); + message->actual_length = 0; list_for_each_entry(transfer, &message->transfers, transfer_list) { @@ -965,37 +989,24 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); - trans_mode = dspi->devtype_data->trans_mode; - switch (trans_mode) { - case DSPI_EOQ_MODE: - regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); - dspi_fifo_write(dspi); - break; - case DSPI_XSPI_MODE: - regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); - dspi_fifo_write(dspi); - break; - case DSPI_DMA_MODE: + if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TFFFE | SPI_RSER_TFFFD | SPI_RSER_RFDFE | SPI_RSER_RFDFD); status = dspi_dma_xfer(dspi); - break; - default: - dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", - trans_mode); - status = -EINVAL; - goto out; - } + if (status) + goto out; + } else if (dspi->irq) { + /* Kick off the interrupt train */ + dspi_fifo_write(dspi); - if (!dspi->irq) { - do { - status = dspi_poll(dspi); - } while (status == -EINPROGRESS); - } else if (trans_mode != DSPI_DMA_MODE) { status = wait_event_interruptible(dspi->waitq, dspi->waitflags); dspi->waitflags = 0; + } else { + do { + status = dspi_poll(dspi); + } while (status == -EINPROGRESS); } if (status) dev_err(&dspi->pdev->dev, @@ -1005,6 +1016,9 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, } out: + if (dspi->irq) + dspi_enable_interrupts(dspi, false); + message->status = status; spi_finalize_current_message(ctlr); @@ -1208,7 +1222,6 @@ static void dspi_init(struct fsl_dspi *dspi) mcr |= SPI_MCR_MASTER; regmap_write(dspi->regmap, SPI_MCR, mcr); - regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); } static int dspi_slave_abort(struct spi_master *master) From patchwork Tue Mar 10 12:55:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11429331 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1657B924 for ; Tue, 10 Mar 2020 13:26:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E18D624649 for ; Tue, 10 Mar 2020 13:26:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IzLPpzYR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730006AbgCJN0c (ORCPT ); Tue, 10 Mar 2020 09:26:32 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:39708 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729585AbgCJMzz (ORCPT ); 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Tue, 10 Mar 2020 05:55:54 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id t81sm4018594wmb.15.2020.03.10.05.55.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 05:55:53 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v3 3/7] spi: spi-fsl-dspi: Fix little endian access to PUSHR CMD and TXDATA Date: Tue, 10 Mar 2020 14:55:38 +0200 Message-Id: <20200310125542.5939-4-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200310125542.5939-1-olteanv@gmail.com> References: <20200310125542.5939-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean In XSPI mode, the 32-bit PUSHR register can be written to separately: the higher 16 bits are for commands and the lower 16 bits are for data. This has nicely been hacked around, by defining a second regmap with a width of 16 bits, and effectively splitting a 32-bit register into 2 16-bit ones, from the perspective of this regmap_pushr. The problem is the assumption about the controller's endianness. If the controller is little endian (such as anything post-LS1046A), then the first 2 bytes, in the order imposed by memory layout, will actually hold the TXDATA, and the last 2 bytes will hold the CMD. So take the controller's endianness into account when performing split writes to PUSHR. The obvious and simple solution would have been to call regmap_get_val_endian(), but that is an internal regmap function and we don't want to change regmap just for this. Therefore, we just re-read the "big-endian" device tree property. Fixes: 58ba07ec79e6 ("spi: spi-fsl-dspi: Add support for XSPI mode registers") Signed-off-by: Vladimir Oltean --- Changes in v3: None. Changes in v2: Parse "big-endian" device tree bindings instead of taking the decision based on compatible SoC. drivers/spi/spi-fsl-dspi.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index f2ba0731aebe..c59b68592283 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -103,10 +103,6 @@ #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) -/* Register offsets for regmap_pushr */ -#define PUSHR_CMD 0x0 -#define PUSHR_TX 0x2 - #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) struct chip_data { @@ -240,6 +236,13 @@ struct fsl_dspi { int words_in_flight; + /* + * Offsets for CMD and TXDATA within SPI_PUSHR when accessed + * individually (in XSPI mode) + */ + int pushr_cmd; + int pushr_tx; + void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata); void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); }; @@ -670,12 +673,12 @@ static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd) */ if (dspi->len > dspi->oper_word_size) cmd |= SPI_PUSHR_CMD_CONT; - regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); + regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd); } static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) { - regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); + regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata); } static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq) @@ -1269,6 +1272,7 @@ static int dspi_probe(struct platform_device *pdev) struct fsl_dspi *dspi; struct resource *res; void __iomem *base; + bool big_endian; ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); if (!ctlr) @@ -1294,6 +1298,7 @@ static int dspi_probe(struct platform_device *pdev) /* Only Coldfire uses platform data */ dspi->devtype_data = &devtype_data[MCF5441X]; + big_endian = true; } else { ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); @@ -1315,6 +1320,15 @@ static int dspi_probe(struct platform_device *pdev) ret = -EFAULT; goto out_ctlr_put; } + + big_endian = of_device_is_big_endian(np); + } + if (big_endian) { + dspi->pushr_cmd = 0; + dspi->pushr_tx = 2; + } else { + dspi->pushr_cmd = 2; + dspi->pushr_tx = 0; } if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) From patchwork Tue Mar 10 12:55:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11429323 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D6C1C139A for ; Tue, 10 Mar 2020 13:26:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A4A002071B for ; Tue, 10 Mar 2020 13:26:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eo1lo0gK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729591AbgCJM4B (ORCPT ); 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bh=uB7g92zSkyc4Tyrv/IlzK5Cjo/ddDsP0TZyadbno/Zs=; b=S14D/CCjgMFUgPg4skSsjFMii6TQp0oHgEg0DeiFVBjHcnV6vHDs6Z9l3iYuRvK0fX qTzqdxbJnxbjWopQcDaZ0qEm6OuN+XVtm16FEYJo7PU6SWcJnDVXAUbz76M3YzwUBTR3 0hy8uYCyCbGkKq6igva7xtcEC7BGjpEYH7bLxpAc4fVnPNZSSSTAImEhyOK/oMRNuFFF 5Ly3FerIQdZ5r/1fXkF5/t4JaaAnHyBI8ucTgie53n8dWL9Gfxlkhy3SuS+AH2W8Z17R KWyUcUWPucglSnTQ+jSOCZRRa5n/u+ckOkSDg5oRWypGLHELbUrl2OGpvce1AUOCqP5S hhGA== X-Gm-Message-State: ANhLgQ0Vsw/gq6zzfi+cqZPBpZq5MwYVLAPexrD21izDfBBIgqh/LFbn 9S9Ezfk0z6jn0O278TIWy0E7ziUtOAk= X-Google-Smtp-Source: ADFU+vuhmnR9pAQBOTGsK/B+rEMl1zK1w8TAzrBYjiyeKZ9qBtGblqtfVv39BW0tJutHBhRbXRswjg== X-Received: by 2002:a05:600c:350:: with SMTP id u16mr2056964wmd.168.1583844955860; Tue, 10 Mar 2020 05:55:55 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id t81sm4018594wmb.15.2020.03.10.05.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 05:55:55 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v3 4/7] spi: spi-fsl-dspi: Fix bits-per-word acceleration in DMA mode Date: Tue, 10 Mar 2020 14:55:39 +0200 Message-Id: <20200310125542.5939-5-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200310125542.5939-1-olteanv@gmail.com> References: <20200310125542.5939-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean In DMA mode, dspi_setup_accel does not get called, which results in the dspi->oper_word_size variable (which is used by dspi_dma_xfer) to not be initialized properly. Because oper_word_size is zero, a few calculations end up being incorrect, and the DMA transfer eventually times out instead of sending anything on the wire. Set up native transfers (or 8-on-16 acceleration) using dspi_setup_accel for DMA mode too. Also take the opportunity and simplify the DMA buffer handling a little bit. Fixes: 6c1c26ecd9a3 ("spi: spi-fsl-dspi: Accelerate transfers using larger word size if possible") Signed-off-by: Vladimir Oltean --- Changes in v3: Pretty much re-did the patch. Before, dspi_setup_accel was called just once at the beginning of dspi_dma_xfer. Now it is called in the while loop. Everything else is just refactoring that follows along. Changes in v2: None. drivers/spi/spi-fsl-dspi.c | 7 +++++-- drivers/spi/spi-fsl-dspi.c | 83 +++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 41 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index c59b68592283..8f5d18dc78d5 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -119,7 +119,6 @@ struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; int fifo_size; - int dma_bufsize; }; enum { @@ -138,7 +137,6 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { [VF610] = { .trans_mode = DSPI_DMA_MODE, .max_clock_factor = 2, - .dma_bufsize = 4096, .fifo_size = 4, }, [LS1021A] = { @@ -167,19 +165,16 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { }, [LS2080A] = { .trans_mode = DSPI_DMA_MODE, - .dma_bufsize = 8, .max_clock_factor = 8, .fifo_size = 4, }, [LS2085A] = { .trans_mode = DSPI_DMA_MODE, - .dma_bufsize = 8, .max_clock_factor = 8, .fifo_size = 4, }, [LX2160A] = { .trans_mode = DSPI_DMA_MODE, - .dma_bufsize = 8, .max_clock_factor = 8, .fifo_size = 4, }, @@ -191,9 +186,6 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { }; struct fsl_dspi_dma { - /* Length of transfer in words of dspi->fifo_size */ - u32 curr_xfer_len; - u32 *tx_dma_buf; struct dma_chan *chan_tx; dma_addr_t tx_dma_phys; @@ -352,7 +344,7 @@ static void dspi_rx_dma_callback(void *arg) int i; if (dspi->rx) { - for (i = 0; i < dma->curr_xfer_len; i++) + for (i = 0; i < dspi->words_in_flight; i++) dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]); } @@ -366,12 +358,12 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) int time_left; int i; - for (i = 0; i < dma->curr_xfer_len; i++) + for (i = 0; i < dspi->words_in_flight; i++) dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi); dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, dma->tx_dma_phys, - dma->curr_xfer_len * + dspi->words_in_flight * DMA_SLAVE_BUSWIDTH_4_BYTES, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); @@ -389,7 +381,7 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, dma->rx_dma_phys, - dma->curr_xfer_len * + dspi->words_in_flight * DMA_SLAVE_BUSWIDTH_4_BYTES, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); @@ -437,46 +429,56 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) return 0; } +static void dspi_setup_accel(struct fsl_dspi *dspi); + static int dspi_dma_xfer(struct fsl_dspi *dspi) { struct spi_message *message = dspi->cur_msg; struct device *dev = &dspi->pdev->dev; - struct fsl_dspi_dma *dma = dspi->dma; - int curr_remaining_bytes; - int bytes_per_buffer; + int bytes_in_flight = dspi->len; + int chunk_size; int ret = 0; - curr_remaining_bytes = dspi->len; - bytes_per_buffer = dspi->devtype_data->dma_bufsize / - dspi->devtype_data->fifo_size; - while (curr_remaining_bytes) { + /* + * dspi->len gets decremented by dspi_pop_tx_pushr in + * dspi_next_xfer_dma_submit + */ + while (dspi->len) { + /* Figure out operational bits-per-word for this chunk */ + dspi_setup_accel(dspi); + + /* + * If the 16-bit TXDATA of the PUSHR is underutilized, then + * each DMA buffer will be able to hold only up to fifo_size + * useful bytes. + */ + if (dspi->oper_word_size == 1) + chunk_size = dspi->devtype_data->fifo_size; + else + chunk_size = dspi->devtype_data->fifo_size * 2; + /* Check if current transfer fits the DMA buffer */ - dma->curr_xfer_len = curr_remaining_bytes / - dspi->oper_word_size; - if (dma->curr_xfer_len > bytes_per_buffer) - dma->curr_xfer_len = bytes_per_buffer; + bytes_in_flight = dspi->len; + if (bytes_in_flight > chunk_size) + bytes_in_flight = chunk_size; + + dspi->words_in_flight = bytes_in_flight / dspi->oper_word_size; ret = dspi_next_xfer_dma_submit(dspi); if (ret) { dev_err(dev, "DMA transfer failed\n"); - goto exit; - - } else { - const int len = dma->curr_xfer_len * - dspi->oper_word_size; - curr_remaining_bytes -= len; - message->actual_length += len; - if (curr_remaining_bytes < 0) - curr_remaining_bytes = 0; + break; } + + message->actual_length += bytes_in_flight; } -exit: return ret; } static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) { + int dma_bufsize = dspi->devtype_data->fifo_size * 2; struct device *dev = &dspi->pdev->dev; struct dma_slave_config cfg; struct fsl_dspi_dma *dma; @@ -500,14 +502,14 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) goto err_tx_channel; } - dma->tx_dma_buf = dma_alloc_coherent(dev, dspi->devtype_data->dma_bufsize, + dma->tx_dma_buf = dma_alloc_coherent(dev, dma_bufsize, &dma->tx_dma_phys, GFP_KERNEL); if (!dma->tx_dma_buf) { ret = -ENOMEM; goto err_tx_dma_buf; } - dma->rx_dma_buf = dma_alloc_coherent(dev, dspi->devtype_data->dma_bufsize, + dma->rx_dma_buf = dma_alloc_coherent(dev, dma_bufsize, &dma->rx_dma_phys, GFP_KERNEL); if (!dma->rx_dma_buf) { ret = -ENOMEM; @@ -544,10 +546,10 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) return 0; err_slave_config: - dma_free_coherent(dev, dspi->devtype_data->dma_bufsize, + dma_free_coherent(dev, dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys); err_rx_dma_buf: - dma_free_coherent(dev, dspi->devtype_data->dma_bufsize, + dma_free_coherent(dev, dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys); err_tx_dma_buf: dma_release_channel(dma->chan_tx); @@ -562,6 +564,7 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) static void dspi_release_dma(struct fsl_dspi *dspi) { + int dma_bufsize = dspi->devtype_data->fifo_size * 2; struct fsl_dspi_dma *dma = dspi->dma; struct device *dev = &dspi->pdev->dev; @@ -570,15 +573,13 @@ static void dspi_release_dma(struct fsl_dspi *dspi) if (dma->chan_tx) { dma_unmap_single(dev, dma->tx_dma_phys, - dspi->devtype_data->dma_bufsize, - DMA_TO_DEVICE); + dma_bufsize, DMA_TO_DEVICE); dma_release_channel(dma->chan_tx); } if (dma->chan_rx) { dma_unmap_single(dev, dma->rx_dma_phys, - dspi->devtype_data->dma_bufsize, - DMA_FROM_DEVICE); + dma_bufsize, DMA_FROM_DEVICE); dma_release_channel(dma->chan_rx); } } From patchwork Tue Mar 10 12:55:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11429325 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 605FA924 for ; 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Tue, 10 Mar 2020 05:55:57 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v3 5/7] spi: spi-fsl-dspi: Add support for LS1028A Date: Tue, 10 Mar 2020 14:55:40 +0200 Message-Id: <20200310125542.5939-6-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200310125542.5939-1-olteanv@gmail.com> References: <20200310125542.5939-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean This is similar to the DSPI instantiation on LS1028A, except that: - The A-011218 erratum has been fixed, so DMA works - The endianness is different, which has implications on XSPI mode Some benchmarking with the following command: spidev_test --device /dev/spidev2.0 --bpw 8 --size 256 --cpha --iter 10000000 --speed 20000000 shows that in DMA mode, it can achieve around 2400 kbps, and in XSPI mode, the same command goes up to 4700 kbps. This is somewhat to be expected, since the DMA buffer size is extremely small at 8 bytes, the winner becomes whomever can prepare the buffers for transmission quicker, and DMA mode has higher overhead there. So XSPI FIFO mode has been chosen as the operating mode for this chip. Signed-off-by: Vladimir Oltean --- Changes in v3: Removed the dma_bufsize variable (obsoleted by 4/7). Changes in v2: Switch to DSPI_XSPI_MODE. drivers/spi/spi-fsl-dspi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 8f5d18dc78d5..fd1f04b996f7 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -124,6 +124,7 @@ struct fsl_dspi_devtype_data { enum { LS1021A, LS1012A, + LS1028A, LS1043A, LS1046A, LS2080A, @@ -151,6 +152,11 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .max_clock_factor = 8, .fifo_size = 16, }, + [LS1028A] = { + .trans_mode = DSPI_XSPI_MODE, + .max_clock_factor = 8, + .fifo_size = 4, + }, [LS1043A] = { /* Has A-011218 DMA erratum */ .trans_mode = DSPI_XSPI_MODE, @@ -1112,6 +1118,9 @@ static const struct of_device_id fsl_dspi_dt_ids[] = { }, { .compatible = "fsl,ls1012a-dspi", .data = &devtype_data[LS1012A], + }, { + .compatible = "fsl,ls1028a-dspi", + .data = &devtype_data[LS1028A], }, { .compatible = "fsl,ls1043a-dspi", .data = &devtype_data[LS1043A], From patchwork Tue Mar 10 12:55:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11429327 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEEC0139A for ; Tue, 10 Mar 2020 13:26:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8ED162071B for ; Tue, 10 Mar 2020 13:26:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tzw71jBu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728572AbgCJN0X (ORCPT ); Tue, 10 Mar 2020 09:26:23 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:34479 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729598AbgCJM4A (ORCPT ); Tue, 10 Mar 2020 08:56:00 -0400 Received: by mail-wm1-f65.google.com with SMTP id x3so713093wmj.1; Tue, 10 Mar 2020 05:55:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VLDdKHutiGZ5j/da9RiNBF1z620DpQjrWhoi+wnkAks=; b=tzw71jBuQlPaAugyIpg+S02LfWWCTiFq0XgGRWZx7NPKF9FtLWjmcvM7i5C4Iihx+I qSLHI7G9ZEAJz/8ASDM+Xwyyxy+a3IS2QU/w1w5k+uLIGQw5sVIdY86jhXEb2tdlLCb5 T4lJNZBEc5z7mul3FNPQTXgmbkVHEr6DFIiKx2ORp8QtsPicfaODYIeV2y4MveSls6Qx Z+xakFeYyp1SCbOtkiVIZoorO7npSJfO3Qs4Qdz5TKT21SxPzdjlAgZbf5MllaPdj/85 UsAhZAv6QUIZoaeKk2by6RRCLpC3AV0cG7kH0/7hkVt3tLVSv2Vc40uT0+R4ly/5Y1zU spvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VLDdKHutiGZ5j/da9RiNBF1z620DpQjrWhoi+wnkAks=; b=SYMopCPpv3HraPE4FXIZKn5PfTvOAT+gH3LHXjsOQkP0oVMSAv97zuSmoNa69NCnyO HHPKg38CRIQ6Yj2ErK0YcRDZ6gWe96axb7H1H12vIzbiQKMuDOHoG1MGjW+DSi/iiEko zOE/ZfDMYFSqc/6h5qAejflya3xdbaIcmbw2KQJK4WYT9vQMI2E4ouH0eXCR/7Q1mff+ 1lDLWpuC10ZXF+O80Zsyqa0SPYXaQsx+jm8kuEd+qaT6NcMJW+Ba35mFtJq4snfZOLtd QhKn6ACRiLxg8RcYWdukfEZn76wP9NxG8UA4C6JbyLNhnsx7Y31uRyFyDftnlxze4oJj qQYg== X-Gm-Message-State: ANhLgQ0w0QB5LIUu5VOWtYKg7P5QLmMYxZvciuOyt+woxRRxBVZ0eNzO KUuegBu/pQ/QqrPCHVmwUsk= X-Google-Smtp-Source: ADFU+vte0i3R1bbs4utymUqUI2PnS8WJx/xlpXtoYNvKWWQaBO6W5FtTYMK9O7MZL8PXPbRYf+7XOw== X-Received: by 2002:a1c:cc11:: with SMTP id h17mr2194107wmb.154.1583844959124; Tue, 10 Mar 2020 05:55:59 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id t81sm4018594wmb.15.2020.03.10.05.55.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 05:55:58 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v3 6/7] arm64: dts: ls1028a: Specify the DMA channels for the DSPI controllers Date: Tue, 10 Mar 2020 14:55:41 +0200 Message-Id: <20200310125542.5939-7-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200310125542.5939-1-olteanv@gmail.com> References: <20200310125542.5939-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean LS1028A has a functional connection to the eDMA module. Even if the spi-fsl-dspi.c driver is not using DMA for LS1028A now, define the slots in the DMAMUX for connecting the eDMA channels to the 3 DSPI controllers. Signed-off-by: Vladimir Oltean --- Changes in v3: None. Changes in v2: None. arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 515e0a1b934f..18155273a46e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -298,6 +298,8 @@ interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 1>; + dmas = <&edma0 0 62>, <&edma0 0 60>; + dma-names = "tx", "rx"; spi-num-chipselects = <4>; little-endian; status = "disabled"; @@ -311,6 +313,8 @@ interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 1>; + dmas = <&edma0 0 58>, <&edma0 0 56>; + dma-names = "tx", "rx"; spi-num-chipselects = <4>; little-endian; status = "disabled"; @@ -324,6 +328,8 @@ interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 1>; + dmas = <&edma0 0 54>, <&edma0 0 2>; + dma-names = "tx", "rx"; spi-num-chipselects = <3>; little-endian; status = "disabled"; From patchwork Tue Mar 10 12:55:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 11429263 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0473B92A for ; Tue, 10 Mar 2020 12:56:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D7D6B2253D for ; Tue, 10 Mar 2020 12:56:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lxNhQrpb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728416AbgCJM4E (ORCPT ); Tue, 10 Mar 2020 08:56:04 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:36291 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729617AbgCJM4E (ORCPT ); Tue, 10 Mar 2020 08:56:04 -0400 Received: by mail-wr1-f68.google.com with SMTP id s5so11822830wrg.3; Tue, 10 Mar 2020 05:56:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2LDQl7IwXLsgWdbG7WRtsJmahe9ELOlGpRrYf324SYo=; b=lxNhQrpbCvDIY90uCxn9ackV2e5ym09lQFAFBY/o3J5La4Tr6bltCGO/l/M7GJn1WV aeItkqxWusoI6rOx54r6UQC485PvfypqIBMsNOoW8n5H5WTG0UJpAlqbFCnEVgTYhCur z8fDmilP6rK66SETC+po7FWPDW/GYEHpTKcs2izqvPn6O8lwK8kzez76IoH2f4SbK9/w sm5DayClua4cPshUqiX8c1/umPhaNj4BDT7a+OoPNHA+4K3OJHd/pO9CAo+TunJ4tIm4 jEx8X0ne+dbXriVX+KLv98Psb2qUD2fKR0Q83bsz4MFGkl2780r81D8DRKnZxLFnNbU5 vW9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2LDQl7IwXLsgWdbG7WRtsJmahe9ELOlGpRrYf324SYo=; b=oFEJVge6RdpJMi1UsfO4yehrPn0MAb21xIKCLNaap+IP3x6JkUsM9dNldgq7D23Vdd BQ5w/Zkw6Ncmv9UgEe1WajIga4lum3vDIiXT/vyAdMUEhFoUtx0zbk3HNMJl0QmyEuiS +qgskGMkb0PSulJWRRWp++qd7aOtyCJXl29UNtC7EaRyyZv+WgyjO454+O7NGBHopoYg syL8RNJUCZNDav9jnPMhY8nilLXYgcLUtLE0tXyT88wqgaDzxpVY4kNcyO1I7HxhNsAd vAc8BmuU6yB3uXX+YaN3MKycwV/9XBTUiHPOG/DhZN5402xXayS9wr4l7n1vtk/I9MIw d7KA== X-Gm-Message-State: ANhLgQ2ayejHh61bKOEft+GHPi6Vo7mSy4rNWTPhV/jeHD/zCDWdogrH adQ4ABCQQxEfqsmf7kXTWAU= X-Google-Smtp-Source: ADFU+vttnPba9hD6mVrnvClOOK8HMD0cDCtk1Jsgf9RHvW5Hvh+3+czQ4K4PfLPn248oQkZAfW2vjw== X-Received: by 2002:a5d:4c4a:: with SMTP id n10mr28574797wrt.116.1583844960527; Tue, 10 Mar 2020 05:56:00 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id t81sm4018594wmb.15.2020.03.10.05.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 05:56:00 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v3 7/7] arm64: dts: ls1028a-rdb: Add a spidev node for the mikroBUS Date: Tue, 10 Mar 2020 14:55:42 +0200 Message-Id: <20200310125542.5939-8-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200310125542.5939-1-olteanv@gmail.com> References: <20200310125542.5939-1-olteanv@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Vladimir Oltean For debugging, it is useful to have access to the DSPI controller signals. On the reference design board, these are exported to either the mikroBUS1 or mikroBUS2 connector (according to the CPLD register BRDCFG3[SPI3]). Signed-off-by: Vladimir Oltean --- Changes in v3: None. Changes in v2: Change compatible string for spidev node. arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index bb7ba3bcbe56..13555ed52b89 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -83,6 +83,20 @@ }; }; +&dspi2 { + bus-num = <2>; + status = "okay"; + + /* mikroBUS1 */ + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <20000000>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <100>; + reg = <0>; + }; +}; + &esdhc { sd-uhs-sdr104; sd-uhs-sdr50;