From patchwork Wed Mar 11 12:34:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11431553 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4079217D5 for ; Wed, 11 Mar 2020 12:35:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2052C24658 for ; Wed, 11 Mar 2020 12:35:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="IuFRQGUw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729442AbgCKMfd (ORCPT ); Wed, 11 Mar 2020 08:35:33 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:34091 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729286AbgCKMfK (ORCPT ); Wed, 11 Mar 2020 08:35:10 -0400 Received: by mail-wm1-f65.google.com with SMTP id x3so3079082wmj.1 for ; Wed, 11 Mar 2020 05:35:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xBDvlQYuE7oNVEONMOO8X/XPChxn1w8gmsgCTidgsCw=; b=IuFRQGUwIPudbPryb66bcSA98/I2fxKUyrPgEpzM7Mb1lLK/P5FF7MyO9h4p4VuskT Yhj5pXVHXTjcli+/HkP3VCsvmL+0g7IDTKiR7iP8+19qQezBMpShkj0kc9XzgONY9raR 3g/ISgcPg3tku4y6jDUrfUqWQ4PSlKmyYwjAhVUV/HQrAq588PH7mliHe1N9X2CsiJaS Vh7+v4NBPDpqXijwB5Q3YUjjz5RacSyPKqEoZ1sHQ1iQQF59sXVnvba0AZXushksIgxf +eWPmswyHwbr3v1abaV5i3iPcYkzE+S0pQ0L57aPZzswXFAsFlBiiXkt5SXrAqu5t2kd Im7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xBDvlQYuE7oNVEONMOO8X/XPChxn1w8gmsgCTidgsCw=; b=HNYeeh7ZnQlImt2vx9GyaioBCgBqQkD+fY01Xnzkjt1GzJnbKvFsrFfGg6KOv0/M5v DUwlhi8l8raD+eriqHfCG3/KzXj5n8vu19YGGpjSuKsHrFJ1r4ns0A03U3u7zbaIOuvd 6d9vtAZcvdbslVhug+jfKAkAFulI5cNOF9LuttRALQZ8iE9QTSnqORYvuoO1/SfeN7XQ 1KvT11Hx/8cBPPmNxgmynvMibpps4U9Y6OryYTfUvMKaTnemK2g1tuuinSQP22ZQDOJg v4SYW3+clujpwGXpUPb+rUT21ps7Wss5BEWJFEZ75GyvANanWuDYTbfxLmxjyLJjBFoa YJrg== X-Gm-Message-State: ANhLgQ26Dy7ZHoZ3IVivHb1UuR0Junx6X08bhLIQ18NMnY5PGJAjoLEg +XC4qEXidxQEyq54TMXCJjtQCQ== X-Google-Smtp-Source: ADFU+vsQz6jYa7lO28kY389afQXTOf18x6yaQthL0HYfPi/AgNw2jQwmb4F0so/4szpPJCmFHz6GRg== X-Received: by 2002:a1c:23d5:: with SMTP id j204mr3724311wmj.59.1583930107055; Wed, 11 Mar 2020 05:35:07 -0700 (PDT) Received: from xps7590.local ([2a02:2450:102f:13b8:9087:3e80:4ebc:ae7b]) by smtp.gmail.com with ESMTPSA id m25sm7822732wml.35.2020.03.11.05.35.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 05:35:06 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, olof@lixom.net, Anson.Huang@nxp.com, maxime@cerno.tech, leonard.crestez@nxp.com, dinguyen@kernel.org, marcin.juszkiewicz@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain Cc: Robert Foss Subject: [v1 1/6] arm64: dts: msm8916: Add i2c-qcom-cci node Date: Wed, 11 Mar 2020 13:34:56 +0100 Message-Id: <20200311123501.18202-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200311123501.18202-1-robert.foss@linaro.org> References: <20200311123501.18202-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Loic Poulain The msm8916 CCI controller provides one CCI/I2C bus. Signed-off-by: Loic Poulain Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 9f31064f2374..afe1d73e5cd3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1503,6 +1503,33 @@ }; }; + cci@1b0c000 { + compatible = "qcom,msm8916-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1b0c000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", "cci_ahb", + "cci", "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <19200000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>; + status = "disabled"; + + cci0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: camss@1b00000 { compatible = "qcom,msm8916-camss"; reg = <0x1b0ac00 0x200>, From patchwork Wed Mar 11 12:34:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11431551 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5BEB51874 for ; Wed, 11 Mar 2020 12:35:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3A13621D7E for ; Wed, 11 Mar 2020 12:35:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="cwJE67Do" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729287AbgCKMfK (ORCPT ); Wed, 11 Mar 2020 08:35:10 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:39737 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729332AbgCKMfJ (ORCPT ); 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Wed, 11 Mar 2020 05:35:08 -0700 (PDT) Received: from xps7590.local ([2a02:2450:102f:13b8:9087:3e80:4ebc:ae7b]) by smtp.gmail.com with ESMTPSA id m25sm7822732wml.35.2020.03.11.05.35.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 05:35:08 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, olof@lixom.net, Anson.Huang@nxp.com, maxime@cerno.tech, leonard.crestez@nxp.com, dinguyen@kernel.org, marcin.juszkiewicz@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain Cc: Robert Foss Subject: [v1 2/6] arm64: dts: apq8016-sbc: Add CCI/Sensor nodes Date: Wed, 11 Mar 2020 13:34:57 +0100 Message-Id: <20200311123501.18202-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200311123501.18202-1-robert.foss@linaro.org> References: <20200311123501.18202-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Loic Poulain Add cci device to msm8916.dtsi. Add default 96boards camera node for db410c (apq8016-sbc). Signed-off-by: Loic Poulain Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 75 +++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 037e26b3f8d5..a3e6982f4f93 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -495,6 +495,81 @@ wcnss@a21b000 { status = "okay"; }; + + camera_vdddo_1v8: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera_vdda_2v8: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + camera_vddd_1v5: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + cci@1b0c000 { + status = "ok"; + i2c-bus@0 { + camera_rear@3b { + compatible = "ovti,ov5640"; + reg = <0x3b>; + + enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>; + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "xclk"; + clock-frequency = <23880000>; + + vdddo-supply = <&camera_vdddo_1v8>; + vdda-supply = <&camera_vdda_2v8>; + vddd-supply = <&camera_vddd_1v5>; + + /* No camera mezzanine by default */ + status = "okay"; + + port { + ov5640_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; + }; + + camss@1b00000 { + status = "ok"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csiphy0_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&ov5640_ep>; + status = "okay"; + }; + }; + }; + }; }; usb2513 { From patchwork Wed Mar 11 12:34:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11431549 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B956617D5 for ; Wed, 11 Mar 2020 12:35:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8FAB222B48 for ; Wed, 11 Mar 2020 12:35:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yu5/OhSa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729428AbgCKMfN (ORCPT ); Wed, 11 Mar 2020 08:35:13 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:36682 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729411AbgCKMfM (ORCPT ); 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Wed, 11 Mar 2020 05:35:10 -0700 (PDT) Received: from xps7590.local ([2a02:2450:102f:13b8:9087:3e80:4ebc:ae7b]) by smtp.gmail.com with ESMTPSA id m25sm7822732wml.35.2020.03.11.05.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 05:35:09 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, olof@lixom.net, Anson.Huang@nxp.com, maxime@cerno.tech, leonard.crestez@nxp.com, dinguyen@kernel.org, marcin.juszkiewicz@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain Cc: Robert Foss Subject: [v1 3/6] arm64: dts: sdm845: Add i2c-qcom-cci node Date: Wed, 11 Mar 2020 13:34:58 +0100 Message-Id: <20200311123501.18202-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200311123501.18202-1-robert.foss@linaro.org> References: <20200311123501.18202-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The sdm845 SOC ships with a CCI controller, which has two CCI/I2C buses. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 110 +++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index eb77aaa6a819..a6b6837c3d68 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -583,3 +583,7 @@ bias-pull-up; }; }; + +&cci { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d42302b8889b..b7f5c0b0f6af 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -717,6 +718,14 @@ #power-domain-cells = <1>; }; + clock_camcc: clock-controller@ad00000 { + compatible = "qcom,sdm845-camcc"; + reg = <0 0xad00000 0 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + qfprom@784000 { compatible = "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>; @@ -1451,6 +1460,60 @@ gpio-ranges = <&tlmm 0 0 150>; wakeup-parent = <&pdc_intc>; + cci0_default: cci0_default { + /* SDA, SCL */ + pinmux { + function = "cci_i2c"; + pins = "gpio17", "gpio18"; + }; + pinconf { + pins = "gpio17", "gpio18"; + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + }; + + cci0_sleep: cci0_sleep { + /* SDA, SCL */ + mux { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + }; + + cci1_default: cci1_default { + /* SDA, SCL */ + pinmux { + function = "cci_i2c"; + pins = "gpio19", "gpio20"; + }; + pinconf { + pins = "gpio19", "gpio20"; + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + }; + + cci1_sleep: cci1_sleep { + /* SDA, SCL */ + mux { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19", "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + }; + qspi_clk: qspi-clk { pinmux { pins = "gpio95"; @@ -2608,6 +2671,53 @@ #reset-cells = <1>; }; + cci: cci@ac4a000 { + compatible = "qcom,sdm845-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0xac4a000 0 0x4000>; + interrupts = ; + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cci", + "cci_clk_src"; + + assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + mdss: mdss@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; From patchwork Wed Mar 11 12:34:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11431539 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E889924 for ; Wed, 11 Mar 2020 12:35:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C4F321655 for ; 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Wed, 11 Mar 2020 05:35:10 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, olof@lixom.net, Anson.Huang@nxp.com, maxime@cerno.tech, leonard.crestez@nxp.com, dinguyen@kernel.org, marcin.juszkiewicz@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain Cc: Robert Foss Subject: [v1 4/6] arm64: dts: sdm845-db845c: Add pm_8998 gpio names Date: Wed, 11 Mar 2020 13:34:59 +0100 Message-Id: <20200311123501.18202-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200311123501.18202-1-robert.foss@linaro.org> References: <20200311123501.18202-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add pm_8998 GPIO trace names. These names are defined in the 96boards db845c mezzanine schematic. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index a6b6837c3d68..e8c056d02ace 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -584,6 +584,36 @@ }; }; +&pm8998_gpio { + gpio-line-names = + "NC", + "NC", + "WLAN_SW_CTRL", + "NC", + "PM_GPIO5_BLUE_BT_LED", + "VOL_UP_N", + "NC", + "ADC_IN1", + "PM_GPIO9_YEL_WIFI_LED", + "CAM0_AVDD_EN", + "NC", + "CAM0_DVDD_EN", + "PM_GPIO13_GREEN_U4_LED", + "DIV_CLK2", + "NC", + "NC", + "NC", + "SMB_STAT", + "NC", + "NC", + "ADC_IN2", + "OPTION1", + "WCSS_PWR_REQ", + "PM845_GPIO24", + "OPTION2", + "PM845_SLB"; +}; + &cci { status = "ok"; }; From patchwork Wed Mar 11 12:35:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11431543 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD935924 for ; Wed, 11 Mar 2020 12:35:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B1F99222C3 for ; Wed, 11 Mar 2020 12:35:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="mWiG+P2p" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729447AbgCKMfR (ORCPT ); Wed, 11 Mar 2020 08:35:17 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:40465 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729423AbgCKMfO (ORCPT ); Wed, 11 Mar 2020 08:35:14 -0400 Received: by mail-wr1-f65.google.com with SMTP id p2so2390197wrw.7 for ; Wed, 11 Mar 2020 05:35:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EsLey6y6SKlRjbgkIy31jgpCjMbbEJbmH2TS7XD1nHc=; b=mWiG+P2pZRLmizuh34OhP27MX0SBZMGPPLs/YPdMWgllcaWklbh7guy+08eWuXJxUs /Ipa746mPKuK+LfdBgdCATUcP++GWjeRDVtWby9q6vrnLC3u8J3gz1p9ZzHgjR3wNjpi q0UScWG0vPv/cXxV04mA2UVSBScF+okNEXCzyP//2YejVgmnuaGvOS9Nu7QX1dzbziUM qn8Ei1PCD4Kuj+vXVgwK2QHlxknkWkfo6IyW/IkKBAfrj69PeeefnDH4g8BF253gwr0q 4ezC/kATL6VKJuEb55xEHxFeYYbe5+1+tpRTvFU3I3CuDZ8l1SSkvDVTW44s8MUVqlFY uckw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EsLey6y6SKlRjbgkIy31jgpCjMbbEJbmH2TS7XD1nHc=; b=jlrnfHLHhOXrKRnU5d3mCT6HbYKmIecsY2Fq9fX+3ImmXJpG5SkCirnxjVHWv7R0PY H7KD3J4vBe14OrbsdN43E10V6riCXE4ruLZTEsmsbURIUIOBxsc6YcLA1EMZ+s3LsGwu t1tpyY1aCY+CtePS95ATlaJDJjIOsSMa/nTnjPoxbAOfpTKP+8bjqLmBbhXDh1cc6CK5 7vxtm67e69V5je0RPqqgyGZKsxC4ZZ+U29jyCs05qPue1t0q/NJMmUsXjAQuLRKRixF3 QDHWiPA3KMuvIU+Jl9ZnhJwFff/x+Frhi17YQMs51nc6W5HEf86Strztd91Vg5sUT+dh 43VQ== X-Gm-Message-State: ANhLgQ3H8YtxSiMeQOnbUNX/JkbXZk4r0y4WuDikc7K8JdqNR+G3mv9g gjyxy7yI0fsqvmwOPL10zySERA== X-Google-Smtp-Source: ADFU+vsLDiiJL2pTGClrrfzghrj2bi6GXYebxKsoYlZUpQHtyIgYMG+4GTMEmr09Abr3Us8gL5WUSw== X-Received: by 2002:adf:b19e:: with SMTP id q30mr4265494wra.163.1583930112809; Wed, 11 Mar 2020 05:35:12 -0700 (PDT) Received: from xps7590.local ([2a02:2450:102f:13b8:9087:3e80:4ebc:ae7b]) by smtp.gmail.com with ESMTPSA id m25sm7822732wml.35.2020.03.11.05.35.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 05:35:12 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, olof@lixom.net, Anson.Huang@nxp.com, maxime@cerno.tech, leonard.crestez@nxp.com, dinguyen@kernel.org, marcin.juszkiewicz@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain Cc: Robert Foss Subject: [v1 5/6] arm64: dts: sdm845-db845c: Add ov8856 & ov7251 camera nodes Date: Wed, 11 Mar 2020 13:35:00 +0100 Message-Id: <20200311123501.18202-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200311123501.18202-1-robert.foss@linaro.org> References: <20200311123501.18202-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the ov8856 main camera and the ov7251 b/w tracking camera used on the Qualcomm RB3 kit. Currently the camera nodes have not yet been attached to an to a CSI2 endpoint, since no driver currently supports the ISP that the the SDM845/db845c ships with. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 239 +++++++++++++++++++++ 1 file changed, 239 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index e8c056d02ace..660550197ce9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -110,6 +110,53 @@ // enable-active-high; }; + cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_DVDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + enable-active-high; + gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_dvdd_1v2_en_default>; + vin-supply = <&vbat>; + }; + + cam0_avdd_2v8: reg_cam0_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_avdd_2v8_en_default>; + vin-supply = <&vbat>; + }; + + /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ + cam3_avdd_2v8: reg_cam3_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM3_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vbat>; + }; + + /* This regulator does not really exits, but a 'vddd-supply' is + * required for the ov7251 driver, but no 'vddd' regulator is used + * in the schematic + */ + cam3_vddd_1v2: reg_cam3_vddd_1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAM3_VDDD_1V2_DUMMY"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <&vbat>; + }; + pcie0_3p3v_dual: vldo-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "VLDO_3V3"; @@ -406,6 +453,81 @@ }; &tlmm { + pcie0_default_state: pcie0-default { + clkreq { + pins = "gpio36"; + function = "pci_e0"; + bias-pull-up; + }; + + reset-n { + pins = "gpio35"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n { + pins = "gpio37"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + cam0_default: cam0_default { + mux_rst { + function = "gpio"; + pins = "gpio9"; + }; + config_rst { + pins = "gpio9"; + drive-strength = <16>; + bias-disable; + }; + + mux_mclk0 { + function = "cam_mclk"; + pins = "gpio13"; + }; + config_mclk0 { + pins = "gpio13"; + drive-strength = <16>; + bias-disable; + }; + }; + + cam3_default: cam3_default { + mux_rst { + function = "gpio"; + pins = "gpio21"; + }; + config_rst { + pins = "gpio21"; + drive-strength = <16>; + bias-disable; + }; + + mux_mclk3 { + function = "cam_mclk"; + pins = "gpio16"; + }; + config_mclk3 { + pins = "gpio16"; + drive-strength = <16>; + bias-disable; + }; + }; + + lt9611_irq_pin: lt9611-irq { + pins = "gpio84"; + function = "gpio"; + bias-disable; + }; + pcie0_pwren_state: pcie0-pwren { pins = "gpio90"; function = "gpio"; @@ -612,8 +734,125 @@ "PM845_GPIO24", "OPTION2", "PM845_SLB"; + + cam0_dvdd_1v2_en_default: cam0_dvdd_1v2_en_pinctrl { + pins = "gpio12"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = ; + }; + + cam0_avdd_2v8_en_default: cam0_avdd_2v8_en_pinctrl { + pins = "gpio10"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = ; + }; }; &cci { status = "ok"; + + i2c-bus@0 { + cam0@10 { + compatible = "ovti,ov8856"; + + /* The Qualcomm RB3 camera mezzanine schematic lists + * 0x20 as I2C address of this device, but the Linux + * kernel documentation lists 0x10 I2C address. + */ + reg = <0x10>; + + // CAM0_RST_N + reset-gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_default>; + gpios = <&tlmm 13 0>, + <&tlmm 9 0>; + + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "xvclk"; + clock-frequency = <19200000>; + + + /* The &vreg_s4a_1p8 trace is powered on as a + * part of the TITAN_TOP_GDSC power domain. + * So it is represented by a fixed regulator. + * + * The 2.8V vdda-supply and 1.2V vddd-supply regulators + * both have to be enabled through the power management + * gpios. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + dovdd-supply = <&vreg_lvs1a_1p8>; + avdd-supply = <&cam0_avdd_2v8>; + dvdd-supply = <&cam0_dvdd_1v2>; + + /* No camera mezzanine by default */ + status = "ok"; + + port { + ov8856_ep: endpoint { + clock-lanes = <1>; + link-frequencies = /bits/ 64 + <360000000 180000000>; + data-lanes = <1 2 3 4>; +// remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; + + i2c-bus@1 { + cam3@60 { + compatible = "ovti,ov7251"; + + // I2C address as per ov7251.txt linux documentation + reg = <0x60>; + + // CAM3_RST_N + enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam3_default>; + gpios = <&tlmm 16 0>, + <&tlmm 21 0>; + + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "xclk"; + clock-frequency = <24000000>; + + /* The &vreg_s4a_1p8 trace is powered on as a + * part of the TITAN_TOP_GDSC power domain. + * So it is represented by a fixed regulator. + * + * The 2.8V vdda-supply regulator is enabled when the + * vreg_s4a_1p8 trace is pulled high. + * It too is represented by a fixed regulator. + * + * No 1.2V vddd-supply regulator is used, a fixed + * regulator represents it. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + vdddo-supply = <&vreg_lvs1a_1p8>; + vdda-supply = <&cam3_avdd_2v8>; + vddd-supply = <&cam3_vddd_1v2>; + + /* No camera mezzanine by default */ + status = "ok"; + + port { + ov7251_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 1>; +// remote-endpoint = <&csiphy3_ep>; + }; + }; + }; + }; }; From patchwork Wed Mar 11 12:35:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11431545 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 42BA1924 for ; Wed, 11 Mar 2020 12:35:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 21E34222C3 for ; Wed, 11 Mar 2020 12:35:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G815P8fy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729423AbgCKMfR (ORCPT ); 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Wed, 11 Mar 2020 05:35:13 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, olof@lixom.net, Anson.Huang@nxp.com, maxime@cerno.tech, leonard.crestez@nxp.com, dinguyen@kernel.org, marcin.juszkiewicz@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain Cc: Robert Foss Subject: [v1 6/6] arm64: defconfig: Enable QCOM CAMCC, CAMSS and CCI drivers Date: Wed, 11 Mar 2020 13:35:01 +0100 Message-Id: <20200311123501.18202-7-robert.foss@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200311123501.18202-1-robert.foss@linaro.org> References: <20200311123501.18202-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Build camera clock, isp and controller drivers as modules. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4db223dbc549..7cb6989249ab 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -376,6 +376,7 @@ CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y CONFIG_I2C_OWL=y CONFIG_I2C_PXA=y +CONFIG_I2C_QCOM_CCI=m CONFIG_I2C_QCOM_GENI=m CONFIG_I2C_QUP=y CONFIG_I2C_RK3X=y @@ -530,6 +531,7 @@ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_RENESAS_FCP=m CONFIG_VIDEO_RENESAS_VSP1=m +CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_DRM=m CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_NOUVEAU=m @@ -732,6 +734,7 @@ CONFIG_MSM_GCC_8994=y CONFIG_MSM_MMCC_8996=y CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y +CONFIG_SDM_CAMCC_845=m CONFIG_SDM_GCC_845=y CONFIG_SM_GCC_8150=y CONFIG_QCOM_HFPLL=y @@ -762,6 +765,7 @@ CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_GENI_SE=y CONFIG_QCOM_GLINK_SSR=m CONFIG_QCOM_RMTFS_MEM=m +CONFIG_SDM_CAMCC_845=m CONFIG_QCOM_RPMH=y CONFIG_QCOM_RPMHPD=y CONFIG_QCOM_SMEM=y