From patchwork Fri Mar 13 13:12:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 11436881 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 219A8921 for ; Fri, 13 Mar 2020 13:12:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0027F2074E for ; Fri, 13 Mar 2020 13:12:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="AzvMnHGd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726591AbgCMNMq (ORCPT ); Fri, 13 Mar 2020 09:12:46 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:64044 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726594AbgCMNMq (ORCPT ); Fri, 13 Mar 2020 09:12:46 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1584105165; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=IyOU3O6vZkvClFfdzNJ2tEJ6rtPVF6loCCxH7MpU/9I=; b=AzvMnHGd5xNcvcHGxsVCKvAZu0gflCawaiE1NUo0t6bsh8+dqn3+cAOdlCqtogozYR6BEwgK 3802xheY7+eFJZgI9VLFIGc8Ody5tLxiGz4Rhs6I67rK4+WKEpdyzim4Sakp8aZxYApJPx8R AWNQeXf5IjKO5Z/goaPH3qnwU4s= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e6b86cd.7f69cf52f260-smtp-out-n01; Fri, 13 Mar 2020 13:12:45 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 3F53FC433BA; Fri, 13 Mar 2020 13:12:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akashast-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akashast) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1EFFBC433D2; Fri, 13 Mar 2020 13:12:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1EFFBC433D2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, evgreen@chromium.org, Akash Asthana Subject: [PATCH V2 1/8] interconnect: Add devm_of_icc_get() as exported API for users Date: Fri, 13 Mar 2020 18:42:07 +0530 Message-Id: <1584105134-13583-2-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> References: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Users can use devm version of of_icc_get() to benefit from automatic resource release. Signed-off-by: Akash Asthana Reviewed-by: Bjorn Andersson --- drivers/interconnect/core.c | 25 +++++++++++++++++++++++++ include/linux/interconnect.h | 7 +++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 2c6515e..f5699ed 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -350,6 +350,31 @@ static struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec) return node; } +static void devm_icc_release(struct device *dev, void *res) +{ + icc_put(*(struct icc_path **)res); +} + +struct icc_path *devm_of_icc_get(struct device *dev, const char *name) +{ + struct icc_path **ptr, *path; + + ptr = devres_alloc(devm_icc_release, sizeof(**ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + path = of_icc_get(dev, name); + if (!IS_ERR(path)) { + *ptr = path; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return path; +} +EXPORT_SYMBOL_GPL(devm_of_icc_get); + /** * of_icc_get() - get a path handle from a DT node based on name * @dev: device pointer for the consumer device diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h index d70a914..7706924 100644 --- a/include/linux/interconnect.h +++ b/include/linux/interconnect.h @@ -28,6 +28,7 @@ struct device; struct icc_path *icc_get(struct device *dev, const int src_id, const int dst_id); struct icc_path *of_icc_get(struct device *dev, const char *name); +struct icc_path *devm_of_icc_get(struct device *dev, const char *name); void icc_put(struct icc_path *path); int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw); void icc_set_tag(struct icc_path *path, u32 tag); @@ -46,6 +47,12 @@ static inline struct icc_path *of_icc_get(struct device *dev, return NULL; } +static inline struct icc_path *devm_of_icc_get(struct device *dev, + const char *name) +{ + return NULL; +} + static inline void icc_put(struct icc_path *path) { } From patchwork Fri Mar 13 13:12:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 11436889 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4325B14B4 for ; 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spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, evgreen@chromium.org, Akash Asthana Subject: [PATCH V2 2/8] soc: qcom: geni: Support for ICC voting Date: Fri, 13 Mar 2020 18:42:08 +0530 Message-Id: <1584105134-13583-3-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> References: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add necessary macros and structure variables to support ICC BW voting from individual SE drivers. Signed-off-by: Akash Asthana --- Changes in V2: - As per Bjorn's comment dropped enums for ICC paths, given the three paths individual members include/linux/qcom-geni-se.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h index dd46494..eaae16e 100644 --- a/include/linux/qcom-geni-se.h +++ b/include/linux/qcom-geni-se.h @@ -6,6 +6,8 @@ #ifndef _LINUX_QCOM_GENI_SE #define _LINUX_QCOM_GENI_SE +#include + /* Transfer mode supported by GENI Serial Engines */ enum geni_se_xfer_mode { GENI_SE_INVALID, @@ -33,6 +35,15 @@ struct clk; * @clk: Handle to the core serial engine clock * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock + * @icc_path_geni_to_core: ICC path handle for geni to core + * @icc_path_cpu_to_geni: ICC path handle for cpu to geni + * @icc_path_geni_to_ddr: ICC path handle for geni to ddr + * @avg_bw_core: Average bus bandwidth value for QUP core 2x clock + * @peak_bw_core: Peak bus bandwidth value for QUP core 2x clock + * @avg_bw_cpu: Average bus bandwidth value for CPU + * @peak_bw_cpu: Peak bus bandwidth value for CPU + * @avg_bw_ddr: Average bus bandwidth value for DDR + * @peak_bw_ddr: Peak bus bandwidth value for DDR */ struct geni_se { void __iomem *base; @@ -41,6 +52,15 @@ struct geni_se { struct clk *clk; unsigned int num_clk_levels; unsigned long *clk_perf_tbl; + struct icc_path *icc_path_geni_to_core; + struct icc_path *icc_path_cpu_to_geni; + struct icc_path *icc_path_geni_to_ddr; + unsigned int avg_bw_core; + unsigned int peak_bw_core; + unsigned int avg_bw_cpu; + unsigned int peak_bw_cpu; + unsigned int avg_bw_ddr; + unsigned int peak_bw_ddr; }; /* Common SE registers */ @@ -229,6 +249,14 @@ struct geni_se { #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) +/* Core 2X clock frequency to BCM threshold mapping */ +#define CORE_2X_19_2_MHZ 960 +#define CORE_2X_50_MHZ 2500 +#define CORE_2X_100_MHZ 5000 +#define CORE_2X_150_MHZ 7500 +#define CORE_2X_200_MHZ 10000 +#define CORE_2X_236_MHZ 16383 + #if IS_ENABLED(CONFIG_QCOM_GENI_SE) u32 geni_se_get_qup_hw_version(struct geni_se *se); From patchwork Fri Mar 13 13:12:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 11436885 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4A8381668 for ; Fri, 13 Mar 2020 13:13:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 29C6620724 for ; Fri, 13 Mar 2020 13:13:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="BaWhvaEB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726633AbgCMNNE (ORCPT ); Fri, 13 Mar 2020 09:13:04 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:54186 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726646AbgCMNNE (ORCPT ); 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Fri, 13 Mar 2020 13:12:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 364F9C433D2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, evgreen@chromium.org, Akash Asthana Subject: [PATCH V2 3/8] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Date: Fri, 13 Mar 2020 18:42:09 +0530 Message-Id: <1584105134-13583-4-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> References: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org V1 patch@https://patchwork.kernel.org/patch/11386469/ caused SC7180 system to reset at boot time. As QUP core clock is shared among all the SE drivers present on particular QUP wrapper, the reset seen is due to earlycon usage after QUP core clock is put to 0 from other SE drivers before real console comes up. As earlycon can't vote for it's QUP core need, to fix this add ICC support to common/QUP wrapper driver and put vote for QUP core from probe on behalf of earlycon and remove vote during sys suspend. Signed-off-by: Akash Asthana Reported-by: Matthias Kaehlcke --- drivers/soc/qcom/qcom-geni-se.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 7d622ea..d244dfc 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -90,6 +90,7 @@ struct geni_wrapper { struct device *dev; void __iomem *base; struct clk_bulk_data ahb_clks[NUM_AHB_CLKS]; + struct icc_path *icc_path_geni_to_core; }; #define QUP_HW_VER_REG 0x4 @@ -747,11 +748,50 @@ static int geni_se_probe(struct platform_device *pdev) } } +#ifdef CONFIG_SERIAL_EARLYCON + wrapper->icc_path_geni_to_core = devm_of_icc_get(dev, "qup-core"); + if (IS_ERR(wrapper->icc_path_geni_to_core)) + return PTR_ERR(wrapper->icc_path_geni_to_core); + /* + * Put minmal BW request on core clocks on behalf of early console. + * The vote will be removed in suspend call. + */ + ret = icc_set_bw(wrapper->icc_path_geni_to_core, Bps_to_icc(1000), + Bps_to_icc(1000)); + if (ret) { + dev_err(&pdev->dev, "%s: ICC BW voting failed for core\n", + __func__); + return ret; + } +#endif + dev_set_drvdata(dev, wrapper); dev_dbg(dev, "GENI SE Driver probed\n"); return devm_of_platform_populate(dev); } +static int __maybe_unused geni_se_sys_suspend(struct device *dev) +{ + struct geni_wrapper *wrapper = dev_get_drvdata(dev); + int ret; + +#ifdef CONFIG_SERIAL_EARLYCON + ret = icc_set_bw(wrapper->icc_path_geni_to_core, 0, 0); + if (ret) { + dev_err(dev, "%s: ICC BW remove failed for core\n", + __func__); + return ret; + } +#endif + + return 0; +} + +static const struct dev_pm_ops geni_se_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(geni_se_sys_suspend, + NULL) +}; + static const struct of_device_id geni_se_dt_match[] = { { .compatible = "qcom,geni-se-qup", }, {} @@ -762,6 +802,7 @@ static struct platform_driver geni_se_driver = { .driver = { .name = "geni_se_qup", .of_match_table = geni_se_dt_match, + .pm = &geni_se_pm_ops, }, .probe = geni_se_probe, }; From patchwork Fri Mar 13 13:12:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 11436897 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C27FA921 for ; Fri, 13 Mar 2020 13:13:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9833F2073E for ; Fri, 13 Mar 2020 13:13:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="xTVtKVoB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726705AbgCMNN2 (ORCPT ); Fri, 13 Mar 2020 09:13:28 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:28317 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726706AbgCMNN2 (ORCPT ); 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Fri, 13 Mar 2020 13:13:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3297EC44788 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, evgreen@chromium.org, Akash Asthana Subject: [PATCH V2 4/8] tty: serial: qcom_geni_serial: Add interconnect support Date: Fri, 13 Mar 2020 18:42:10 +0530 Message-Id: <1584105134-13583-5-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> References: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Get the interconnect paths for Uart based Serial Engine device and vote according to the baud rate requirement of the driver. Signed-off-by: Akash Asthana --- Changes in V2: - As per Bjorn's comment, removed se == NULL check from geni_serial_icc_get - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting path handle - As per Matthias comment, added error handling for icc_set_bw call drivers/tty/serial/qcom_geni_serial.c | 69 +++++++++++++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 272bae0..c8ad7e9 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -184,6 +184,19 @@ static struct qcom_geni_serial_port qcom_geni_console_port = { }, }; +static int geni_serial_icc_get(struct geni_se *se) +{ + se->icc_path_geni_to_core = devm_of_icc_get(se->dev, "qup-core"); + if (IS_ERR(se->icc_path_geni_to_core)) + return PTR_ERR(se->icc_path_geni_to_core); + + se->icc_path_cpu_to_geni = devm_of_icc_get(se->dev, "qup-config"); + if (IS_ERR(se->icc_path_cpu_to_geni)) + return PTR_ERR(se->icc_path_cpu_to_geni); + + return 0; +} + static int qcom_geni_serial_request_port(struct uart_port *uport) { struct platform_device *pdev = to_platform_device(uport->dev); @@ -962,6 +975,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, struct qcom_geni_serial_port *port = to_dev_port(uport, uport); unsigned long clk_rate; u32 ver, sampling_rate; + int ret; qcom_geni_serial_stop_rx(uport); /* baud rate */ @@ -983,6 +997,18 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; + /* + * Put BW vote only on CPU path as driver supports FIFO mode only. + * Assume peak_bw as twice of avg_bw. + */ + port->se.avg_bw_cpu = Bps_to_icc(baud); + port->se.peak_bw_cpu = Bps_to_icc(2 * baud); + ret = icc_set_bw(port->se.icc_path_cpu_to_geni, port->se.avg_bw_cpu, + port->se.peak_bw_cpu); + if (ret) + dev_err(uport->dev, "%s: ICC BW voting failed for cpu\n", + __func__); + /* parity */ tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); @@ -1208,16 +1234,40 @@ static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { struct qcom_geni_serial_port *port = to_dev_port(uport, uport); - + int ret; /* If we've never been called, treat it as off */ if (old_state == UART_PM_STATE_UNDEFINED) old_state = UART_PM_STATE_OFF; - if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) + if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { + /* Put BW vote for core clocks and CPU */ + ret = icc_set_bw(port->se.icc_path_geni_to_core, + port->se.avg_bw_core, port->se.peak_bw_core); + if (ret) + dev_err(uport->dev, "%s: ICC BW voting failed for core\n", + __func__); + + ret = icc_set_bw(port->se.icc_path_cpu_to_geni, + port->se.avg_bw_cpu, port->se.peak_bw_cpu); + if (ret) + dev_err(uport->dev, "%s: ICC BW voting failed for cpu\n", + __func__); + geni_se_resources_on(&port->se); - else if (new_state == UART_PM_STATE_OFF && - old_state == UART_PM_STATE_ON) + } else if (new_state == UART_PM_STATE_OFF && + old_state == UART_PM_STATE_ON) { geni_se_resources_off(&port->se); + /* Remove BW vote from core clocks and CPU */ + ret = icc_set_bw(port->se.icc_path_geni_to_core, 0, 0); + if (ret) + dev_err(uport->dev, "%s: ICC BW remove failed for core\n", + __func__); + + ret = icc_set_bw(port->se.icc_path_cpu_to_geni, 0, 0); + if (ret) + dev_err(uport->dev, "%s: ICC BW remove failed for cpu\n", + __func__); + } } static const struct uart_ops qcom_geni_console_pops = { @@ -1308,6 +1358,17 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; + ret = geni_serial_icc_get(&port->se); + if (ret) + return ret; + /* Set the bus quota to a reasonable value */ + port->se.avg_bw_core = console ? Bps_to_icc(1000) : + Bps_to_icc(CORE_2X_50_MHZ); + port->se.peak_bw_core = console ? Bps_to_icc(1000) : + Bps_to_icc(CORE_2X_100_MHZ); + port->se.avg_bw_cpu = Bps_to_icc(1000); + port->se.peak_bw_cpu = Bps_to_icc(1000); + port->name = devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); From patchwork Fri Mar 13 13:12:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 11436895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 60BD114B4 for ; Fri, 13 Mar 2020 13:13:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3FE6720724 for ; Fri, 13 Mar 2020 13:13:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="ThCfPjPE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726691AbgCMNN1 (ORCPT ); Fri, 13 Mar 2020 09:13:27 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:23902 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726692AbgCMNN1 (ORCPT ); Fri, 13 Mar 2020 09:13:27 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1584105207; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=TMCjXiCd22oaTIvt1nqWA3krN7Avu7WdjmJ3LXbEBQU=; b=ThCfPjPE3BKDmAOkq6mjsOR6pPuwYhSgDV3DtAH8zKwDNJ23r2IPIirgS+C2tnjRMDJmpkob 52cTqBC++yLzG15t6Z+83mFygp8PdC/igo53nMoa89b8cIW5TqngmuXRH2iSceW8S2I2D3Eb J8rJHJriJSYxPmNHwyYj/NEyHY4= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e6b86f1.7f1981611c00-smtp-out-n01; Fri, 13 Mar 2020 13:13:21 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id BF9F0C44793; Fri, 13 Mar 2020 13:13:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akashast-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akashast) by smtp.codeaurora.org (Postfix) with ESMTPSA id D8E6BC44793; Fri, 13 Mar 2020 13:13:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D8E6BC44793 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, evgreen@chromium.org, Akash Asthana Subject: [PATCH V2 5/8] i2c: i2c-qcom-geni: Add interconnect support Date: Fri, 13 Mar 2020 18:42:11 +0530 Message-Id: <1584105134-13583-6-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> References: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Get the interconnect paths for I2C based Serial Engine device and vote according to the bus speed of the driver. Signed-off-by: Akash Asthana --- Changes in V2: - As per Bjorn's comment, removed se == NULL check from geni_i2c_icc_get - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting path handle - As per Matthias comment, added error handling for icc_set_bw call drivers/i2c/busses/i2c-qcom-geni.c | 110 +++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 17abf60c..33ab685 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -163,6 +163,23 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); } +static int geni_i2c_icc_get(struct geni_se *se) +{ + se->icc_path_geni_to_core = devm_of_icc_get(se->dev, "qup-core"); + if (IS_ERR(se->icc_path_geni_to_core)) + return PTR_ERR(se->icc_path_geni_to_core); + + se->icc_path_cpu_to_geni = devm_of_icc_get(se->dev, "qup-config"); + if (IS_ERR(se->icc_path_cpu_to_geni)) + return PTR_ERR(se->icc_path_cpu_to_geni); + + se->icc_path_geni_to_ddr = devm_of_icc_get(se->dev, "qup-memory"); + if (IS_ERR(se->icc_path_geni_to_ddr)) + return PTR_ERR(se->icc_path_geni_to_ddr); + + return 0; +} + static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) { u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); @@ -563,6 +580,39 @@ static int geni_i2c_probe(struct platform_device *pdev) gi2c->adap.dev.of_node = pdev->dev.of_node; strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); + ret = geni_i2c_icc_get(&gi2c->se); + if (ret) + return ret; + /* + * Set the bus quota for core and cpu to a reasonable value for + * register access. + * Set quota for DDR based on bus speed, assume peak requirement + * as twice of avg bw. + */ + gi2c->se.avg_bw_core = Bps_to_icc(1000); + gi2c->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ); + gi2c->se.avg_bw_cpu = Bps_to_icc(1000); + gi2c->se.peak_bw_cpu = Bps_to_icc(1000); + gi2c->se.avg_bw_ddr = Bps_to_icc(gi2c->clk_freq_out); + gi2c->se.peak_bw_ddr = Bps_to_icc(2 * gi2c->clk_freq_out); + + /* Vote for core clocks and CPU for register access */ + ret = icc_set_bw(gi2c->se.icc_path_geni_to_core, gi2c->se.avg_bw_core, + gi2c->se.peak_bw_core); + if (ret) { + dev_err(&pdev->dev, "%s: ICC BW voting failed for core\n", + __func__); + return ret; + } + + ret = icc_set_bw(gi2c->se.icc_path_cpu_to_geni, gi2c->se.avg_bw_cpu, + gi2c->se.peak_bw_cpu); + if (ret) { + dev_err(&pdev->dev, "%s: ICC BW voting failed for cpu\n", + __func__); + return ret; + } + ret = geni_se_resources_on(&gi2c->se); if (ret) { dev_err(&pdev->dev, "Error turning on resources %d\n", ret); @@ -584,6 +634,19 @@ static int geni_i2c_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Error turning off resources %d\n", ret); return ret; } + /* Remove vote from core clocks and CPU */ + ret = icc_set_bw(gi2c->se.icc_path_geni_to_core, 0, 0); + if (ret) { + dev_err(&pdev->dev, "%s: ICC BW remove failed for core\n", + __func__); + return ret; + } + + ret = icc_set_bw(gi2c->se.icc_path_cpu_to_geni, 0, 0); + if (ret) { + dev_err(&pdev->dev, "%s: ICC BW remove failed for cpu\n", + __func__); + } dev_dbg(&pdev->dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); @@ -629,6 +692,28 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) gi2c->suspended = 1; } + /* Remove BW votes */ + ret = icc_set_bw(gi2c->se.icc_path_geni_to_core, 0, 0); + if (ret) { + dev_err_ratelimited(gi2c->se.dev, "%s: ICC BW remove failed for core\n", + __func__); + return ret; + } + + ret = icc_set_bw(gi2c->se.icc_path_cpu_to_geni, 0, 0); + if (ret) { + dev_err_ratelimited(gi2c->se.dev, "%s: ICC BW remove failed for cpu\n", + __func__); + return ret; + } + + ret = icc_set_bw(gi2c->se.icc_path_geni_to_ddr, 0, 0); + if (ret) { + dev_err_ratelimited(gi2c->se.dev, "%s: ICC BW remove failed for ddr\n", + __func__); + return ret; + } + return 0; } @@ -637,6 +722,31 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) int ret; struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); + /* Vote on Core, CPU and DDR path respectively */ + ret = icc_set_bw(gi2c->se.icc_path_geni_to_core, gi2c->se.avg_bw_core, + gi2c->se.peak_bw_core); + if (ret) { + dev_err_ratelimited(gi2c->se.dev, "%s: ICC BW voting failed for core\n", + __func__); + return ret; + } + + ret = icc_set_bw(gi2c->se.icc_path_cpu_to_geni, gi2c->se.avg_bw_cpu, + gi2c->se.peak_bw_cpu); + if (ret) { + dev_err_ratelimited(gi2c->se.dev, "%s: ICC BW voting failed for cpu\n", + __func__); + return ret; + } + + ret = icc_set_bw(gi2c->se.icc_path_geni_to_ddr, gi2c->se.avg_bw_ddr, + gi2c->se.peak_bw_ddr); + if (ret) { + dev_err_ratelimited(gi2c->se.dev, "%s: ICC BW voting failed for ddr\n", + __func__); + return ret; + } + ret = geni_se_resources_on(&gi2c->se); if (ret) return ret; From patchwork Fri Mar 13 13:12:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 11436903 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CBFC0921 for ; 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spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, evgreen@chromium.org, Akash Asthana Subject: [PATCH V2 6/8] spi: spi-geni-qcom: Add interconnect support Date: Fri, 13 Mar 2020 18:42:12 +0530 Message-Id: <1584105134-13583-7-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> References: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Get the interconnect paths for SPI based Serial Engine device and vote according to the current bus speed of the driver. Signed-off-by: Akash Asthana --- - As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting path handle - As per Matthias comment, added error handling for icc_set_bw call drivers/spi/spi-geni-qcom.c | 74 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index c397242..09c4709 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -118,6 +118,19 @@ static int get_spi_clk_cfg(unsigned int speed_hz, return ret; } +static int geni_spi_icc_get(struct geni_se *se) +{ + se->icc_path_geni_to_core = devm_of_icc_get(se->dev, "qup-core"); + if (IS_ERR(se->icc_path_geni_to_core)) + return PTR_ERR(se->icc_path_geni_to_core); + + se->icc_path_cpu_to_geni = devm_of_icc_get(se->dev, "qup-config"); + if (IS_ERR(se->icc_path_cpu_to_geni)) + return PTR_ERR(se->icc_path_cpu_to_geni); + + return 0; +} + static void handle_fifo_timeout(struct spi_master *spi, struct spi_message *msg) { @@ -234,6 +247,20 @@ static int setup_fifo_params(struct spi_device *spi_slv, return ret; } + /* + * Set BW quota for CPU as driver supports FIFO mode only. + * Assume peak bw as twice of avg bw. + */ + se->avg_bw_cpu = Bps_to_icc(mas->cur_speed_hz); + se->peak_bw_cpu = Bps_to_icc(2 * mas->cur_speed_hz); + ret = icc_set_bw(se->icc_path_cpu_to_geni, se->avg_bw_cpu, + se->peak_bw_cpu); + if (ret) { + dev_err(mas->dev, "%s: ICC BW voting failed for cpu\n", + __func__); + return ret; + } + clk_sel = idx & CLK_SEL_MSK; m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); @@ -578,6 +605,15 @@ static int spi_geni_probe(struct platform_device *pdev) spin_lock_init(&mas->lock); pm_runtime_enable(dev); + ret = geni_spi_icc_get(&mas->se); + if (ret) + goto spi_geni_probe_runtime_disable; + /* Set the bus quota to a reasonable value for register access */ + mas->se.avg_bw_core = Bps_to_icc(CORE_2X_50_MHZ); + mas->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ); + mas->se.avg_bw_cpu = Bps_to_icc(1000); + mas->se.peak_bw_cpu = Bps_to_icc(1000); + ret = spi_geni_init(mas); if (ret) goto spi_geni_probe_runtime_disable; @@ -616,14 +652,50 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) { struct spi_master *spi = dev_get_drvdata(dev); struct spi_geni_master *mas = spi_master_get_devdata(spi); + int ret; + + ret = geni_se_resources_off(&mas->se); + if (ret) + return ret; - return geni_se_resources_off(&mas->se); + ret = icc_set_bw(mas->se.icc_path_geni_to_core, 0, 0); + if (ret) { + dev_err_ratelimited(mas->dev, "%s: ICC BW remove failed for core\n", + __func__); + return ret; + } + + ret = icc_set_bw(mas->se.icc_path_cpu_to_geni, 0, 0); + if (ret) { + dev_err_ratelimited(mas->dev, "%s: ICC BW remove failed for cpu\n", + __func__); + return ret; + } + + return 0; } static int __maybe_unused spi_geni_runtime_resume(struct device *dev) { struct spi_master *spi = dev_get_drvdata(dev); struct spi_geni_master *mas = spi_master_get_devdata(spi); + int ret; + + ret = icc_set_bw(mas->se.icc_path_geni_to_core, mas->se.avg_bw_core, + mas->se.peak_bw_core); + if (ret) { + dev_err_ratelimited(mas->dev, "%s: ICC BW voting failed for core\n", + __func__); + return ret; + } + + ret = icc_set_bw(mas->se.icc_path_cpu_to_geni, mas->se.avg_bw_cpu, + mas->se.peak_bw_cpu); + if (ret) { + dev_err_ratelimited(mas->dev, "%s: ICC BW voting failed for cpu\n", + __func__); + return ret; + } return geni_se_resources_on(&mas->se); } From patchwork Fri Mar 13 13:12:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 11436905 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B0D5914B4 for ; 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spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, evgreen@chromium.org, Akash Asthana Subject: [PATCH V2 7/8] spi: spi-qcom-qspi: Add interconnect support Date: Fri, 13 Mar 2020 18:42:13 +0530 Message-Id: <1584105134-13583-8-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> References: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Get the interconnect paths for QSPI device and vote according to the current bus speed of the driver. Signed-off-by: Akash Asthana --- - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting path handle - As per Matthias comment, added error handling for icc_set_bw call drivers/spi/spi-qcom-qspi.c | 46 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index 3c4f83b..ad48f43 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -2,6 +2,7 @@ // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. #include +#include #include #include #include @@ -139,7 +140,10 @@ struct qcom_qspi { struct device *dev; struct clk_bulk_data *clks; struct qspi_xfer xfer; - /* Lock to protect xfer and IRQ accessed registers */ + struct icc_path *icc_path_cpu_to_qspi; + unsigned int avg_bw_cpu; + unsigned int peak_bw_cpu; + /* Lock to protect data accessed by IRQs */ spinlock_t lock; }; @@ -241,6 +245,20 @@ static int qcom_qspi_transfer_one(struct spi_master *master, return ret; } + /* + * Set BW quota for CPU as driver supports FIFO mode only. + * Assume peak bw as twice of avg bw. + */ + ctrl->avg_bw_cpu = Bps_to_icc(speed_hz); + ctrl->peak_bw_cpu = Bps_to_icc(2 * speed_hz); + ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, ctrl->avg_bw_cpu, + ctrl->peak_bw_cpu); + if (ret) { + dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu\n", + __func__); + return ret; + } + spin_lock_irqsave(&ctrl->lock, flags); /* We are half duplex, so either rx or tx will be set */ @@ -458,6 +476,15 @@ static int qcom_qspi_probe(struct platform_device *pdev) if (ret) goto exit_probe_master_put; + ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config"); + if (IS_ERR(ctrl->icc_path_cpu_to_qspi)) { + ret = PTR_ERR(ctrl->icc_path_cpu_to_qspi); + goto exit_probe_master_put; + } + /* Put BW vote on CPU path for register access */ + ctrl->avg_bw_cpu = Bps_to_icc(1000); + ctrl->peak_bw_cpu = Bps_to_icc(1000); + ret = platform_get_irq(pdev, 0); if (ret < 0) goto exit_probe_master_put; @@ -511,9 +538,17 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); struct qcom_qspi *ctrl = spi_master_get_devdata(master); + int ret; clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks); + ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, 0, 0); + if (ret) { + dev_err_ratelimited(ctrl->dev, "%s: ICC BW remove failed for cpu\n", + __func__); + return ret; + } + return 0; } @@ -521,6 +556,15 @@ static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); struct qcom_qspi *ctrl = spi_master_get_devdata(master); + int ret; + + ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, ctrl->avg_bw_cpu, + ctrl->peak_bw_cpu); + if (ret) { + dev_err_ratelimited(ctrl->dev, "%s: ICC BW voting failed for cpu\n", + __func__); + return ret; + } return clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks); } From patchwork Fri Mar 13 13:12:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 11436911 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D7F841668 for ; Fri, 13 Mar 2020 13:14:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AC16A20724 for ; Fri, 13 Mar 2020 13:14:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="IHDLfvIA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726726AbgCMNOB (ORCPT ); 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Fri, 13 Mar 2020 13:13:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akashast-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akashast) by smtp.codeaurora.org (Postfix) with ESMTPSA id D0BC0C44798; Fri, 13 Mar 2020 13:13:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D0BC0C44798 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, evgreen@chromium.org, Akash Asthana Subject: [PATCH V2 8/8] arm64: dts: sc7180: Add interconnect for QUP and QSPI Date: Fri, 13 Mar 2020 18:42:14 +0530 Message-Id: <1584105134-13583-9-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> References: <1584105134-13583-1-git-send-email-akashast@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add interconnect ports for GENI QUPs and QSPI to set bus capabilities. Signed-off-by: Akash Asthana --- Changes in V2: - As per Bjorn's comment, ignoring 80 char limit in defining interconnects paths. arch/arm64/boot/dts/qcom/sc7180.dtsi | 127 +++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 89ba012..5c0185c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -427,6 +427,8 @@ #size-cells = <2>; ranges; iommus = <&apps_smmu 0x43 0x0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>; + interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { @@ -439,6 +441,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -452,6 +459,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -463,6 +473,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart0_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -476,6 +489,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -489,6 +507,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -500,6 +521,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart1_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -513,6 +537,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -524,6 +553,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -537,6 +569,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -550,6 +587,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -561,6 +601,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -574,6 +617,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -585,6 +633,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart4_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -598,6 +649,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -611,6 +667,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -622,6 +681,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart5_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; @@ -636,6 +698,8 @@ #size-cells = <2>; ranges; iommus = <&apps_smmu 0x4c3 0x0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>; + interconnect-names = "qup-core"; status = "disabled"; i2c6: i2c@a80000 { @@ -648,6 +712,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -661,6 +730,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -672,6 +744,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -685,6 +760,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -696,6 +776,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -709,6 +792,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -722,6 +810,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -733,6 +824,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart8_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -746,6 +840,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -757,6 +856,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart9_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -770,6 +872,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -783,6 +890,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -794,6 +904,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart10_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -807,6 +920,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -820,6 +938,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -831,6 +952,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart11_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; @@ -1336,6 +1460,9 @@ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QSPI_0>; + interconnect-names = "qspi-config"; status = "disabled"; };