From patchwork Fri Mar 13 16:58:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11437443 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 700871667 for ; Fri, 13 Mar 2020 16:58:57 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 6B636206EB; Fri, 13 Mar 2020 16:58:57 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 15F51206B7; Fri, 13 Mar 2020 16:58:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gWa1uZa2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 15F51206B7 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=thierry.reding@gmail.com Received: by mail-wr1-f47.google.com with SMTP id l18so12960133wru.11; Fri, 13 Mar 2020 09:58:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=SasAQUXkfroYsOYpPXJJCL2Y1hUNoc4M6M8VYYK0keI=; b=gWa1uZa2BFVfX9rodYZOIjCoKFUb9fp5qZkMsAaV4QGa08HvkgVLCO6cBXU1UsJKgN sV/Bdg7GpHYHtaMnNnODPUFgJmZ7Uy8N6PfaMMIRteWIn4HWlwM1oxyw9SCk3ZmlLSP3 am9eD7ZDyTiber1Jf0OSh7XlciTCxnQ8LXNTWVnSC8sJCiB4T0Z7Xm85zygVIgrTM0hw Mfd4KkK0E79rQIFFKNGcNljHjHyTKgjFdJdAEF9kHXSnji1B6T4JY6epYQn0B8nioCs3 gLMSV0bsFlv9ZU+SXcRPbx0ylFCA3dvS8QPz5yeHnu0lfuBk7a8l7YxaF4M2okqLv6HM JKDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=SasAQUXkfroYsOYpPXJJCL2Y1hUNoc4M6M8VYYK0keI=; b=qkZDPCIVUq5jjcpJ22MH2jVaiyvxoy44VOV+AVJO8spv4YxZLcvNyljcUtmF9mc4Bi dIe8ccfAsAgXWlqQHD6F7OKra6jtzrG9h3/P4Zz/vaP2GFcLUkWJ3XiG6hajCE1usgVT ErEYxdK1HSktE6trzg3zEwygUiLYOsH29OF4gu/qjocd6ZQpo+yoGvypNmD6xtzFbOWT 88fgR/McDql+IYWtJDb5J+0OqFguRB+PXudaHJ39pHjBl36SsuTtzE8t19eSXt4qeaN4 /+YV2wgfg2Aai6b+7vDnupItJnFMmVZMeajIDfyer+exQDO1VuOAHIBZ1es4xjWj8VpI gYoA== X-Gm-Message-State: ANhLgQ2pkAcJ1SKt6j5mG1iAbXvOuOhOBObXGO3BYsFY2H9LA/wJvB8S n7H1hRfHoakO11YE+QiVi4ZF9JR+ X-Google-Smtp-Source: ADFU+vucg0CqsQ16ZoemjPuQ4xlKbLeo4LxUNxUVpcATUZFISeJiloFJIyIvK7pkhBWDbxKUy6WPqQ== X-Received: by 2002:a5d:4683:: with SMTP id u3mr19615631wrq.251.1584118735140; Fri, 13 Mar 2020 09:58:55 -0700 (PDT) Received: from localhost (pD9E516A9.dip0.t-ipconnect.de. [217.229.22.169]) by smtp.gmail.com with ESMTPSA id v8sm77801355wrw.2.2020.03.13.09.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:58:54 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 01/10] dt-bindings: Changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:39 +0100 Message-Id: <20200313165848.2915133-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-dt-bindings for you to fetch changes up to eba512375e6bc297c674353841523feba03cf712: dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding (2020-03-13 09:15:11 +0100) Thanks, Thierry ---------------------------------------------------------------- dt-bindings: Changes for v5.7-rc1 New IDs are added for clocks that are controlled by the PMC. This replaces older IDs that were erroneously provided by the clock and reset controller. This also adds device tree bindings for XUSB pad controller support on Tegra194 as well as USB role switching on NVIDIA Tegra SoCs. ---------------------------------------------------------------- JC Kuo (1): dt-bindings: phy: tegra: Add Tegra194 support Nagarjuna Kristam (2): dt-bindings: phy: tegra-xusb: Add usb-role-switch dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding Sowjanya Komatineni (4): dt-bindings: clock: tegra: Add IDs for OSC clocks dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 300 ----------------- .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 354 +++++++++++++++++++++ .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 24 ++ .../devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 190 +++++++++++ include/dt-bindings/clock/tegra114-car.h | 4 +- include/dt-bindings/clock/tegra124-car-common.h | 4 +- include/dt-bindings/clock/tegra210-car.h | 4 +- include/dt-bindings/clock/tegra30-car.h | 4 +- include/dt-bindings/soc/tegra-pmc.h | 16 + 9 files changed, 596 insertions(+), 304 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml create mode 100644 include/dt-bindings/soc/tegra-pmc.h From patchwork Fri Mar 13 16:58:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11437445 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2D954921 for ; Fri, 13 Mar 2020 16:59:00 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 291A320746; Fri, 13 Mar 2020 16:59:00 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BE4DA206B7; Fri, 13 Mar 2020 16:58:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="i2UGQ1SG" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BE4DA206B7 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=thierry.reding@gmail.com Received: by mail-wr1-f67.google.com with SMTP id s14so13020999wrt.8; Fri, 13 Mar 2020 09:58:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4ZtpoizzVl8pdp804KeThlDclE0eGVD9drg6pWo+El0=; b=i2UGQ1SGbp+mel+QVnxrd0VCpoXiF55ypqwakm/eQQbgmGxhx07CJfHqLNHyNIvtoV IV9bqbnyszCY2aR9wMUjjaqxjy9w0gpvOk7k0Qjh3PL6D0jJ2UyX6xHIoQnidbmtL8IO lDa6RNLzenkQeRXCm0XSfRHx5YvUzTTVuHuIkNm+sfijHu9zxlP/DIS8lr8qICoEKwBZ 3e43N1OEC+7MXCQNjXNN0xdKNxzjrh3KVUC9eHdrnB6/fIfyN8k1XxWkm7829IA06t9T rQm7VzFUrwBv6KlJz5kZMXm+iDR9Yiq9YEpVPOVLKisQknGymGbMfwHfgZ38FGeZr3L0 lPhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4ZtpoizzVl8pdp804KeThlDclE0eGVD9drg6pWo+El0=; b=KkcikWkpPZ3jrs56P/mXQlqxBYMqocnk1rx3GPFMnkBiQb49+sc9fiSDkfLtGTfVFi 0hW4Z6SnzidLfajCdYjR56MRe66xYQDdYYXeej7Pu8cgYIp5k0s6yyYg86gZfCdYcJxS xJrZ3ViuXk3sVqLw2G9pwcjlVsc2IxCjGn3X6OXSs2yFDkv96NOiU4/jgqEhGE90jOv3 uCd61zi3ffGe0C3XlQnZRkkw34xdH5DlciWIwk/JS4RXOkvnKjhC3kuJjRHvy+S+dVB6 rPnQThLwmj3NKMDfojEsREAkzuNQNNosiZzCaGWS8Vb1FP+CD7DaI/uHeMnpixzhQEQz EcQw== X-Gm-Message-State: ANhLgQ2zUGw0L7b7WiTT9LFnq4VbV9hTk1fwvzyrHjzXaIeVQR+2PrdF mgVOIm43oiCf6H9ArBU+BfPN8So/ X-Google-Smtp-Source: ADFU+vtsHX4RwxjvrPuT7ImBThVXBi88Xy6BlRSWICD+LYdJ3D0XlIlkc1TQjIoSeYskz83SR9L3Yg== X-Received: by 2002:adf:dec8:: with SMTP id i8mr19317886wrn.326.1584118737923; Fri, 13 Mar 2020 09:58:57 -0700 (PDT) Received: from localhost (pD9E516A9.dip0.t-ipconnect.de. [217.229.22.169]) by smtp.gmail.com with ESMTPSA id t187sm18276952wmt.25.2020.03.13.09.58.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:58:57 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 02/10] firmware: tegra: Changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:40 +0100 Message-Id: <20200313165848.2915133-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313165848.2915133-1-thierry.reding@gmail.com> References: <20200313165848.2915133-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-firmware for you to fetch changes up to 6c2d3a14b7aff13f74fb2331d9a54202c66bea4d: firmware: tegra: Fix a typo in Kconfig (2020-02-17 08:54:09 +0100) Thanks, Thierry ---------------------------------------------------------------- firmware: tegra: Changes for v5.7-rc1 A trivial typofix for the Kconfig entry of the Tegra IVC library. ---------------------------------------------------------------- Christophe JAILLET (1): firmware: tegra: Fix a typo in Kconfig drivers/firmware/tegra/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) From patchwork Fri Mar 13 16:58:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11437447 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A20F11667 for ; Fri, 13 Mar 2020 16:59:02 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 9D5AB206B7; Fri, 13 Mar 2020 16:59:02 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3CF532072C; Fri, 13 Mar 2020 16:59:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="shqhanNg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3CF532072C Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=thierry.reding@gmail.com Received: by mail-wr1-f65.google.com with SMTP id 6so13008220wre.4; Fri, 13 Mar 2020 09:59:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u2Z5UcmV8/VofLHm97f5YbQrhljIP7Kqx9/wdHClbo8=; b=shqhanNgu6CUiTgvC+fvofwKds2aVa+PN19WE7YVRO19OdXXPLw11iLUCyIKLn7itd PiimYJXj2aD8ItxRT9DOHBprZeBQdfSBW6s8Plb2vddcEiKrRCHfXusAKyBQKaz4S72P 8TRl+vcBCuejzM+joA5ukgGmRL4aIvGEdyMlRbw5PAhnyKD/b2NzBG4n+r8xpxcuP/7g a8R++LDuJjMF3+qqeh/433eu5RZfTvv0OrZDxgGRXsiaabzgNgoreU/VTkaRGOB/TFOF RW9G8rOj63kLO1HmNcYCJj2OI88jsNdhyPcHTvzAmi/oGbZdkyykrurwnFRWxknIcujE bcDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u2Z5UcmV8/VofLHm97f5YbQrhljIP7Kqx9/wdHClbo8=; b=FmGfLQoqGtQ+zS+Ud6aLCeo2hGDHcEPoqAgeOCGGQlhibvVvg98iAHpoRxmK6lIbrC QgxZ/zGgeqVELFa/YXrFOJmNqAFi+ptwETmIb7dBF2lrgRJicO84aSQLmaRZ+K+a9fwN rmFFlLiXdLlXF7nDPcOVNpwfyFsV+s365kAAwTYUwcEdHamEOfVCFsAQrwvyKc4hQdHR vL6DSqo4Ghrb1FiMoOjM69vXXYQh5GpYBURZ5z/Gpnt0LhkfeMn9kXBA9Y8VmnhkwNpI tCSEWYT1cynMMrHga+oLWZnb41R0kWv0HSpv+sdANFodKv1tqxDGz78M6sBDLfVlQK1X 0q7g== X-Gm-Message-State: ANhLgQ23LIL4chysxaxUKnvKT6RrmlzwEXj5EY+QcLxNRsPVItltDwNA TxH6MNRXp8iQkvUHFoAQuH/xizdf X-Google-Smtp-Source: ADFU+vuH7CkP7rWK/tMMl7um+/dktR/3uTHUtNvgvBKom1Y+98hD6NSEKua1SljTWsm5xTR7l2vPog== X-Received: by 2002:adf:a555:: with SMTP id j21mr19040106wrb.409.1584118739503; Fri, 13 Mar 2020 09:58:59 -0700 (PDT) Received: from localhost (pD9E516A9.dip0.t-ipconnect.de. [217.229.22.169]) by smtp.gmail.com with ESMTPSA id s28sm4995825wrb.42.2020.03.13.09.58.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:58:58 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 03/10] soc/tegra: Changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:41 +0100 Message-Id: <20200313165848.2915133-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313165848.2915133-1-thierry.reding@gmail.com> References: <20200313165848.2915133-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-soc for you to fetch changes up to 4825f5354ef2e3f6bce61d0ed652a23daf379f8e: soc/tegra: pmc: Cleanup whitespace usage (2020-03-13 10:53:10 +0100) Thanks, Thierry ---------------------------------------------------------------- soc/tegra: Changes for v5.7-rc1 These changes implement various clocks that are controlled by the PMC and add support for configuring the voltage level of some pins (needed for example to support high-speed modes on the SD/MMC interfaces). ---------------------------------------------------------------- JC Kuo (1): dt-bindings: phy: tegra: Add Tegra194 support Nagarjuna Kristam (2): dt-bindings: phy: tegra-xusb: Add usb-role-switch dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding Sowjanya Komatineni (6): dt-bindings: clock: tegra: Add IDs for OSC clocks dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock soc/tegra: Add Tegra PMC clocks registration into PMC driver soc/tegra: Add support for 32 kHz blink clock Thierry Reding (2): Merge branch 'for-5.7/dt-bindings' into for-5.7/soc soc/tegra: pmc: Cleanup whitespace usage Venkat Reddy Talla (1): soc/tegra: pmc: Add pins for Tegra194 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 300 --------- .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 354 +++++++++++ .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 24 + .../devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 190 ++++++ drivers/soc/tegra/pmc.c | 688 ++++++++++++++++----- include/dt-bindings/clock/tegra114-car.h | 4 +- include/dt-bindings/clock/tegra124-car-common.h | 4 +- include/dt-bindings/clock/tegra210-car.h | 4 +- include/dt-bindings/clock/tegra30-car.h | 4 +- include/dt-bindings/soc/tegra-pmc.h | 16 + include/soc/tegra/pmc.h | 3 +- 11 files changed, 1125 insertions(+), 466 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml create mode 100644 include/dt-bindings/soc/tegra-pmc.h From patchwork Fri Mar 13 16:58:42 2020 Content-Type: text/plain; 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[217.229.22.169]) by smtp.gmail.com with ESMTPSA id l7sm9001198wrw.33.2020.03.13.09.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:59:00 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 04/10] memory: tegra: Changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:42 +0100 Message-Id: <20200313165848.2915133-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313165848.2915133-1-thierry.reding@gmail.com> References: <20200313165848.2915133-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-memory for you to fetch changes up to 141267bffd1dc19a76e4d50e3e4829f85a806875: memory: tegra: Correct debugfs clk rate-range on Tegra124 (2020-03-11 15:24:16 +0100) Thanks, Thierry ---------------------------------------------------------------- memory: tegra: Changes for v5.7-rc1 These patches contain fixes for EMC scaling debugfs support on Tegra20, Tegra30 and Tegra124. ---------------------------------------------------------------- Dmitry Osipenko (3): memory: tegra: Correct debugfs clk rate-range on Tegra20 memory: tegra: Correct debugfs clk rate-range on Tegra30 memory: tegra: Correct debugfs clk rate-range on Tegra124 drivers/memory/tegra/tegra124-emc.c | 5 +++++ drivers/memory/tegra/tegra20-emc.c | 5 +++++ drivers/memory/tegra/tegra30-emc.c | 5 +++++ 3 files changed, 15 insertions(+) From patchwork Fri Mar 13 16:58:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11437451 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35508921 for ; Fri, 13 Mar 2020 16:59:06 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 309E02074E; Fri, 13 Mar 2020 16:59:06 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E16E12072C; Fri, 13 Mar 2020 16:59:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aKUCCumZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E16E12072C Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=thierry.reding@gmail.com Received: by mail-wm1-f67.google.com with SMTP id a5so10776149wmb.0; Fri, 13 Mar 2020 09:59:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pl3mvQUZlYeLm1+9mgGrbjOiFn06n8Rmi/zI05KnQ6c=; b=aKUCCumZnOm/aOCa1h+Bu2EL821dLnsht0b922Vfoip5qX6Z5JPEHlIl8ibmvo3/Xx tp8f0d7WGTvmSZC1ztxXf/WWYbpv6CXcgbMIB+ysQWJBv1pJYnx6d3NONoOpkjY8m202 RZx+dZwSdJ8GT+DjnRUYvaL8DJ3vN8A0cXaIzL+kRoJZmsDzIghLoxdFtfGGQHw4m/mz Ncs2X0DymxvJXcELii9hyH+2XIFBhgzlJg4eUVD2FCsbHRtQ8MDlh09UQ3xZLLnhJNqn D3EJXmOjPQ82HO5h7PwdkapiTd7LLLFdHtGkz1o173WSuqIjkvAwVL9zUFp+6ySbhTcx 0e0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pl3mvQUZlYeLm1+9mgGrbjOiFn06n8Rmi/zI05KnQ6c=; b=Jd44WLDJhjGtj6vIB0AgZ0AiH6O/LlVQWs0dOY4GQgIaoQoc1/WWMd379EvdzW3bSf d3Iljbd66TNSflrHwnfcyu85woHCX/hU0DItKAUc/TabLQ2B/qb8ZLjIcnDFHKuO39WH /ZS6o09YnabZBQ2H4Yq/cLzfTkx8tMz2CY3SSDRQa1wWd/7QmR5c0hAVKh3NqIotVRHv 6zr5PMZMQOCab6jGnLnWW45kSH0ieDEUHH1fiPrGH0dhbsenrS6nAUv4wOsSH9w8wDV4 vZ/2pL5KozIRTj3si8BF4zQhIZvrSLbf7/+DEpkr59J8wvlDvaK+au/3qTgBstgv1LD5 Z0sg== X-Gm-Message-State: ANhLgQ1XgwofYZ5WMs3KBwaacqFUd7mqX+rH5aIp+SlO/BX0MEt+gzR/ zOtY6DTiHTp5GKVHUUGZTarrRNih X-Google-Smtp-Source: ADFU+vubdaUjSrckubQn283ZoaceATczfJE+/H8q4lZRJsVazTtdHkVB7euKf6/lnLil+u8FJlutow== X-Received: by 2002:a1c:41d4:: with SMTP id o203mr11378963wma.1.1584118743682; Fri, 13 Mar 2020 09:59:03 -0700 (PDT) Received: from localhost (pD9E516A9.dip0.t-ipconnect.de. [217.229.22.169]) by smtp.gmail.com with ESMTPSA id m11sm33643370wrn.92.2020.03.13.09.59.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:59:02 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 05/10] ARM: tegra: Core changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:43 +0100 Message-Id: <20200313165848.2915133-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313165848.2915133-1-thierry.reding@gmail.com> References: <20200313165848.2915133-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-arm-core for you to fetch changes up to 650a941c341b880dae451e36dd8e47f3762a3909: ARM: tegra: cpuidle: Remove unnecessary memory barrier (2020-03-13 11:23:10 +0100) Thanks, Thierry ---------------------------------------------------------------- ARM: tegra: Core changes for v5.7-rc1 These patches a preparatory work to move the CPU idle drivers into drivers/cpuidle. ---------------------------------------------------------------- Dmitry Osipenko (11): ARM: tegra: Compile sleep-tegra20/30.S unconditionally ARM: tegra: Add tegra_pm_park_secondary_cpu() ARM: tegra: Remove pen-locking from cpuidle-tegra20 ARM: tegra: Change tegra_set_cpu_in_lp2() type to void ARM: tegra: Propagate error from tegra_idle_lp2_last() ARM: tegra: Expose PM functions required for new cpuidle driver ARM: tegra: Rename some of the newly exposed PM functions ARM: tegra: Make outer_disable() open-coded ARM: tegra: cpuidle: Handle case where secondary CPU hangs on entering LP2 ARM: tegra: cpuidle: Make abort_flag atomic ARM: tegra: cpuidle: Remove unnecessary memory barrier arch/arm/mach-tegra/Makefile | 6 +- arch/arm/mach-tegra/cpuidle-tegra114.c | 9 +- arch/arm/mach-tegra/cpuidle-tegra20.c | 111 ++++++++------- arch/arm/mach-tegra/cpuidle-tegra30.c | 27 ++-- arch/arm/mach-tegra/irq.c | 3 +- arch/arm/mach-tegra/pm.c | 54 ++++--- arch/arm/mach-tegra/pm.h | 4 - arch/arm/mach-tegra/reset-handler.S | 11 -- arch/arm/mach-tegra/reset.h | 9 +- arch/arm/mach-tegra/sleep-tegra20.S | 170 ----------------------- arch/arm/mach-tegra/sleep-tegra30.S | 6 +- arch/arm/mach-tegra/sleep.h | 15 -- arch/arm/mach-tegra/tegra.c | 1 - {arch/arm/mach-tegra => include/soc/tegra}/irq.h | 8 +- include/soc/tegra/pm.h | 31 +++++ 15 files changed, 150 insertions(+), 315 deletions(-) rename {arch/arm/mach-tegra => include/soc/tegra}/irq.h (59%) From patchwork Fri Mar 13 16:58:44 2020 Content-Type: text/plain; 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[217.229.22.169]) by smtp.gmail.com with ESMTPSA id s28sm4996272wrb.42.2020.03.13.09.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:59:04 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 06/10] ARM: tegra: Device tree changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:44 +0100 Message-Id: <20200313165848.2915133-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313165848.2915133-1-thierry.reding@gmail.com> References: <20200313165848.2915133-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-arm-dt for you to fetch changes up to bdb2c52a6e564af02b467862097b77941699c698: ARM: tegra: Update sound node clocks in device tree (2020-03-13 11:25:44 +0100) Thanks, Thierry ---------------------------------------------------------------- ARM: tegra: Device tree changes for v5.7-rc1 Minor fixes and additions for 32-bit Tegra SoC device trees. ---------------------------------------------------------------- JC Kuo (1): dt-bindings: phy: tegra: Add Tegra194 support Nagarjuna Kristam (3): dt-bindings: phy: tegra-xusb: Add usb-role-switch dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding ARM: tegra: Remove USB 2-0 port from Jetson TK1 padctl Sowjanya Komatineni (6): dt-bindings: clock: tegra: Add IDs for OSC clocks dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock ARM: tegra: Add clock-cells property to PMC ARM: tegra: Update sound node clocks in device tree Thierry Reding (1): Merge branch 'for-5.7/dt-bindings' into for-5.7/arm/dt .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 300 ----------------- .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 354 +++++++++++++++++++++ .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 24 ++ .../devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 190 +++++++++++ arch/arm/boot/dts/tegra114-dalmore.dts | 8 +- arch/arm/boot/dts/tegra114.dtsi | 4 +- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 8 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 8 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 14 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 8 +- arch/arm/boot/dts/tegra124-venice2.dts | 8 +- arch/arm/boot/dts/tegra124.dtsi | 4 +- arch/arm/boot/dts/tegra20.dtsi | 4 +- arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 8 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 8 +- arch/arm/boot/dts/tegra30-beaver.dts | 8 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 8 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 8 +- arch/arm/boot/dts/tegra30.dtsi | 4 +- include/dt-bindings/clock/tegra114-car.h | 4 +- include/dt-bindings/clock/tegra124-car-common.h | 4 +- include/dt-bindings/clock/tegra210-car.h | 4 +- include/dt-bindings/clock/tegra30-car.h | 4 +- include/dt-bindings/soc/tegra-pmc.h | 16 + 24 files changed, 685 insertions(+), 325 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml create mode 100644 include/dt-bindings/soc/tegra-pmc.h From patchwork Fri Mar 13 16:58:45 2020 Content-Type: text/plain; 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[217.229.22.169]) by smtp.gmail.com with ESMTPSA id y143sm3076390wmd.12.2020.03.13.09.59.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:59:06 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 07/10] ARM: tegra: Default configuration changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:45 +0100 Message-Id: <20200313165848.2915133-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313165848.2915133-1-thierry.reding@gmail.com> References: <20200313165848.2915133-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-arm-defconfig for you to fetch changes up to 224c6632050481885368d5b7f3db56254a34c247: ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig (2020-03-12 11:05:00 +0100) Thanks, Thierry ---------------------------------------------------------------- ARM: tegra: Default configuration changes for v5.7-rc1 These patches enable the new, unified CPU idle driver for Tegra20, Tegra30 and Tegra114. ---------------------------------------------------------------- Dmitry Osipenko (2): ARM: multi_v7_defconfig: Enable Tegra cpuidle driver ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig arch/arm/configs/multi_v7_defconfig | 1 + arch/arm/configs/tegra_defconfig | 1 + 2 files changed, 2 insertions(+) From patchwork Fri Mar 13 16:58:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11437459 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 714F7921 for ; Fri, 13 Mar 2020 16:59:11 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 6D04F206E7; Fri, 13 Mar 2020 16:59:11 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 27260206B7; Fri, 13 Mar 2020 16:59:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hg9jxfVB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 27260206B7 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=thierry.reding@gmail.com Received: by mail-wr1-f42.google.com with SMTP id a25so13039426wrd.0; Fri, 13 Mar 2020 09:59:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y7E/7I3UwnoYO4kboIxPPunVUq6lzAu3iTHHuSklZrw=; b=hg9jxfVBhWx9OFfJIBsDeZGL8xTFUmDYN4ffVvtSmy1Xq/kAZqoWXPIoiTtUgChgee 2qPUhSCrZAtIcbZehU5jH4TZojxHtisu9hS7qVs6LK8c5GOapg7QPRc4NIvTRGPnDIoh u0W6zSGv3De1+qjxPUkABOfvFd/K4JcOnvYnLOpIFmuGKSo+7tsd7l7OdDlHA0upmG8H BDmzlVz5LNlgrNWaI9a/Qg6m2bV54IVUm3U5Ly6GeNDe+djG936PhDqjWnIYaP9u+IsJ 4O3LbRDJVMy5/DvG76ihrEkg1KHIwnuU1PdEgoQXKa3NTkAs1gBdehfWiUwmE4WFC1s7 FadQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y7E/7I3UwnoYO4kboIxPPunVUq6lzAu3iTHHuSklZrw=; b=FR2l78M25Kk2NpLKf55pCZ36ARta379mXnN6cxHmHe7AZ4iwlIrkm3dh1TJeuZDD4s N9Z4tUNTzaMtE17V9bY7Pr0eFplOsd0mCrO/93OiJoXIlTxJOyY3zQX/Rp01RgQXmMI9 9+8FbWuUb1utDRAfw6tCi1KGhLKvqvMyDYvO4kOiNmSGjFDSw4ogi3X9/k5o50O0s0oV TazR1Dw+kgqDCfjJMKBrmuDEUGsMXPaqHTksJhiZWZoqiyYYYBtOMK+sqzCBFjK0A0VB nuvXAszm6AZYqnchYpvjdQ7F2+Ne71N/zvtSit0JiKeIynWzefEW4+kQ3yTxqzjLjWo8 DZIw== X-Gm-Message-State: ANhLgQ19lBiRoixeo3hWgCQq1B5E1ClrjsNri4u+oVOBmbJ4vm2DeiwC NoYBrhjP+Q7s+GbpaXXqwWTc2c9W X-Google-Smtp-Source: ADFU+vssbO4TufJR7WDKRLhsy6jm8DZzzwhkYunqFuhHpdXgYbkPqO4pibw89cfm5vrGAhM2E2R4Sw== X-Received: by 2002:adf:ec88:: with SMTP id z8mr3131265wrn.61.1584118749224; Fri, 13 Mar 2020 09:59:09 -0700 (PDT) Received: from localhost (pD9E516A9.dip0.t-ipconnect.de. [217.229.22.169]) by smtp.gmail.com with ESMTPSA id s13sm28875891wrw.29.2020.03.13.09.59.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:59:08 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 08/10] arm64: tegra: Device tree changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:46 +0100 Message-Id: <20200313165848.2915133-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313165848.2915133-1-thierry.reding@gmail.com> References: <20200313165848.2915133-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-arm64-dt for you to fetch changes up to 84eaaf7500036f292f5563b39a983c492d5b12ae: arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 platform (2020-03-12 12:14:31 +0100) Thanks, Thierry ---------------------------------------------------------------- arm64: tegra: Device tree changes for v5.7-rc1 These changes add support for the XUSB pad controller, as well as the XUSB controller on Tegra194. Furthermore, USB device mode is supported across Tegra210 and Tegra186 boards. PCIe endpoint mode support is added for the Jetson AGX Xavier platform. Various minor fixes eliminate warnings on boot related to missing power supplies for some devices. ---------------------------------------------------------------- JC Kuo (2): arm64: tegra: Add XUSB and pad controller on Tegra194 arm64: tegra: Enable XUSB host in P2972-0000 board Jon Hunter (5): arm64: tegra: Fix Tegra194 PCIe compatible string arm64: tegra: Enable I2C controller for EEPROM arm64: tegra: Add EEPROM supplies arm64: tegra: Fix Tegra186 SOR supply arm64: tegra: Populate LP8557 backlight regulator Nagarjuna Kristam (8): arm64: tegra: Update OTG port entries for Jetson TX1 arm64: tegra: Update OTG port entries for Jetson TX2 arm64: tegra: Add XUDC node for Tegra210 arm64: tegra: Enable XUDC on Jetson TX1 arm64: tegra: Add XUDC node for Tegra186 arm64: tegra: Enable XUDC node on Jetson TX2 arm64: tegra: Update OTG port entries for Jetson Nano arm64: tegra: Enable XUDC node on Jetson Nano Sowjanya Komatineni (6): dt-bindings: clock: tegra: Add IDs for OSC clocks dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock arm64: tegra: Add clock-cells property to Tegra PMC node arm64: tegra: smaug: Change clk_out_2 provider to PMC Thierry Reding (2): Merge branch 'for-5.7/dt-bindings' into for-5.7/arm64/dt arm64: tegra: Add ethernet alias on Jetson TX1 Vidya Sagar (2): arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194 arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 platform .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 300 ----------------- .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 354 +++++++++++++++++++++ .../bindings/pci/nvidia,tegra194-pcie.txt | 2 +- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 26 +- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra186.dtsi | 19 ++ arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 ++- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 81 +++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 250 ++++++++++++++- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 3 + arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 2 + arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 45 ++- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 24 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 25 +- include/dt-bindings/clock/tegra114-car.h | 4 +- include/dt-bindings/clock/tegra124-car-common.h | 4 +- include/dt-bindings/clock/tegra210-car.h | 4 +- include/dt-bindings/clock/tegra30-car.h | 4 +- include/dt-bindings/soc/tegra-pmc.h | 16 + 21 files changed, 883 insertions(+), 323 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml create mode 100644 include/dt-bindings/soc/tegra-pmc.h From patchwork Fri Mar 13 16:58:47 2020 Content-Type: text/plain; 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[217.229.22.169]) by smtp.gmail.com with ESMTPSA id t124sm18104873wmg.13.2020.03.13.09.59.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:59:10 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 09/10] cpuidle: tegra: Changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:47 +0100 Message-Id: <20200313165848.2915133-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313165848.2915133-1-thierry.reding@gmail.com> References: <20200313165848.2915133-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-cpuidle for you to fetch changes up to 382ac8e22b90e6334d373da03c17b319458b258e: cpuidle: tegra: Disable CC6 state if LP2 unavailable (2020-03-13 11:32:01 +0100) This set of changes was acked by Daniel Lezcano and the preference is to take this through the ARM SoC tree because it has a dependency on one of the other branches (tegra-for-5.7-arm-core) that also goes through the ARM SoC tree. Thanks, Thierry ---------------------------------------------------------------- cpuidle: tegra: Changes for v5.7-rc1 These changes unify CPU idle support for Tegra20, Tegra30 and Tegra114. ---------------------------------------------------------------- Dmitry Osipenko (15): ARM: tegra: Compile sleep-tegra20/30.S unconditionally ARM: tegra: Add tegra_pm_park_secondary_cpu() ARM: tegra: Remove pen-locking from cpuidle-tegra20 ARM: tegra: Change tegra_set_cpu_in_lp2() type to void ARM: tegra: Propagate error from tegra_idle_lp2_last() ARM: tegra: Expose PM functions required for new cpuidle driver ARM: tegra: Rename some of the newly exposed PM functions ARM: tegra: Make outer_disable() open-coded ARM: tegra: cpuidle: Handle case where secondary CPU hangs on entering LP2 ARM: tegra: cpuidle: Make abort_flag atomic ARM: tegra: cpuidle: Remove unnecessary memory barrier cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle cpuidle: tegra: Squash Tegra30 driver into the common driver cpuidle: tegra: Squash Tegra114 driver into the common driver cpuidle: tegra: Disable CC6 state if LP2 unavailable Thierry Reding (1): Merge branch 'for-5.7/arm/core' into for-5.7/cpuidle arch/arm/mach-tegra/Makefile | 19 +- arch/arm/mach-tegra/cpuidle-tegra114.c | 89 ----- arch/arm/mach-tegra/cpuidle-tegra20.c | 212 ------------ arch/arm/mach-tegra/cpuidle-tegra30.c | 132 -------- arch/arm/mach-tegra/cpuidle.c | 50 --- arch/arm/mach-tegra/cpuidle.h | 21 -- arch/arm/mach-tegra/irq.c | 3 +- arch/arm/mach-tegra/pm.c | 54 ++-- arch/arm/mach-tegra/pm.h | 4 - arch/arm/mach-tegra/reset-handler.S | 11 - arch/arm/mach-tegra/reset.h | 9 +- arch/arm/mach-tegra/sleep-tegra20.S | 170 ---------- arch/arm/mach-tegra/sleep-tegra30.S | 6 +- arch/arm/mach-tegra/sleep.h | 15 - arch/arm/mach-tegra/tegra.c | 7 +- drivers/cpuidle/Kconfig.arm | 8 + drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-tegra.c | 392 +++++++++++++++++++++++ include/soc/tegra/cpuidle.h | 2 +- {arch/arm/mach-tegra => include/soc/tegra}/irq.h | 8 +- include/soc/tegra/pm.h | 31 ++ 21 files changed, 483 insertions(+), 761 deletions(-) delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra114.c delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra20.c delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra30.c delete mode 100644 arch/arm/mach-tegra/cpuidle.c delete mode 100644 arch/arm/mach-tegra/cpuidle.h create mode 100644 drivers/cpuidle/cpuidle-tegra.c rename {arch/arm/mach-tegra => include/soc/tegra}/irq.h (59%) From patchwork Fri Mar 13 16:58:48 2020 Content-Type: text/plain; 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[217.229.22.169]) by smtp.gmail.com with ESMTPSA id e1sm69648524wrx.90.2020.03.13.09.59.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 09:59:11 -0700 (PDT) From: Thierry Reding List-Id: To: arm@kernel.org, soc@kernel.org Cc: Thierry Reding , Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [GIT PULL 10/10] phy: tegra: Changes for v5.7-rc1 Date: Fri, 13 Mar 2020 17:58:48 +0100 Message-Id: <20200313165848.2915133-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313165848.2915133-1-thierry.reding@gmail.com> References: <20200313165848.2915133-1-thierry.reding@gmail.com> MIME-Version: 1.0 Hi ARM SoC maintainers, The following changes since commit bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9: Linux 5.6-rc1 (2020-02-09 16:08:48 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.7-phy for you to fetch changes up to 04c929223d1db6ad4ba8e4c23122e1052f670c2e: phy: tegra: xusb: Don't warn on probe defer (2020-03-13 09:17:50 +0100) This is a dependency for the USB changes that are also part of this series of pull requests, so it was deemed easier to take this all through the ARM SoC tree. The patches have all been acked by Kishon. Thanks, Thierry ---------------------------------------------------------------- phy: tegra: Changes for v5.7-rc1 This set of patches adds role switching support for the XUSB pad controller, which will be used by USB host and device drivers to switch between peripheral and host modes. ---------------------------------------------------------------- JC Kuo (2): phy: tegra: xusb: Protect Tegra186 soc with config phy: tegra: xusb: Add Tegra194 support Jon Hunter (1): phy: tegra: xusb: Don't warn on probe defer Nagarjuna Kristam (5): phy: tegra: xusb: Add usb-role-switch support phy: tegra: xusb: Add usb-phy support phy: tegra: xusb: Add support to get companion USB 3 port phy: tegra: xusb: Add set_mode support for USB 2 phy on Tegra210 phy: tegra: xusb: Add set_mode support for UTMI phy on Tegra186 drivers/phy/tegra/Kconfig | 1 + drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 261 +++++++++++++++++++++++++++++--------- drivers/phy/tegra/xusb-tegra210.c | 131 +++++++++++++++---- drivers/phy/tegra/xusb.c | 189 +++++++++++++++++++++++++++ drivers/phy/tegra/xusb.h | 10 ++ include/linux/phy/tegra/xusb.h | 2 + 7 files changed, 511 insertions(+), 84 deletions(-)