From patchwork Mon Mar 16 16:06:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440699 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C38114E5 for ; Mon, 16 Mar 2020 16:18:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C3F820719 for ; Mon, 16 Mar 2020 16:18:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="ZyxYnznZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732005AbgCPQSk (ORCPT ); Mon, 16 Mar 2020 12:18:40 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:30854 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731545AbgCPQSj (ORCPT ); Mon, 16 Mar 2020 12:18:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375518; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WUQmK3jX+ITRgjT53gJOYB77qbIWiqXEgYr8J8FbjTA=; b=ZyxYnznZFFpwgBIrvnEqFnHvPDDy5LxYF/LBIMfhNjAATkXGrnZ4BRJXAyeghwRXmliayO yynP63D8i4L4TOXPfQRDZ9tSc5XPA0xfMRn0Q9l0iivXZr5oRRnlTe7P54AGXXrXbeY/FK 7YHRq4LEb4CH/bmfAnxtLEdbt0i3pAQ= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-139-8fK9p7SXPHKMlaIwDbeE-w-1; Mon, 16 Mar 2020 12:06:45 -0400 X-MC-Unique: 8fK9p7SXPHKMlaIwDbeE-w-1 Received: by mail-wr1-f69.google.com with SMTP id w11so9253211wrp.20 for ; Mon, 16 Mar 2020 09:06:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WUQmK3jX+ITRgjT53gJOYB77qbIWiqXEgYr8J8FbjTA=; b=qJN0epzUfboFFZAZdVODeqvnhgFgOcI/6odg5TAL+1+1ueS2a5LlA9ruG6TPXIYFq+ d5qooN85LMszAm+upWjA8Omtd5T7aPm5aItOJ/KmRDWEW6HPBxIs+ExD8WuC1dSBeYEH tmg9lX0jqaIETJcbE7bU5z3Gr8uzqw+u236p6+UkXtFT+59ow90wG/C9YB7Yt2KBAsbN l98uoRnU9YOst1njAG2d5T58wIQ1NimXAAUXvtFM1NM3OL16SRCdSnwFQU9CTeQc1Tnl kEcIVNY2A2S3jMzKFPjKR1cYczWj5wGn2+yD8jXCGEdddzE7Ztr2rr/tG7wX2qUeGwMl Uq0Q== X-Gm-Message-State: ANhLgQ2BlHpf4c0rEkg+dtmwvRu6+QdiRpB0KieQ7tglxuFeAKQOGK0P KPl68p4dow+zXEb+3FwIcN+3zE0HfyRIjzI5/9OZJsPJLA5fw52EiIvj4mEIDwbWEyeGeBfC70S wT0nzXiW9TgtY X-Received: by 2002:a1c:ab04:: with SMTP id u4mr28378905wme.88.1584374803976; Mon, 16 Mar 2020 09:06:43 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtV0XnwGOD9HZ+gDhSELi6gG1sO2wgoMuiEbFWxHuGz29Lw9cyiUjcbAj92lhznjafti4kUQw== X-Received: by 2002:a1c:ab04:: with SMTP id u4mr28378818wme.88.1584374802766; Mon, 16 Mar 2020 09:06:42 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id a10sm480884wrv.89.2020.03.16.09.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:06:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature() Date: Mon, 16 Mar 2020 17:06:16 +0100 Message-Id: <20200316160634.3386-2-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé --- target/arm/kvm32.c | 10 +++++----- target/arm/kvm64.c | 16 ++++++++-------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f271181ab8..0ab28b473a 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -22,7 +22,7 @@ #include "internals.h" #include "qemu/log.h" -static inline void set_feature(uint64_t *features, int feature) +static inline void kvm_set_feature(uint64_t *features, int feature) { *features |= 1ULL << feature; } @@ -146,14 +146,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) * timers; this in turn implies most of the other feature * bits, but a few must be tested. */ - set_feature(&features, ARM_FEATURE_V7VE); - set_feature(&features, ARM_FEATURE_GENERIC_TIMER); + kvm_set_feature(&features, ARM_FEATURE_V7VE); + kvm_set_feature(&features, ARM_FEATURE_GENERIC_TIMER); if (extract32(id_pfr0, 12, 4) == 1) { - set_feature(&features, ARM_FEATURE_THUMB2EE); + kvm_set_feature(&features, ARM_FEATURE_THUMB2EE); } if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) { - set_feature(&features, ARM_FEATURE_NEON); + kvm_set_feature(&features, ARM_FEATURE_NEON); } ahcf->features = features; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index be5b31c2b0..ad33e048e4 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -447,12 +447,12 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) } } -static inline void set_feature(uint64_t *features, int feature) +static inline void kvm_set_feature(uint64_t *features, int feature) { *features |= 1ULL << feature; } -static inline void unset_feature(uint64_t *features, int feature) +static inline void kvm_unset_feature(uint64_t *features, int feature) { *features &= ~(1ULL << feature); } @@ -648,11 +648,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) * with VFPv4+Neon; this in turn implies most of the other * feature bits. */ - set_feature(&features, ARM_FEATURE_V8); - set_feature(&features, ARM_FEATURE_NEON); - set_feature(&features, ARM_FEATURE_AARCH64); - set_feature(&features, ARM_FEATURE_PMU); - set_feature(&features, ARM_FEATURE_GENERIC_TIMER); + kvm_set_feature(&features, ARM_FEATURE_V8); + kvm_set_feature(&features, ARM_FEATURE_NEON); + kvm_set_feature(&features, ARM_FEATURE_AARCH64); + kvm_set_feature(&features, ARM_FEATURE_PMU); + kvm_set_feature(&features, ARM_FEATURE_GENERIC_TIMER); ahcf->features = features; @@ -802,7 +802,7 @@ int kvm_arch_init_vcpu(CPUState *cs) if (cpu->has_pmu) { cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; } else { - unset_feature(&env->features, ARM_FEATURE_PMU); + kvm_unset_feature(&env->features, ARM_FEATURE_PMU); } if (cpu_isar_feature(aa64_sve, cpu)) { assert(kvm_arm_sve_supported(cs)); From patchwork Mon Mar 16 16:06:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440659 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 70A00139A for ; Mon, 16 Mar 2020 16:13:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 47FD72051A for ; Mon, 16 Mar 2020 16:13:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="HAbn5yp9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731948AbgCPQND (ORCPT ); Mon, 16 Mar 2020 12:13:03 -0400 Received: from us-smtp-delivery-74.mimecast.com ([216.205.24.74]:41389 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731545AbgCPQND (ORCPT ); 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b15sm498970wru.70.2020.03.16.09.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:06:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson , Eric Auger Subject: [PATCH v3 02/19] target/arm: Make set_feature() available for other files Date: Mon, 16 Mar 2020 17:06:17 +0100 Message-Id: <20200316160634.3386-3-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Thomas Huth Move the common set_feature() and unset_feature() functions from cpu.c and cpu64.c to internals.h. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Split Thomas's patch in two: set_feature, cpu_register (later)] Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 10 ---------- target/arm/cpu64.c | 11 +---------- 3 files changed, 11 insertions(+), 20 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e633aff36e..7341848e1d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -27,6 +27,16 @@ #include "hw/registerfields.h" +static inline void set_feature(CPUARMState *env, int feature) +{ + env->features |= 1ULL << feature; +} + +static inline void unset_feature(CPUARMState *env, int feature) +{ + env->features &= ~(1ULL << feature); +} + /* register banks for CPU modes */ #define BANK_USRSYS 0 #define BANK_SVC 1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3623ecefbd..c074364542 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -723,16 +723,6 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs) #endif -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |= 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &= ~(1ULL << feature); -} - static int print_insn_thumb1(bfd_vma pc, disassemble_info *info) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 62d36f9e8d..622082eae2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#include "internals.h" #include "qemu/module.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" @@ -29,16 +30,6 @@ #include "kvm_arm.h" #include "qapi/visitor.h" -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |= 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &= ~(1ULL << feature); -} - #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { From patchwork Mon Mar 16 16:06:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440663 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF3A714B4 for ; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b12sm483914wro.66.2020.03.16.09.06.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:06:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel Date: Mon, 16 Mar 2020 17:06:18 +0100 Message-Id: <20200316160634.3386-4-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Under KVM the 'Data or unified Cache line Clean by VA to PoP' instruction will trap. Fixes: 0d57b4999 ("Add support for DC CVAP & DC CVADP ins") Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b61ee73d18..924deffd65 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6777,7 +6777,7 @@ static const ARMCPRegInfo rndr_reginfo[] = { REGINFO_SENTINEL }; -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, uint64_t value) { @@ -6820,9 +6820,9 @@ static const ARMCPRegInfo dcpodp_reg[] = { .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, REGINFO_SENTINEL }; -#endif /*CONFIG_USER_ONLY*/ +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ -#endif +#endif /* TARGET_AARCH64 */ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -7929,7 +7929,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { define_one_arm_cp_reg(cpu, dcpop_reg); @@ -7938,8 +7938,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, dcpodp_reg); } } -#endif /*CONFIG_USER_ONLY*/ -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ +#endif /* TARGET_AARCH64 */ if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); From patchwork Mon Mar 16 16:06:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440669 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3686B14B4 for ; Mon, 16 Mar 2020 16:14:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 171922073E for ; Mon, 16 Mar 2020 16:14:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="PkrV0qAg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732037AbgCPQOD (ORCPT ); Mon, 16 Mar 2020 12:14:03 -0400 Received: from us-smtp-delivery-74.mimecast.com ([216.205.24.74]:52806 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732033AbgCPQOC (ORCPT ); Mon, 16 Mar 2020 12:14:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375241; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x1weIqYNF3Fo5tV0WZvC7V944GYiMwvqowZHCwqs/e8=; b=PkrV0qAgHEoJV2yEPOQdVTFlpiYj/lct5DsrV3fIg6RDJzcPR83rQAJqqFjjdNDK2za7BU bYLdYNQCDLhE+WEYA6kD4WPnptRH0ZoRyjmEp1rtaTk/s5fo5pBgU4G+ZfH3Bt1uEgzujW MeIg+iLD5JC5h8QPHUXUYMfCo3k7RNI= Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-210-3qL5pODGMhC1F98C1trumg-1; Mon, 16 Mar 2020 12:07:00 -0400 X-MC-Unique: 3qL5pODGMhC1F98C1trumg-1 Received: by mail-wm1-f72.google.com with SMTP id f185so1010493wmf.8 for ; Mon, 16 Mar 2020 09:07:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x1weIqYNF3Fo5tV0WZvC7V944GYiMwvqowZHCwqs/e8=; b=XKJyOV0gIbTLDxgxR1AsCDv4rZAPw8BDXtEbO0xVHrB3JZSe8prFQJVtbO0QlEMhC4 R5SfnWBX3963dDkgmgWrvlmpy9ZYi1+IAyGU77bFLE5kJ6noNEZ8f9lsUXvcCac+VwBw oZ8VkCaP7Rq/oprmQ/+9xbWz+/wzCYWQIDLF4XBxWzaq4L02uarsFPh752EWQLi5PWMv T/YTmEF1do4S28UZ547LHSZ7kcgUJvq887WIS/SeuWJbFVky3qf0mRdbZeDKkM35bf2S 9juDyrn+mhujHll20JBAPS9iHRSpTHSZ091ZhPAqjn2H8z8C27rwLE+PSNeOjFtmw0eT QEEg== X-Gm-Message-State: ANhLgQ2kMrMeBywdwKhCXixUWu488RB+Z5vtHnqHBfqYMxV+UzJ6uxPR IfrtdSuzoadXMbmI1TE0s/9w6U+0SRFt1uCnPUYmgo1H1JzGoVfFKyzMlrLzSnbb5KJbDwwZqLm D9MSVTpoqgKu6 X-Received: by 2002:a1c:6385:: with SMTP id x127mr28120924wmb.141.1584374819494; Mon, 16 Mar 2020 09:06:59 -0700 (PDT) X-Google-Smtp-Source: ADFU+vsfX0n8OJNrHnrM7slMemare5ZJPKg4uT9S5KNvko7zVE1qXAD/IK5hEDswewh2HAjGFyl3Zg== X-Received: by 2002:a1c:6385:: with SMTP id x127mr28120897wmb.141.1584374819229; Mon, 16 Mar 2020 09:06:59 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id y5sm166058wmi.34.2020.03.16.09.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:06:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 04/19] target/arm: Restric the Address Translate operations to TCG accel Date: Mon, 16 Mar 2020 17:06:19 +0100 Message-Id: <20200316160634.3386-5-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Under KVM the ATS instruction will trap. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 924deffd65..a5280c091b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3322,7 +3322,7 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) } } -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* get_phys_addr() isn't present for user-mode-only targets */ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3631,7 +3631,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); } -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ static const ARMCPRegInfo vapa_cp_reginfo[] = { { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, @@ -3639,7 +3639,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = { .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), offsetoflow32(CPUARMState, cp15.par_ns) }, .writefn = par_write }, -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* This underdecoding is safe because the reginfo is NO_RAW. */ { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .accessfn = ats_access, @@ -4880,7 +4880,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_alle1is_write }, -#ifndef CONFIG_USER_ONLY + +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* 64 bit address translation operations */ { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, @@ -4929,7 +4930,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .access = PL1_RW, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), .writefn = par_write }, -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ + /* TLB invalidate last level of translation table walk */ { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, @@ -5536,7 +5538,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae2is_write }, -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* Unlike the other EL2-related AT operations, these must * UNDEF from EL3 if EL2 is not implemented, which is why we * define them here rather than with the rest of the AT ops. @@ -6992,7 +6994,7 @@ static const ARMCPRegInfo vhe_reginfo[] = { REGINFO_SENTINEL }; -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static const ARMCPRegInfo ats1e1_reginfo[] = { { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, @@ -7894,14 +7896,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pan, cpu)) { define_one_arm_cp_reg(cpu, &pan_reginfo); } -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) if (cpu_isar_feature(aa64_ats1e1, cpu)) { define_arm_cp_regs(cpu, ats1e1_reginfo); } if (cpu_isar_feature(aa32_ats1e1, cpu)) { define_arm_cp_regs(cpu, ats1cp_reginfo); } -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ if (cpu_isar_feature(aa64_uao, cpu)) { define_one_arm_cp_reg(cpu, &uao_reginfo); } From patchwork Mon Mar 16 16:06:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440685 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B30F013B1 for ; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id 31sm14913edc.26.2020.03.16.09.07.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 05/19] target/arm: Restrict Virtualization Host Extensions instructions to TCG Date: Mon, 16 Mar 2020 17:06:20 +0100 Message-Id: <20200316160634.3386-6-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Under KVM the ARMv8.1-VHE instruction will trap. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a5280c091b..ce6778283d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2897,16 +2897,6 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_VIRT, value); } -static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu = env_archcpu(env); - - trace_arm_gt_cntvoff_write(value); - raw_write(env, ri, value); - gt_recalc_timer(cpu, GTIMER_VIRT); -} - static uint64_t gt_virt_redir_cval_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -2949,6 +2939,17 @@ static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, gt_ctl_write(env, ri, timeridx, value); } +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu = env_archcpu(env); + + trace_arm_gt_cntvoff_write(value); + raw_write(env, ri, value); + gt_recalc_timer(cpu, GTIMER_VIRT); +} + static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { gt_timer_reset(env, ri, GTIMER_HYP); @@ -2976,6 +2977,7 @@ static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, { gt_ctl_write(env, ri, GTIMER_HYP, value); } +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { From patchwork Mon Mar 16 16:06:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440665 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1F90139A for ; Mon, 16 Mar 2020 16:13:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A279920679 for ; Mon, 16 Mar 2020 16:13:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="cnyidcUk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731994AbgCPQNX (ORCPT ); Mon, 16 Mar 2020 12:13:23 -0400 Received: from us-smtp-delivery-74.mimecast.com ([216.205.24.74]:59149 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731991AbgCPQNX (ORCPT ); Mon, 16 Mar 2020 12:13:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375201; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yxNTHu0Y9BXexKmUFsNlCCh8LSzlOCW9yO82fm58I4s=; b=cnyidcUk9ksnMIUa+VWHBwfrkx32BSgWA/5DtgzW3JgfGOo50FwW6y1RlCeg/fxMTZKjTC hSRWLU3ksO749F/Tc6R1pt0rlvnBzYthEL1MnZuEgM2XIw8HgwvcJ/m8AeVkCuN/R0nD49 LVkHDmiOHkHzCOmrdXecIHSehU8Y18E= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-403-6rI3XHHhMHKLi5nWOkpE2g-1; Mon, 16 Mar 2020 12:07:11 -0400 X-MC-Unique: 6rI3XHHhMHKLi5nWOkpE2g-1 Received: by mail-wr1-f69.google.com with SMTP id 94so4576704wrr.3 for ; Mon, 16 Mar 2020 09:07:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yxNTHu0Y9BXexKmUFsNlCCh8LSzlOCW9yO82fm58I4s=; b=mMjkJT/DPXw+hSOQgSHd27S7Bh3fPpJ+HRccfMozEUhndfP2DiTas4xFlFrBZqSTu1 CkGy06OE1SYWuzIsUtOvcizU5iG/IIcvSB9EQTmOzraCdhXYRyE4oTDd3fgrmQu5UgpR Oy1COjyszQaNwP+13TpowTUzTkQhoG7VgvhbWZqdm8UPYarhlofX0PCpIaa0EHLuyyWC ZFjML5+5Z5n2+Fz8YyLcKe1crMdHE/PpWooY7zk4B0T0ToqYHurjUZZBui/pwL+qnAJt hFN3I4EIQ9J8W3Nh+IpYTLbFFQRnTo2qbgPpqwdx79uiTWN5k5v0AZbjQRQtCfcc9c42 vs4w== X-Gm-Message-State: ANhLgQ1AZsADC/+M25HN7hndO0yEK+JpeJMrwN8YhbVLA6/88+Y+9BeA 9C/542MSY93YyzL1ipsBAPcblUNbh5xkL1PqMX28d3gHRznL/b/V65zGbIP1/PZ4yP95GSg9gRD G9/WOhocB1RvI X-Received: by 2002:a7b:c5cd:: with SMTP id n13mr28456586wmk.172.1584374830944; Mon, 16 Mar 2020 09:07:10 -0700 (PDT) X-Google-Smtp-Source: ADFU+vs7IJfPb/lnQB6VsT1fXs4khiy3iYFUFjrhDCacWI//Wr03P/OMBnlYg0XoQf+8TAXToOGQKQ== X-Received: by 2002:a7b:c5cd:: with SMTP id n13mr28456569wmk.172.1584374830787; Mon, 16 Mar 2020 09:07:10 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id p8sm552349wrw.19.2020.03.16.09.07.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 06/19] target/arm: Move Makefile variable restricted to CONFIG_TCG Date: Mon, 16 Mar 2020 17:06:21 +0100 Message-Id: <20200316160634.3386-7-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Simple code movement which simplifies next commits. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/Makefile.objs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index cf26c16f5f..0c6f8c248d 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -1,4 +1,3 @@ -obj-$(CONFIG_TCG) += arm-semi.o obj-y += helper.o vfp_helper.o obj-y += cpu.o gdbstub.o obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o @@ -56,6 +55,12 @@ target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-t32.inc.c target/arm/translate.o: target/arm/decode-t16.inc.c +ifeq ($(CONFIG_TCG),y) + +obj-y += arm-semi.o + +endif # CONFIG_TCG + obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o obj-y += crypto_helper.o From patchwork Mon Mar 16 16:06:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440691 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6A0E717E6 for ; Mon, 16 Mar 2020 16:16:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4B55F20679 for ; Mon, 16 Mar 2020 16:16:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Y8pcIBYP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732072AbgCPQQD (ORCPT ); Mon, 16 Mar 2020 12:16:03 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:55988 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731924AbgCPQQD (ORCPT ); Mon, 16 Mar 2020 12:16:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375362; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r1sJ64QkUjojSCH6EGfhYUMESaCKLhSIpdoia+8OdJA=; b=Y8pcIBYPiaPQvfm82U6HsC+KWv9Gn+86vVgo1gU/djhRobrRxjSVluTXkj9baINRW+A1Z6 mT4BLFHBeKIGwXr4SoI1knS/m+tY85Q9BvZG1mRZ7WfTkvyAhkQh3WpjMIfSg3wbxHFfWg MTslW17MH0rDk7cIkt4YKbswzmxWhrc= Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-366-ltVIQjEtMFyN7mIPM5wqgw-1; Mon, 16 Mar 2020 12:07:39 -0400 X-MC-Unique: ltVIQjEtMFyN7mIPM5wqgw-1 Received: by mail-wr1-f70.google.com with SMTP id b11so9233295wru.21 for ; Mon, 16 Mar 2020 09:07:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r1sJ64QkUjojSCH6EGfhYUMESaCKLhSIpdoia+8OdJA=; b=rcXqeXjG+shZqgxwTvS4vFOTINBr2EBdYNXALZzHEcbV5NJEMVY9gOyQSyl5rAbpvx JRfZXvc7WBFDpniNiTx7wtzFap2RMbZSyt+ifZ7OjkQygJ7D78cannnjQSRfpYa/X5wp UsM8opOmwlSh8IVPIy1NAdQA7CfzBcrKPWP+6MAQduzqyEFrj3jSudYqfeF5/4yNl9Yi LNQATr+6egu2dMLF1XiCI1LLCqNR3P2k/QrWyW7nxf+uTyj1gQvlQX/hKOnOTjKDgeoc jDS0Dnts1uflaXFtSsCpnKaC9B/V9bTwmGvJiEijrqgvp1Wd3px3bIpdCcQxaDkLYxjS 4LWA== X-Gm-Message-State: ANhLgQ0BRtdXeI7nKt06qw7Xp6fVPlYzXokuDHd+iy3dkQBfI2sE9qdI NCylOVcKbyX6+hZGPjpmlGZq3pvsUEsae1UhewqOAMiACkVQjSbWBw5bqIz7WXHVVn6qjh2AGLv Mg1KM+aqIDIKM X-Received: by 2002:a05:6000:d0:: with SMTP id q16mr77275wrx.71.1584374836479; Mon, 16 Mar 2020 09:07:16 -0700 (PDT) X-Google-Smtp-Source: ADFU+vuudPESzx7lkwiv+yf4OA/xliD4IQtL8C5kEgXeePSGNU/JOytk/Z7I5CpK3n1RCITbf/5TOg== X-Received: by 2002:a05:6000:d0:: with SMTP id q16mr77257wrx.71.1584374836307; Mon, 16 Mar 2020 09:07:16 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id y7sm22973551wmd.1.2020.03.16.09.07.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson , Eric Auger Subject: [PATCH v3 07/19] target/arm: Make cpu_register() available for other files Date: Mon, 16 Mar 2020 17:06:22 +0100 Message-Id: <20200316160634.3386-8-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Thomas Huth Make cpu_register() (renamed to arm_cpu_register()) available from internals.h so we can register CPUs also from other files in the future. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Split Thomas's patch in two: set_feature (earlier), cpu_register] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu-qom.h | 9 ++++++++- target/arm/cpu.c | 10 ++-------- target/arm/cpu64.c | 8 +------- 3 files changed, 11 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 3a9d31ea9d..29c5e2f2c9 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,7 +35,14 @@ struct arm_boot_info; #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU -typedef struct ARMCPUInfo ARMCPUInfo; +typedef struct ARMCPUInfo { + const char *name; + void (*initfn)(Object *obj); + void (*class_init)(ObjectClass *oc, void *data); +} ARMCPUInfo; + +void arm_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_register(const ARMCPUInfo *info); /** * ARMCPUClass: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c074364542..d2813eb81a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2698,12 +2698,6 @@ static void arm_max_initfn(Object *obj) #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo arm_cpus[] = { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) { .name = "arm926", .initfn = arm926_initfn }, @@ -2869,7 +2863,7 @@ static void cpu_register_class_init(ObjectClass *oc, void *data) acc->info = data; } -static void cpu_register(const ARMCPUInfo *info) +void arm_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info = { .parent = TYPE_ARM_CPU, @@ -2910,7 +2904,7 @@ static void arm_cpu_register_types(void) type_register_static(&idau_interface_type_info); while (info->name) { - cpu_register(info); + arm_cpu_register(info); info++; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 622082eae2..e89388378b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -728,12 +728,6 @@ static void aarch64_max_initfn(Object *obj) cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal); } -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, @@ -816,7 +810,7 @@ static void cpu_register_class_init(ObjectClass *oc, void *data) acc->info = data; } -static void aarch64_cpu_register(const ARMCPUInfo *info) +void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info = { .parent = TYPE_AARCH64_CPU, From patchwork Mon Mar 16 16:06:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440667 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0195A13B1 for ; Mon, 16 Mar 2020 16:14:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D617920719 for ; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id u204sm185104wmg.40.2020.03.16.09.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 08/19] target/arm: Add semihosting stub to allow building without TCG Date: Mon, 16 Mar 2020 17:06:23 +0100 Message-Id: <20200316160634.3386-9-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Semihosting requires TCG. When configured with --disable-tcg, the build fails because the 'do_arm_semihosting' is missing. Instead of adding more few more #ifdeffery to the helper code, add a stub. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/arm-semi-stub.c | 13 +++++++++++++ target/arm/Makefile.objs | 3 ++- 2 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 target/arm/arm-semi-stub.c diff --git a/target/arm/arm-semi-stub.c b/target/arm/arm-semi-stub.c new file mode 100644 index 0000000000..47d042f942 --- /dev/null +++ b/target/arm/arm-semi-stub.c @@ -0,0 +1,13 @@ +/* + * Arm "Angel" semihosting syscalls stubs + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "hw/semihosting/semihost.h" + +target_ulong do_arm_semihosting(CPUARMState *env) +{ + abort(); +} diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 0c6f8c248d..fa278bb4c1 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -57,7 +57,8 @@ target/arm/translate.o: target/arm/decode-t16.inc.c ifeq ($(CONFIG_TCG),y) -obj-y += arm-semi.o +obj-$(CONFIG_SEMIHOSTING) += arm-semi.o +obj-$(call lnot,$(CONFIG_SEMIHOSTING)) += arm-semi-stub.o endif # CONFIG_TCG From patchwork Mon Mar 16 16:06:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440695 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 459B81668 for ; Mon, 16 Mar 2020 16:18:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 262A420663 for ; Mon, 16 Mar 2020 16:18:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="TFnLWEK2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732024AbgCPQSk (ORCPT ); Mon, 16 Mar 2020 12:18:40 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:47625 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731674AbgCPQSj (ORCPT ); Mon, 16 Mar 2020 12:18:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375518; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZbHLr8MN7Y181YkXNU9q35GGyibM63M9cMs0mFzNFC4=; b=TFnLWEK2AyH8pyhInKP2lXJpOBPjjjtAchbkUOq9493fZNnnTnuPG6pmNi26LtvvpoCEF7 +jINnITt0reGLAq1OIwbQlhnqdvptQVcPL+EmRkhvn098LibAj+WJVVGJD30VUaUZqPo0v CmUfA1rjaV6yUsthH+nkR48crrAyT0M= Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-173-US0_RaMUM4K3Ip0mzlr96g-1; Mon, 16 Mar 2020 12:07:28 -0400 X-MC-Unique: US0_RaMUM4K3Ip0mzlr96g-1 Received: by mail-wm1-f70.google.com with SMTP id p4so5070418wmp.0 for ; Mon, 16 Mar 2020 09:07:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZbHLr8MN7Y181YkXNU9q35GGyibM63M9cMs0mFzNFC4=; b=hs8CnZgWppLuBUEi/4MWT6x/l6hyDwDQB6rylNivmyi3ZE147y/3G66mhOOtJ6eSho NY5IH0tl9Wnug6jG/rF2p9m6UHH4XkEOHyZC98vA3c3lWhV0STlsckEMLTR6WG2Q66Q3 IjQ6FgPJNpG1oVRjABzf4vXiOFrXWNtzdYNAza1qe96AbzMZkkB3SnlegUbnd8oa8Kh9 PgduF3H1Qr7NCMuF+Ng7iAI+eZXD/NhI6PqvGyujnBN3sa4atni4hmrACwVDifK4CABf TMhGcT2jthRjP8pxXFgfApUdw22C5dqBs7DvZhepWl67MnXcAXkQpH7VjkBqr+2RkNK0 elBg== X-Gm-Message-State: ANhLgQ0WrwstUiXtbx7KsFxSYLbswaQqj1iO8cMoBW+rNZ7Nxv1dIo5Z 0/Yf9oM014d/fX7BRqm5lQmpOO4unsPyEEhb0QszccgvSbAAhSEg8u2uA3gwUKf8aSefYJvC3eH 0Ah5gBE9FmKVa X-Received: by 2002:a1c:de82:: with SMTP id v124mr27908591wmg.70.1584374847177; Mon, 16 Mar 2020 09:07:27 -0700 (PDT) X-Google-Smtp-Source: ADFU+vvmhZSbs8NzLKXqUjgdCfW3w9WctLHdMyXVqEBO9jZ0UEFAr0Le+jcnqG4RZo4FMyA5CMMs0Q== X-Received: by 2002:a1c:de82:: with SMTP id v124mr27908565wmg.70.1584374846997; Mon, 16 Mar 2020 09:07:26 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id k5sm221948wmj.18.2020.03.16.09.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 09/19] target/arm: Move ARM_V7M Kconfig from hw/ to target/ Date: Mon, 16 Mar 2020 17:06:24 +0100 Message-Id: <20200316160634.3386-10-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org ARM_V7M is a concept tied to the architecture. Move it to the target/arm/ directory to keep the hardware/architecture separation clearer. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson --- hw/arm/Kconfig | 3 --- target/Kconfig | 2 +- target/arm/Kconfig | 2 ++ 3 files changed, 3 insertions(+), 4 deletions(-) create mode 100644 target/arm/Kconfig diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e5a876c8d1..e3d7e7694a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -285,9 +285,6 @@ config ZYNQ select XILINX_SPIPS select ZYNQ_DEVCFG -config ARM_V7M - bool - config ALLWINNER_A10 bool select AHCI diff --git a/target/Kconfig b/target/Kconfig index 8b13789179..130d0c7a85 100644 --- a/target/Kconfig +++ b/target/Kconfig @@ -1 +1 @@ - +source arm/Kconfig diff --git a/target/arm/Kconfig b/target/arm/Kconfig new file mode 100644 index 0000000000..e68c71a6ff --- /dev/null +++ b/target/arm/Kconfig @@ -0,0 +1,2 @@ +config ARM_V7M + bool From patchwork Mon Mar 16 16:06:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440671 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C11CE139A for ; Mon, 16 Mar 2020 16:14:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 968DB20736 for ; Mon, 16 Mar 2020 16:14:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="gY+hYduq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732050AbgCPQOF (ORCPT ); Mon, 16 Mar 2020 12:14:05 -0400 Received: from us-smtp-delivery-74.mimecast.com ([216.205.24.74]:23938 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732033AbgCPQOF (ORCPT ); Mon, 16 Mar 2020 12:14:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375243; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3HJ4BPrTTJoaZ0DIQ+Bm5OwC5QHXxR7lFDDNNHr42oA=; b=gY+hYduqDlhAL41eu4tcw2ZNookRJyIf+JQrgbwSbe6fyBiA5+p5wAfZDky5kvPQYUkcCn 9A1kXLH5zI+v7PZJdIU39fi8kGoFvcXfMWwthd/bvLcCvmQ17/Fnmc7qXYggmneRLrANqP yb3z+TCZjXSbO7EWEZAQ6i3cTpg766k= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-400-rmNVSgqBOqu8mMusX0_9Tg-1; Mon, 16 Mar 2020 12:07:35 -0400 X-MC-Unique: rmNVSgqBOqu8mMusX0_9Tg-1 Received: by mail-wr1-f69.google.com with SMTP id b12so9325985wro.4 for ; Mon, 16 Mar 2020 09:07:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3HJ4BPrTTJoaZ0DIQ+Bm5OwC5QHXxR7lFDDNNHr42oA=; b=qKGr5XhJJNbN7z1GKsp4OstByVmCUIXEsbC93m8ro0wjQSJhLnaPVa0SeU4BOS55nT sTRIsHIW2bdVyCKiinsLD7HTyb2Au7AytVP3cEwxyTmBQ1WonAj9xKYWWkr0QfQAgOjo 6TgwBT6NNdlDXjB8GP7k5pRDZt1ruPFcSP1uTk9vU+DQJ9GoG9fVk5bWBg6Jzt0Eqbfo dXVrDW0YlNossgQJjffvqhFs8IAccmlBYvXP4tbznt7i4nofCIV7w6wg0PSU5jRFuQtD yd5Dei2qfqOQnkzXHviMZgs6h8Uxr+UhCdAS9VeWsps0Oh+HS3x5F0osMd/mJ8+WQZ4o p7nA== X-Gm-Message-State: ANhLgQ2EHPbpFQC62ha2Yw0x5azvryZVrqC0NAWhMJstXea2VTYlfHuT 5WSuiegdHH8ja10VcnK2NgUysuc9HqQbiK6NA9tkmT8ed3omBlTiyspg+3k6Rn7W1clgCpMMEvg z2Yyt70TXq+N+ X-Received: by 2002:a5d:69c1:: with SMTP id s1mr47284wrw.351.1584374852710; Mon, 16 Mar 2020 09:07:32 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtrKaxBzOd8Im5SmvT1u80g+l61wwRhiOvBIE54mUu/WaIr9u73VUZDQPx9shnTaY32+aclQQ== X-Received: by 2002:a5d:69c1:: with SMTP id s1mr47263wrw.351.1584374852435; Mon, 16 Mar 2020 09:07:32 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id 127sm68345wmd.38.2020.03.16.09.07.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:25 +0100 Message-Id: <20200316160634.3386-11-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv4 CPUs when TCG is available: - StrongARM (SA1100/1110) - OMAP1510 (TI925T) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 2 - target/arm/cpu.c | 33 ----------------- target/arm/cpu_v4.c | 65 +++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 2 + target/arm/Kconfig | 4 ++ target/arm/Makefile.objs | 2 + 6 files changed, 73 insertions(+), 35 deletions(-) create mode 100644 target/arm/cpu_v4.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 8b89d8c4c0..0652396296 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -17,8 +17,6 @@ CONFIG_INTEGRATOR=y CONFIG_FSL_IMX31=y CONFIG_MUSICPAL=y CONFIG_MUSCA=y -CONFIG_CHEETAH=y -CONFIG_SX1=y CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2813eb81a..b08b6933be 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2459,36 +2459,6 @@ static void cortex_a15_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } -static void ti925t_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V4T); - set_feature(&cpu->env, ARM_FEATURE_OMAPCP); - cpu->midr = ARM_CPUID_TI925T; - cpu->ctr = 0x5109149; - cpu->reset_sctlr = 0x00000070; -} - -static void sa1100_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "intel,sa1100"; - set_feature(&cpu->env, ARM_FEATURE_STRONGARM); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr = 0x4401A11B; - cpu->reset_sctlr = 0x00000070; -} - -static void sa1110_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_STRONGARM); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr = 0x6901B119; - cpu->reset_sctlr = 0x00000070; -} - static void pxa250_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -2727,9 +2697,6 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn }, - { .name = "ti925t", .initfn = ti925t_initfn }, - { .name = "sa1100", .initfn = sa1100_initfn }, - { .name = "sa1110", .initfn = sa1110_initfn }, { .name = "pxa250", .initfn = pxa250_initfn }, { .name = "pxa255", .initfn = pxa255_initfn }, { .name = "pxa260", .initfn = pxa260_initfn }, diff --git a/target/arm/cpu_v4.c b/target/arm/cpu_v4.c new file mode 100644 index 0000000000..1de00a03ee --- /dev/null +++ b/target/arm/cpu_v4.c @@ -0,0 +1,65 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static void ti925t_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V4T); + set_feature(&cpu->env, ARM_FEATURE_OMAPCP); + cpu->midr = ARM_CPUID_TI925T; + cpu->ctr = 0x5109149; + cpu->reset_sctlr = 0x00000070; +} + +static void sa1100_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "intel,sa1100"; + set_feature(&cpu->env, ARM_FEATURE_STRONGARM); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr = 0x4401A11B; + cpu->reset_sctlr = 0x00000070; +} + +static void sa1110_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_STRONGARM); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr = 0x6901B119; + cpu->reset_sctlr = 0x00000070; +} + +static const ARMCPUInfo arm_v4_cpus[] = { + { .name = "ti925t", .initfn = ti925t_initfn }, + { .name = "sa1100", .initfn = sa1100_initfn }, + { .name = "sa1110", .initfn = sa1110_initfn }, + { .name = NULL } +}; + +static void arm_v4_cpu_register_types(void) +{ + const ARMCPUInfo *info = arm_v4_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v4_cpu_register_types) + +#endif diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e3d7e7694a..7fc0cff776 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -28,6 +28,7 @@ config ARM_VIRT config CHEETAH bool + select ARM_V4 select OMAP select TSC210X @@ -242,6 +243,7 @@ config COLLIE config SX1 bool + select ARM_V4 select OMAP config VERSATILE diff --git a/target/arm/Kconfig b/target/arm/Kconfig index e68c71a6ff..0d496d318a 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -1,2 +1,6 @@ +config ARM_V4 + depends on TCG + bool + config ARM_V7M bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index fa278bb4c1..bc0f63ebbc 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -68,6 +68,8 @@ obj-y += crypto_helper.o obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o obj-y += m_helper.o +obj-$(CONFIG_ARM_V4) += cpu_v4.o + obj-$(CONFIG_SOFTMMU) += psci.o obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o From patchwork Mon Mar 16 16:06:26 2020 Content-Type: text/plain; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id w204sm241548wma.1.2020.03.16.09.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 11/19] target/arm: Restrict ARMv5 cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:26 +0100 Message-Id: <20200316160634.3386-12-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv5 CPUs when TCG is available: - ARM926 - ARM946 - ARM1026 - XScale (PXA250/255/260/261/262/270) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 12 -- target/arm/cpu.c | 234 ---------------------------- target/arm/cpu_v5.c | 266 ++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 7 + target/arm/Kconfig | 4 + target/arm/Makefile.objs | 1 + 6 files changed, 278 insertions(+), 246 deletions(-) create mode 100644 target/arm/cpu_v5.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 0652396296..f176a98296 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -13,32 +13,20 @@ CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_HIGHBANK=y -CONFIG_INTEGRATOR=y CONFIG_FSL_IMX31=y -CONFIG_MUSICPAL=y CONFIG_MUSCA=y CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y -CONFIG_VERSATILE=y CONFIG_VEXPRESS=y CONFIG_ZYNQ=y -CONFIG_MAINSTONE=y -CONFIG_GUMSTIX=y -CONFIG_SPITZ=y -CONFIG_TOSA=y -CONFIG_Z2=y -CONFIG_COLLIE=y -CONFIG_ASPEED_SOC=y CONFIG_NETDUINO2=y CONFIG_NETDUINOPLUS2=y CONFIG_MPS2=y CONFIG_RASPI=y -CONFIG_DIGIC=y CONFIG_SABRELITE=y CONFIG_EMCRAFT_SF2=y CONFIG_MICROBIT=y -CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_ALLWINNER_H3=y diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b08b6933be..f1d1ba8451 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1834,86 +1834,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -static void arm926_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,arm926"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - cpu->midr = 0x41069265; - cpu->reset_fpsid = 0x41011090; - cpu->ctr = 0x1dd20d2; - cpu->reset_sctlr = 0x00090078; - - /* - * ARMv5 does not have the ID_ISAR registers, but we can still - * set the field to indicate Jazelle support within QEMU. - */ - cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); - /* - * Similarly, we need to set MVFR0 fields to enable vfp and short vector - * support even though ARMv5 doesn't have this register. - */ - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); -} - -static void arm946_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,arm946"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_PMSA); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr = 0x41059461; - cpu->ctr = 0x0f004006; - cpu->reset_sctlr = 0x00000078; -} - -static void arm1026_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,arm1026"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_AUXCR); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - cpu->midr = 0x4106a262; - cpu->reset_fpsid = 0x410110a0; - cpu->ctr = 0x1dd20d2; - cpu->reset_sctlr = 0x00090078; - cpu->reset_auxcr = 1; - - /* - * ARMv5 does not have the ID_ISAR registers, but we can still - * set the field to indicate Jazelle support within QEMU. - */ - cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); - /* - * Similarly, we need to set MVFR0 fields to enable vfp and short vector - * support even though ARMv5 doesn't have this register. - */ - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); - - { - /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ - ARMCPRegInfo ifar = { - .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, - .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), - .resetvalue = 0 - }; - define_one_arm_cp_reg(cpu, &ifar); - } -} - static void arm1136_r2_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -2459,144 +2379,6 @@ static void cortex_a15_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } -static void pxa250_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr = 0x69052100; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa255_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr = 0x69052d00; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa260_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr = 0x69052903; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa261_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr = 0x69052d05; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa262_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr = 0x69052d06; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa270a0_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr = 0x69054110; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa270a1_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr = 0x69054111; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa270b0_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr = 0x69054112; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa270b1_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr = 0x69054113; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa270c0_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr = 0x69054114; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - -static void pxa270c5_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr = 0x69054117; - cpu->ctr = 0xd172172; - cpu->reset_sctlr = 0x00000078; -} - #ifndef TARGET_AARCH64 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. @@ -2670,9 +2452,6 @@ static void arm_max_initfn(Object *obj) static const ARMCPUInfo arm_cpus[] = { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - { .name = "arm926", .initfn = arm926_initfn }, - { .name = "arm946", .initfn = arm946_initfn }, - { .name = "arm1026", .initfn = arm1026_initfn }, /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an * older core than plain "arm1136". In particular this does not * have the v6K features. @@ -2697,19 +2476,6 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn }, - { .name = "pxa250", .initfn = pxa250_initfn }, - { .name = "pxa255", .initfn = pxa255_initfn }, - { .name = "pxa260", .initfn = pxa260_initfn }, - { .name = "pxa261", .initfn = pxa261_initfn }, - { .name = "pxa262", .initfn = pxa262_initfn }, - /* "pxa270" is an alias for "pxa270-a0" */ - { .name = "pxa270", .initfn = pxa270a0_initfn }, - { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, - { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, - { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, - { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, - { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, - { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, #ifndef TARGET_AARCH64 { .name = "max", .initfn = arm_max_initfn }, #endif diff --git a/target/arm/cpu_v5.c b/target/arm/cpu_v5.c new file mode 100644 index 0000000000..7a231ef649 --- /dev/null +++ b/target/arm/cpu_v5.c @@ -0,0 +1,266 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static void arm926_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,arm926"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); + cpu->midr = 0x41069265; + cpu->reset_fpsid = 0x41011090; + cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00090078; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); + /* + * Similarly, we need to set MVFR0 fields to enable vfp and short vector + * support even though ARMv5 doesn't have this register. + */ + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); +} + +static void arm946_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,arm946"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr = 0x41059461; + cpu->ctr = 0x0f004006; + cpu->reset_sctlr = 0x00000078; +} + +static void arm1026_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,arm1026"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_AUXCR); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); + cpu->midr = 0x4106a262; + cpu->reset_fpsid = 0x410110a0; + cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00090078; + cpu->reset_auxcr = 1; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); + /* + * Similarly, we need to set MVFR0 fields to enable vfp and short vector + * support even though ARMv5 doesn't have this register. + */ + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); + + { + /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ + ARMCPRegInfo ifar = { + .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), + .resetvalue = 0 + }; + define_one_arm_cp_reg(cpu, &ifar); + } +} + +static void pxa250_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr = 0x69052100; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa255_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr = 0x69052d00; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa260_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr = 0x69052903; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa261_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr = 0x69052d05; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa262_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr = 0x69052d06; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa270a0_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr = 0x69054110; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa270a1_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr = 0x69054111; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa270b0_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr = 0x69054112; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa270b1_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr = 0x69054113; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa270c0_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr = 0x69054114; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static void pxa270c5_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr = 0x69054117; + cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; +} + +static const ARMCPUInfo arm_v5_cpus[] = { + { .name = "arm926", .initfn = arm926_initfn }, + { .name = "arm946", .initfn = arm946_initfn }, + { .name = "arm1026", .initfn = arm1026_initfn }, + { .name = "pxa250", .initfn = pxa250_initfn }, + { .name = "pxa255", .initfn = pxa255_initfn }, + { .name = "pxa260", .initfn = pxa260_initfn }, + { .name = "pxa261", .initfn = pxa261_initfn }, + { .name = "pxa262", .initfn = pxa262_initfn }, + /* "pxa270" is an alias for "pxa270-a0" */ + { .name = "pxa270", .initfn = pxa270a0_initfn }, + { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, + { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, + { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, + { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, + { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, + { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, + { .name = NULL } +}; + +static void arm_v5_cpu_register_types(void) +{ + const ARMCPUInfo *info = arm_v5_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v5_cpu_register_types) + +#endif diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7fc0cff776..3b78471de0 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -38,6 +38,7 @@ config CUBIEBOARD config DIGIC bool + select ARM_V5 select PTIMER select PFLASH_CFI02 @@ -67,6 +68,7 @@ config HIGHBANK config INTEGRATOR bool + select ARM_V5 select ARM_TIMER select INTEGRATOR_DEBUG select PL011 # UART @@ -93,6 +95,7 @@ config MUSCA config MUSICPAL bool + select ARM_V5 select BITBANG_I2C select MARVELL_88W8618 select PTIMER @@ -132,6 +135,7 @@ config OMAP config PXA2XX bool + select ARM_V5 select FRAMEBUFFER select I2C select SERIAL @@ -248,6 +252,7 @@ config SX1 config VERSATILE bool + select ARM_V5 select ARM_TIMER # sp804 select PFLASH_CFI01 select LSI_SCSI_PCI @@ -354,6 +359,7 @@ config XLNX_VERSAL config FSL_IMX25 bool + select ARM_V5 select IMX select IMX_FEC select IMX_I2C @@ -376,6 +382,7 @@ config FSL_IMX6 config ASPEED_SOC bool + select ARM_V5 select DS1338 select FTGMAC100 select I2C diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 0d496d318a..028d8382fe 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -2,5 +2,9 @@ config ARM_V4 depends on TCG bool +config ARM_V5 + depends on TCG + bool + config ARM_V7M bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index bc0f63ebbc..f66f7f1158 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -69,6 +69,7 @@ obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o obj-y += m_helper.o obj-$(CONFIG_ARM_V4) += cpu_v4.o +obj-$(CONFIG_ARM_V5) += cpu_v5.o obj-$(CONFIG_SOFTMMU) += psci.o From patchwork Mon Mar 16 16:06:27 2020 Content-Type: text/plain; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id 96sm549814wrm.63.2020.03.16.09.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 12/19] target/arm: Restrict ARMv6 cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:27 +0100 Message-Id: <20200316160634.3386-13-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv6 CPUs when TCG is available: - ARM1136 - ARM1176 - ARM11MPCore - Cortex-M0 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 2 - target/arm/cpu.c | 137 ------------------------- target/arm/cpu_v6.c | 171 ++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 2 + target/arm/Kconfig | 4 + target/arm/Makefile.objs | 1 + 6 files changed, 178 insertions(+), 139 deletions(-) create mode 100644 target/arm/cpu_v6.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index f176a98296..3aa27f3b40 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -13,9 +13,7 @@ CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_HIGHBANK=y -CONFIG_FSL_IMX31=y CONFIG_MUSCA=y -CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y CONFIG_VEXPRESS=y diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f1d1ba8451..34908828a0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1834,135 +1834,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -static void arm1136_r2_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an - * older core than plain "arm1136". In particular this does not - * have the v6K features. - * These ID register values are correct for 1136 but may be wrong - * for 1136_r2 (in particular r0p2 does not actually implement most - * of the ID registers). - */ - - cpu->dtb_compatible = "arm,arm1136"; - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); - set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - cpu->midr = 0x4107b362; - cpu->reset_fpsid = 0x410120b4; - cpu->isar.mvfr0 = 0x11111111; - cpu->isar.mvfr1 = 0x00000000; - cpu->ctr = 0x1dd20d2; - cpu->reset_sctlr = 0x00050078; - cpu->id_pfr0 = 0x111; - cpu->id_pfr1 = 0x1; - cpu->isar.id_dfr0 = 0x2; - cpu->id_afr0 = 0x3; - cpu->isar.id_mmfr0 = 0x01130003; - cpu->isar.id_mmfr1 = 0x10030302; - cpu->isar.id_mmfr2 = 0x01222110; - cpu->isar.id_isar0 = 0x00140011; - cpu->isar.id_isar1 = 0x12002111; - cpu->isar.id_isar2 = 0x11231111; - cpu->isar.id_isar3 = 0x01102131; - cpu->isar.id_isar4 = 0x141; - cpu->reset_auxcr = 7; -} - -static void arm1136_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,arm1136"; - set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); - set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - cpu->midr = 0x4117b363; - cpu->reset_fpsid = 0x410120b4; - cpu->isar.mvfr0 = 0x11111111; - cpu->isar.mvfr1 = 0x00000000; - cpu->ctr = 0x1dd20d2; - cpu->reset_sctlr = 0x00050078; - cpu->id_pfr0 = 0x111; - cpu->id_pfr1 = 0x1; - cpu->isar.id_dfr0 = 0x2; - cpu->id_afr0 = 0x3; - cpu->isar.id_mmfr0 = 0x01130003; - cpu->isar.id_mmfr1 = 0x10030302; - cpu->isar.id_mmfr2 = 0x01222110; - cpu->isar.id_isar0 = 0x00140011; - cpu->isar.id_isar1 = 0x12002111; - cpu->isar.id_isar2 = 0x11231111; - cpu->isar.id_isar3 = 0x01102131; - cpu->isar.id_isar4 = 0x141; - cpu->reset_auxcr = 7; -} - -static void arm1176_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,arm1176"; - set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VAPA); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); - set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - set_feature(&cpu->env, ARM_FEATURE_EL3); - cpu->midr = 0x410fb767; - cpu->reset_fpsid = 0x410120b5; - cpu->isar.mvfr0 = 0x11111111; - cpu->isar.mvfr1 = 0x00000000; - cpu->ctr = 0x1dd20d2; - cpu->reset_sctlr = 0x00050078; - cpu->id_pfr0 = 0x111; - cpu->id_pfr1 = 0x11; - cpu->isar.id_dfr0 = 0x33; - cpu->id_afr0 = 0; - cpu->isar.id_mmfr0 = 0x01130003; - cpu->isar.id_mmfr1 = 0x10030302; - cpu->isar.id_mmfr2 = 0x01222100; - cpu->isar.id_isar0 = 0x0140011; - cpu->isar.id_isar1 = 0x12002111; - cpu->isar.id_isar2 = 0x11231121; - cpu->isar.id_isar3 = 0x01102131; - cpu->isar.id_isar4 = 0x01141; - cpu->reset_auxcr = 7; -} - -static void arm11mpcore_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,arm11mpcore"; - set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VAPA); - set_feature(&cpu->env, ARM_FEATURE_MPIDR); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr = 0x410fb022; - cpu->reset_fpsid = 0x410120b4; - cpu->isar.mvfr0 = 0x11111111; - cpu->isar.mvfr1 = 0x00000000; - cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ - cpu->id_pfr0 = 0x111; - cpu->id_pfr1 = 0x1; - cpu->isar.id_dfr0 = 0; - cpu->id_afr0 = 0x2; - cpu->isar.id_mmfr0 = 0x01100103; - cpu->isar.id_mmfr1 = 0x10020302; - cpu->isar.id_mmfr2 = 0x01222000; - cpu->isar.id_isar0 = 0x00100011; - cpu->isar.id_isar1 = 0x12002111; - cpu->isar.id_isar2 = 0x11221011; - cpu->isar.id_isar3 = 0x01102131; - cpu->isar.id_isar4 = 0x141; - cpu->reset_auxcr = 1; -} - static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -2452,14 +2323,6 @@ static void arm_max_initfn(Object *obj) static const ARMCPUInfo arm_cpus[] = { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an - * older core than plain "arm1136". In particular this does not - * have the v6K features. - */ - { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, - { .name = "arm1136", .initfn = arm1136_initfn }, - { .name = "arm1176", .initfn = arm1176_initfn }, - { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, { .name = "cortex-m0", .initfn = cortex_m0_initfn, .class_init = arm_v7m_class_init }, { .name = "cortex-m3", .initfn = cortex_m3_initfn, diff --git a/target/arm/cpu_v6.c b/target/arm/cpu_v6.c new file mode 100644 index 0000000000..1c73c881f3 --- /dev/null +++ b/target/arm/cpu_v6.c @@ -0,0 +1,171 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static void arm1136_r2_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + /* + * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an + * older core than plain "arm1136". In particular this does not + * have the v6K features. + * These ID register values are correct for 1136 but may be wrong + * for 1136_r2 (in particular r0p2 does not actually implement most + * of the ID registers). + */ + + cpu->dtb_compatible = "arm,arm1136"; + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); + set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + cpu->midr = 0x4107b362; + cpu->reset_fpsid = 0x410120b4; + cpu->isar.mvfr0 = 0x11111111; + cpu->isar.mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00050078; + cpu->id_pfr0 = 0x111; + cpu->id_pfr1 = 0x1; + cpu->isar.id_dfr0 = 0x2; + cpu->id_afr0 = 0x3; + cpu->isar.id_mmfr0 = 0x01130003; + cpu->isar.id_mmfr1 = 0x10030302; + cpu->isar.id_mmfr2 = 0x01222110; + cpu->isar.id_isar0 = 0x00140011; + cpu->isar.id_isar1 = 0x12002111; + cpu->isar.id_isar2 = 0x11231111; + cpu->isar.id_isar3 = 0x01102131; + cpu->isar.id_isar4 = 0x141; + cpu->reset_auxcr = 7; +} + +static void arm1136_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,arm1136"; + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); + set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + cpu->midr = 0x4117b363; + cpu->reset_fpsid = 0x410120b4; + cpu->isar.mvfr0 = 0x11111111; + cpu->isar.mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00050078; + cpu->id_pfr0 = 0x111; + cpu->id_pfr1 = 0x1; + cpu->isar.id_dfr0 = 0x2; + cpu->id_afr0 = 0x3; + cpu->isar.id_mmfr0 = 0x01130003; + cpu->isar.id_mmfr1 = 0x10030302; + cpu->isar.id_mmfr2 = 0x01222110; + cpu->isar.id_isar0 = 0x00140011; + cpu->isar.id_isar1 = 0x12002111; + cpu->isar.id_isar2 = 0x11231111; + cpu->isar.id_isar3 = 0x01102131; + cpu->isar.id_isar4 = 0x141; + cpu->reset_auxcr = 7; +} + +static void arm1176_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,arm1176"; + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_VAPA); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); + set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->midr = 0x410fb767; + cpu->reset_fpsid = 0x410120b5; + cpu->isar.mvfr0 = 0x11111111; + cpu->isar.mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00050078; + cpu->id_pfr0 = 0x111; + cpu->id_pfr1 = 0x11; + cpu->isar.id_dfr0 = 0x33; + cpu->id_afr0 = 0; + cpu->isar.id_mmfr0 = 0x01130003; + cpu->isar.id_mmfr1 = 0x10030302; + cpu->isar.id_mmfr2 = 0x01222100; + cpu->isar.id_isar0 = 0x0140011; + cpu->isar.id_isar1 = 0x12002111; + cpu->isar.id_isar2 = 0x11231121; + cpu->isar.id_isar3 = 0x01102131; + cpu->isar.id_isar4 = 0x01141; + cpu->reset_auxcr = 7; +} + +static void arm11mpcore_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,arm11mpcore"; + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_VAPA); + set_feature(&cpu->env, ARM_FEATURE_MPIDR); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr = 0x410fb022; + cpu->reset_fpsid = 0x410120b4; + cpu->isar.mvfr0 = 0x11111111; + cpu->isar.mvfr1 = 0x00000000; + cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ + cpu->id_pfr0 = 0x111; + cpu->id_pfr1 = 0x1; + cpu->isar.id_dfr0 = 0; + cpu->id_afr0 = 0x2; + cpu->isar.id_mmfr0 = 0x01100103; + cpu->isar.id_mmfr1 = 0x10020302; + cpu->isar.id_mmfr2 = 0x01222000; + cpu->isar.id_isar0 = 0x00100011; + cpu->isar.id_isar1 = 0x12002111; + cpu->isar.id_isar2 = 0x11221011; + cpu->isar.id_isar3 = 0x01102131; + cpu->isar.id_isar4 = 0x141; + cpu->reset_auxcr = 1; +} + +static const ARMCPUInfo arm_v6_cpus[] = { + /* + * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. + * an older core than plain "arm1136". In particular this does + * not have the v6K features. + */ + { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, + { .name = "arm1136", .initfn = arm1136_initfn }, + { .name = "arm1176", .initfn = arm1176_initfn }, + { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, + { .name = NULL } +}; + +static void arm_v6_cpu_register_types(void) +{ + const ARMCPUInfo *info = arm_v6_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v6_cpu_register_types) + +#endif diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3b78471de0..e87dd611f2 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -113,6 +113,7 @@ config NETDUINOPLUS2 config NSERIES bool + select ARM_V6 select OMAP select TMP105 # tempature sensor select BLIZZARD # LCD/TV controller @@ -367,6 +368,7 @@ config FSL_IMX25 config FSL_IMX31 bool + select ARM_V6 select SERIAL select IMX select IMX_I2C diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 028d8382fe..df5f8dff42 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -6,5 +6,9 @@ config ARM_V5 depends on TCG bool +config ARM_V6 + depends on TCG + bool + config ARM_V7M bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index f66f7f1158..0473c559c6 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -70,6 +70,7 @@ obj-y += m_helper.o obj-$(CONFIG_ARM_V4) += cpu_v4.o obj-$(CONFIG_ARM_V5) += cpu_v5.o +obj-$(CONFIG_ARM_V6) += cpu_v6.o obj-$(CONFIG_SOFTMMU) += psci.o From patchwork Mon Mar 16 16:06:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440689 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 43B4B14E5 for ; Mon, 16 Mar 2020 16:16:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 138C720679 for ; Mon, 16 Mar 2020 16:16:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="KCglB/pK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732067AbgCPQQD (ORCPT ); Mon, 16 Mar 2020 12:16:03 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:22891 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732021AbgCPQQC (ORCPT ); Mon, 16 Mar 2020 12:16:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375362; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ruq5flSyrIJQ0ARl8BHVFpMVJrCuW/pkqeZBiZJSNHg=; b=KCglB/pK8QUOhHk7/3NFHSG0h9/UGSU4ZnsWatuco8FgS+8CAH7UX0sMnjTKX6J3A1MVm4 smQs8xiPXTy/MB5MerOeAovzXnclEQEPrQuF00l7nGehUiOriWoi8N0Y3qhsaR1Ss6wQy5 bxCqSHFSxq90/qKah3+Obks4bKj97rI= Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-433-WZ9kpkZ5MUKHN4a3UUHkrg-1; Mon, 16 Mar 2020 12:07:50 -0400 X-MC-Unique: WZ9kpkZ5MUKHN4a3UUHkrg-1 Received: by mail-wr1-f71.google.com with SMTP id w11so9254638wrp.20 for ; Mon, 16 Mar 2020 09:07:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ruq5flSyrIJQ0ARl8BHVFpMVJrCuW/pkqeZBiZJSNHg=; b=Gy+4qJSORUwBUhkgSFWxIvDAYZKUkd1gTshy2adX1s4U0WnVic3kcFhatJLL2b6JLl ftBiufG+rBdbZFfxYwIHAOZCxRpP7UBb5NYXWgn7z6tFpm4zokR/BDo6HExwk6q9dG01 paa/slJv7N25W4i/UtHaMB9T8ycoVRp4J77Ia2iLRmB0HSTimGaAWNrX6ys0PyMOZYzv OyjXmNNcjBdBRjeg43peyEa/S7h5WdwIMYEeMREdqu4F3E2TWEMMjSdI80QW5iYfzsnl VkhpLCDFtffm3qrVonR3C90JVpFUBSVN1kS4trjUIbabI3Nwz6Tchy8t7YUu3ky+RTsY wdzw== X-Gm-Message-State: ANhLgQ1uR0bvxQwwjIsUPcTDebOtbE2LSwXxCHBLX1fi4PrwUVwngqpT HzeezqQaP8/PzIlymh+6oJHuq1BnR+TVKDbRuUrOyD5jHhVJWj5pM9HyGGQZF0EyoCHkvT05+Xn 6IAvy/rLE8ays X-Received: by 2002:a5d:5089:: with SMTP id a9mr63910wrt.187.1584374869131; Mon, 16 Mar 2020 09:07:49 -0700 (PDT) X-Google-Smtp-Source: ADFU+vsH9erD+/AzduZt6/2G1VOVoVwqiEnP7oEPNYJjE5gdXKGGdo2hHizz2wb54XtGoBPo2ebMbQ== X-Received: by 2002:a5d:5089:: with SMTP id a9mr63883wrt.187.1584374868815; Mon, 16 Mar 2020 09:07:48 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id k9sm494508wrd.74.2020.03.16.09.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 13/19] target/arm: Restrict ARMv7 R-profile cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:28 +0100 Message-Id: <20200316160634.3386-14-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A KVM-only build won't be able to run R-profile cpus. Only enable the following ARMv7 R-Profile CPUs when TCG is available: - Cortex-R5 - Cortex-R5F Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- default-configs/aarch64-softmmu.mak | 1 - target/arm/cpu.c | 51 ------------------ target/arm/cpu_v7r.c | 83 +++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + target/arm/Kconfig | 4 ++ target/arm/Makefile.objs | 1 + 6 files changed, 89 insertions(+), 52 deletions(-) create mode 100644 target/arm/cpu_v7r.c diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak index 958b1e08e4..a4202f5681 100644 --- a/default-configs/aarch64-softmmu.mak +++ b/default-configs/aarch64-softmmu.mak @@ -3,6 +3,5 @@ # We support all the 32 bit boards so need all their config include arm-softmmu.mak -CONFIG_XLNX_ZYNQMP_ARM=y CONFIG_XLNX_VERSAL=y CONFIG_SBSA_REF=y diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 34908828a0..84be8792f6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1975,55 +1975,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; } -static const ARMCPRegInfo cortexr5_cp_reginfo[] = { - /* Dummy the TCM region regs for the moment */ - { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, - .access = PL1_RW, .type = ARM_CP_CONST }, - { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, - .access = PL1_RW, .type = ARM_CP_CONST }, - { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, - .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, - REGINFO_SENTINEL -}; - -static void cortex_r5_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_V7MP); - set_feature(&cpu->env, ARM_FEATURE_PMSA); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr = 0x411fc153; /* r1p3 */ - cpu->id_pfr0 = 0x0131; - cpu->id_pfr1 = 0x001; - cpu->isar.id_dfr0 = 0x010400; - cpu->id_afr0 = 0x0; - cpu->isar.id_mmfr0 = 0x0210030; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x01200000; - cpu->isar.id_mmfr3 = 0x0211; - cpu->isar.id_isar0 = 0x02101111; - cpu->isar.id_isar1 = 0x13112111; - cpu->isar.id_isar2 = 0x21232141; - cpu->isar.id_isar3 = 0x01112131; - cpu->isar.id_isar4 = 0x0010142; - cpu->isar.id_isar5 = 0x0; - cpu->isar.id_isar6 = 0x0; - cpu->mp_is_up = true; - cpu->pmsav7_dregion = 16; - define_arm_cp_regs(cpu, cortexr5_cp_reginfo); -} - -static void cortex_r5f_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cortex_r5_initfn(obj); - cpu->isar.mvfr0 = 0x10110221; - cpu->isar.mvfr1 = 0x00000011; -} - static const ARMCPRegInfo cortexa8_cp_reginfo[] = { { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -2333,8 +2284,6 @@ static const ARMCPUInfo arm_cpus[] = { .class_init = arm_v7m_class_init }, { .name = "cortex-m33", .initfn = cortex_m33_initfn, .class_init = arm_v7m_class_init }, - { .name = "cortex-r5", .initfn = cortex_r5_initfn }, - { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, { .name = "cortex-a7", .initfn = cortex_a7_initfn }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, diff --git a/target/arm/cpu_v7r.c b/target/arm/cpu_v7r.c new file mode 100644 index 0000000000..9576844b5c --- /dev/null +++ b/target/arm/cpu_v7r.c @@ -0,0 +1,83 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static const ARMCPRegInfo cortexr5_cp_reginfo[] = { + /* Dummy the TCM region regs for the moment */ + { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST }, + { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST }, + { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, + .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, + REGINFO_SENTINEL +}; + +static void cortex_r5_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr = 0x411fc153; /* r1p3 */ + cpu->id_pfr0 = 0x0131; + cpu->id_pfr1 = 0x001; + cpu->isar.id_dfr0 = 0x010400; + cpu->id_afr0 = 0x0; + cpu->isar.id_mmfr0 = 0x0210030; + cpu->isar.id_mmfr1 = 0x00000000; + cpu->isar.id_mmfr2 = 0x01200000; + cpu->isar.id_mmfr3 = 0x0211; + cpu->isar.id_isar0 = 0x02101111; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232141; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x0010142; + cpu->isar.id_isar5 = 0x0; + cpu->isar.id_isar6 = 0x0; + cpu->mp_is_up = true; + cpu->pmsav7_dregion = 16; + define_arm_cp_regs(cpu, cortexr5_cp_reginfo); +} + +static void cortex_r5f_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cortex_r5_initfn(obj); + cpu->isar.mvfr0 = 0x10110221; + cpu->isar.mvfr1 = 0x00000011; +} + +static const ARMCPUInfo arm_v7r_cpus[] = { + { .name = "cortex-r5", .initfn = cortex_r5_initfn }, + { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, + { .name = NULL } +}; + +static void arm_v7r_cpu_register_types(void) +{ + const ARMCPUInfo *info = arm_v7r_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v7r_cpu_register_types) + +#endif diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e87dd611f2..d0903d8544 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -340,6 +340,7 @@ config XLNX_ZYNQMP_ARM bool select AHCI select ARM_GIC + select ARM_V7R select CADENCE select DDC select DPCD diff --git a/target/arm/Kconfig b/target/arm/Kconfig index df5f8dff42..9768f9180f 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -10,5 +10,9 @@ config ARM_V6 depends on TCG bool +config ARM_V7R + depends on TCG + bool + config ARM_V7M bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 0473c559c6..a2508f0655 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -71,6 +71,7 @@ obj-y += m_helper.o obj-$(CONFIG_ARM_V4) += cpu_v4.o obj-$(CONFIG_ARM_V5) += cpu_v5.o obj-$(CONFIG_ARM_V6) += cpu_v6.o +obj-$(CONFIG_ARM_V7R) += cpu_v7r.o obj-$(CONFIG_SOFTMMU) += psci.o From patchwork Mon Mar 16 16:06:29 2020 Content-Type: text/plain; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id u25sm215843wml.17.2020.03.16.09.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 14/19] target/arm: Restrict ARMv7 M-profile cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:29 +0100 Message-Id: <20200316160634.3386-15-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A KVM-only build won't be able to run M-profile cpus. Only enable the following ARMv7 M-Profile CPUs when TCG is available: - Cortex-M3 - Cortex-M4 - Cortex-M33 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 8 -- target/arm/cpu.c | 176 --------------------------- target/arm/cpu_v7m.c | 207 ++++++++++++++++++++++++++++++++ target/arm/Kconfig | 1 + target/arm/Makefile.objs | 1 + 5 files changed, 209 insertions(+), 184 deletions(-) create mode 100644 target/arm/cpu_v7m.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 3aa27f3b40..511d74da58 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -12,19 +12,11 @@ CONFIG_ARM_V7M=y CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y -CONFIG_HIGHBANK=y -CONFIG_MUSCA=y -CONFIG_STELLARIS=y CONFIG_REALVIEW=y CONFIG_VEXPRESS=y CONFIG_ZYNQ=y -CONFIG_NETDUINO2=y -CONFIG_NETDUINOPLUS2=y -CONFIG_MPS2=y CONFIG_RASPI=y CONFIG_SABRELITE=y -CONFIG_EMCRAFT_SF2=y -CONFIG_MICROBIT=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_ALLWINNER_H3=y diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 84be8792f6..dfa7e64c7e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -573,31 +573,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return true; } -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - CPUClass *cc = CPU_GET_CLASS(cs); - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - bool ret = false; - - /* ARMv7-M interrupt masking works differently than -A or -R. - * There is no FIQ/IRQ distinction. Instead of I and F bits - * masking FIQ and IRQ interrupts, an exception is taken only - * if it is higher priority than the current execution priority - * (which depends on state like BASEPRI, FAULTMASK and the - * currently active exception). - */ - if (interrupt_request & CPU_INTERRUPT_HARD - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { - cs->exception_index = EXCP_IRQ; - cc->do_interrupt(cs); - ret = true; - } - return ret; -} -#endif - void arm_cpu_update_virq(ARMCPU *cpu) { /* @@ -1834,147 +1809,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -static void cortex_m0_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_M); - - cpu->midr = 0x410cc200; -} - -static void cortex_m3_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - cpu->midr = 0x410fc231; - cpu->pmsav7_dregion = 8; - cpu->id_pfr0 = 0x00000030; - cpu->id_pfr1 = 0x00000200; - cpu->isar.id_dfr0 = 0x00100000; - cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00000030; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x00000000; - cpu->isar.id_mmfr3 = 0x00000000; - cpu->isar.id_isar0 = 0x01141110; - cpu->isar.id_isar1 = 0x02111000; - cpu->isar.id_isar2 = 0x21112231; - cpu->isar.id_isar3 = 0x01111110; - cpu->isar.id_isar4 = 0x01310102; - cpu->isar.id_isar5 = 0x00000000; - cpu->isar.id_isar6 = 0x00000000; -} - -static void cortex_m4_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr = 0x410fc240; /* r0p0 */ - cpu->pmsav7_dregion = 8; - cpu->isar.mvfr0 = 0x10110021; - cpu->isar.mvfr1 = 0x11000011; - cpu->isar.mvfr2 = 0x00000000; - cpu->id_pfr0 = 0x00000030; - cpu->id_pfr1 = 0x00000200; - cpu->isar.id_dfr0 = 0x00100000; - cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00000030; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x00000000; - cpu->isar.id_mmfr3 = 0x00000000; - cpu->isar.id_isar0 = 0x01141110; - cpu->isar.id_isar1 = 0x02111000; - cpu->isar.id_isar2 = 0x21112231; - cpu->isar.id_isar3 = 0x01111110; - cpu->isar.id_isar4 = 0x01310102; - cpu->isar.id_isar5 = 0x00000000; - cpu->isar.id_isar6 = 0x00000000; -} - -static void cortex_m7_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr = 0x411fc272; /* r1p2 */ - cpu->pmsav7_dregion = 8; - cpu->isar.mvfr0 = 0x10110221; - cpu->isar.mvfr1 = 0x12000011; - cpu->isar.mvfr2 = 0x00000040; - cpu->id_pfr0 = 0x00000030; - cpu->id_pfr1 = 0x00000200; - cpu->isar.id_dfr0 = 0x00100000; - cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00100030; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x01000000; - cpu->isar.id_mmfr3 = 0x00000000; - cpu->isar.id_isar0 = 0x01101110; - cpu->isar.id_isar1 = 0x02112000; - cpu->isar.id_isar2 = 0x20232231; - cpu->isar.id_isar3 = 0x01111131; - cpu->isar.id_isar4 = 0x01310132; - cpu->isar.id_isar5 = 0x00000000; - cpu->isar.id_isar6 = 0x00000000; -} - -static void cortex_m33_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr = 0x410fd213; /* r0p3 */ - cpu->pmsav7_dregion = 16; - cpu->sau_sregion = 8; - cpu->isar.mvfr0 = 0x10110021; - cpu->isar.mvfr1 = 0x11000011; - cpu->isar.mvfr2 = 0x00000040; - cpu->id_pfr0 = 0x00000030; - cpu->id_pfr1 = 0x00000210; - cpu->isar.id_dfr0 = 0x00200000; - cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x00101F40; - cpu->isar.id_mmfr1 = 0x00000000; - cpu->isar.id_mmfr2 = 0x01000000; - cpu->isar.id_mmfr3 = 0x00000000; - cpu->isar.id_isar0 = 0x01101110; - cpu->isar.id_isar1 = 0x02212000; - cpu->isar.id_isar2 = 0x20232232; - cpu->isar.id_isar3 = 0x01111131; - cpu->isar.id_isar4 = 0x01310132; - cpu->isar.id_isar5 = 0x00000000; - cpu->isar.id_isar6 = 0x00000000; - cpu->clidr = 0x00000000; - cpu->ctr = 0x8000c000; -} - -static void arm_v7m_class_init(ObjectClass *oc, void *data) -{ - ARMCPUClass *acc = ARM_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); - - acc->info = data; -#ifndef CONFIG_USER_ONLY - cc->do_interrupt = arm_v7m_cpu_do_interrupt; -#endif - - cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; -} - static const ARMCPRegInfo cortexa8_cp_reginfo[] = { { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -2274,16 +2108,6 @@ static void arm_max_initfn(Object *obj) static const ARMCPUInfo arm_cpus[] = { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - { .name = "cortex-m0", .initfn = cortex_m0_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-m3", .initfn = cortex_m3_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-m4", .initfn = cortex_m4_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-m7", .initfn = cortex_m7_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-m33", .initfn = cortex_m33_initfn, - .class_init = arm_v7m_class_init }, { .name = "cortex-a7", .initfn = cortex_a7_initfn }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, diff --git a/target/arm/cpu_v7m.c b/target/arm/cpu_v7m.c new file mode 100644 index 0000000000..529259b9cd --- /dev/null +++ b/target/arm/cpu_v7m.c @@ -0,0 +1,207 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc = CPU_GET_CLASS(cs); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + bool ret = false; + + /* + * ARMv7-M interrupt masking works differently than -A or -R. + * There is no FIQ/IRQ distinction. Instead of I and F bits + * masking FIQ and IRQ interrupts, an exception is taken only + * if it is higher priority than the current execution priority + * (which depends on state like BASEPRI, FAULTMASK and the + * currently active exception). + */ + if (interrupt_request & CPU_INTERRUPT_HARD + && (armv7m_nvic_can_take_pending_exception(env->nvic))) { + cs->exception_index = EXCP_IRQ; + cc->do_interrupt(cs); + ret = true; + } + return ret; +} + +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + cpu->midr = 0x410cc200; +} + +static void cortex_m3_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + cpu->midr = 0x410fc231; + cpu->pmsav7_dregion = 8; + cpu->id_pfr0 = 0x00000030; + cpu->id_pfr1 = 0x00000200; + cpu->isar.id_dfr0 = 0x00100000; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_mmfr0 = 0x00000030; + cpu->isar.id_mmfr1 = 0x00000000; + cpu->isar.id_mmfr2 = 0x00000000; + cpu->isar.id_mmfr3 = 0x00000000; + cpu->isar.id_isar0 = 0x01141110; + cpu->isar.id_isar1 = 0x02111000; + cpu->isar.id_isar2 = 0x21112231; + cpu->isar.id_isar3 = 0x01111110; + cpu->isar.id_isar4 = 0x01310102; + cpu->isar.id_isar5 = 0x00000000; + cpu->isar.id_isar6 = 0x00000000; +} + +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr = 0x410fc240; /* r0p0 */ + cpu->pmsav7_dregion = 8; + cpu->isar.mvfr0 = 0x10110021; + cpu->isar.mvfr1 = 0x11000011; + cpu->isar.mvfr2 = 0x00000000; + cpu->id_pfr0 = 0x00000030; + cpu->id_pfr1 = 0x00000200; + cpu->isar.id_dfr0 = 0x00100000; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_mmfr0 = 0x00000030; + cpu->isar.id_mmfr1 = 0x00000000; + cpu->isar.id_mmfr2 = 0x00000000; + cpu->isar.id_mmfr3 = 0x00000000; + cpu->isar.id_isar0 = 0x01141110; + cpu->isar.id_isar1 = 0x02111000; + cpu->isar.id_isar2 = 0x21112231; + cpu->isar.id_isar3 = 0x01111110; + cpu->isar.id_isar4 = 0x01310102; + cpu->isar.id_isar5 = 0x00000000; + cpu->isar.id_isar6 = 0x00000000; +} + +static void cortex_m7_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr = 0x411fc272; /* r1p2 */ + cpu->pmsav7_dregion = 8; + cpu->isar.mvfr0 = 0x10110221; + cpu->isar.mvfr1 = 0x12000011; + cpu->isar.mvfr2 = 0x00000040; + cpu->id_pfr0 = 0x00000030; + cpu->id_pfr1 = 0x00000200; + cpu->isar.id_dfr0 = 0x00100000; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_mmfr0 = 0x00100030; + cpu->isar.id_mmfr1 = 0x00000000; + cpu->isar.id_mmfr2 = 0x01000000; + cpu->isar.id_mmfr3 = 0x00000000; + cpu->isar.id_isar0 = 0x01101110; + cpu->isar.id_isar1 = 0x02112000; + cpu->isar.id_isar2 = 0x20232231; + cpu->isar.id_isar3 = 0x01111131; + cpu->isar.id_isar4 = 0x01310132; + cpu->isar.id_isar5 = 0x00000000; + cpu->isar.id_isar6 = 0x00000000; +} + +static void cortex_m33_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr = 0x410fd213; /* r0p3 */ + cpu->pmsav7_dregion = 16; + cpu->sau_sregion = 8; + cpu->isar.mvfr0 = 0x10110021; + cpu->isar.mvfr1 = 0x11000011; + cpu->isar.mvfr2 = 0x00000040; + cpu->id_pfr0 = 0x00000030; + cpu->id_pfr1 = 0x00000210; + cpu->isar.id_dfr0 = 0x00200000; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_mmfr0 = 0x00101F40; + cpu->isar.id_mmfr1 = 0x00000000; + cpu->isar.id_mmfr2 = 0x01000000; + cpu->isar.id_mmfr3 = 0x00000000; + cpu->isar.id_isar0 = 0x01101110; + cpu->isar.id_isar1 = 0x02212000; + cpu->isar.id_isar2 = 0x20232232; + cpu->isar.id_isar3 = 0x01111131; + cpu->isar.id_isar4 = 0x01310132; + cpu->isar.id_isar5 = 0x00000000; + cpu->isar.id_isar6 = 0x00000000; + cpu->clidr = 0x00000000; + cpu->ctr = 0x8000c000; +} + +static void arm_v7m_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc = ARM_CPU_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + + acc->info = data; +#ifndef CONFIG_USER_ONLY + cc->do_interrupt = arm_v7m_cpu_do_interrupt; +#endif + + cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; +} + +static const ARMCPUInfo arm_v7m_cpus[] = { + { .name = "cortex-m0", .initfn = cortex_m0_initfn, + .class_init = arm_v7m_class_init }, + { .name = "cortex-m3", .initfn = cortex_m3_initfn, + .class_init = arm_v7m_class_init }, + { .name = "cortex-m4", .initfn = cortex_m4_initfn, + .class_init = arm_v7m_class_init }, + { .name = "cortex-m7", .initfn = cortex_m7_initfn, + .class_init = arm_v7m_class_init }, + { .name = "cortex-m33", .initfn = cortex_m33_initfn, + .class_init = arm_v7m_class_init }, + { .name = NULL } +}; + +static void arm_v7m_cpu_register_types(void) +{ + const ARMCPUInfo *info = arm_v7m_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v7m_cpu_register_types) + +#endif diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 9768f9180f..929e252d89 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -15,4 +15,5 @@ config ARM_V7R bool config ARM_V7M + depends on TCG bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index a2508f0655..a0df58526b 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -72,6 +72,7 @@ obj-$(CONFIG_ARM_V4) += cpu_v4.o obj-$(CONFIG_ARM_V5) += cpu_v5.o obj-$(CONFIG_ARM_V6) += cpu_v6.o obj-$(CONFIG_ARM_V7R) += cpu_v7r.o +obj-$(CONFIG_ARM_V7M) += cpu_v7m.o obj-$(CONFIG_SOFTMMU) += psci.o From patchwork Mon Mar 16 16:06:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440677 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 59BFB139A for ; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id f203sm206459wmf.18.2020.03.16.09.07.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 15/19] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M Date: Mon, 16 Mar 2020 17:06:30 +0100 Message-Id: <20200316160634.3386-16-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Thomas Huth We've already got the CONFIG_ARM_V7M switch, but it currently can not be disabled yet. The m_helper.c code should not be compiled into the binary if the switch is not enabled. We also have to provide some stubs in a separate file to make sure that we still can link the other code without CONFIG_ARM_V7M. Signed-off-by: Thomas Huth Message-Id: <20190903154810.27365-4-thuth@redhat.com> [PMD: add write_v7m_exception() stub when not using TCG, remove CONFIG_ARM_V7M=y in default-configs/arm-softmmu.mak] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 6 ---- target/arm/cpu.h | 7 ++++ target/arm/m_helper-stub.c | 59 +++++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 3 +- 4 files changed, 68 insertions(+), 7 deletions(-) create mode 100644 target/arm/m_helper-stub.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 511d74da58..7ae8006556 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -1,11 +1,5 @@ # Default configuration for arm-softmmu -# CONFIG_SEMIHOSTING is always required on this architecture -CONFIG_SEMIHOSTING=y - -# TODO: ARM_V7M is currently always required - make this more flexible! -CONFIG_ARM_V7M=y - # CONFIG_PCI_DEVICES=n # CONFIG_TEST_DEVICES=n diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ffd991b6f..84e14ce5a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1278,7 +1278,14 @@ void pmu_init(ARMCPU *cpu); /* Write a new value to v7m.exception, thus transitioning into or out * of Handler mode; this may result in a change of active stack pointer. */ +#if !defined(CONFIG_TCG) +static inline void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + g_assert_not_reached(); +} +#else void write_v7m_exception(CPUARMState *env, uint32_t new_exc); +#endif /* Map EL and handler into a PSTATE_MODE. */ static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c new file mode 100644 index 0000000000..9316a9995b --- /dev/null +++ b/target/arm/m_helper-stub.c @@ -0,0 +1,59 @@ +/* + * ARM V7M related stubs. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "internals.h" + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + abort(); +} + +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) +{ + abort(); +} + +uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) +{ + abort(); +} + +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) +{ + abort(); +} + +uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) +{ + abort(); +} + +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + abort(); +} + +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + abort(); +} + +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + abort(); +} + +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + abort(); +} + +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + abort(); +} diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index a0df58526b..993899d731 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -66,7 +66,8 @@ obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o obj-y += crypto_helper.o obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o -obj-y += m_helper.o +obj-$(CONFIG_ARM_V7M) += m_helper.o +obj-$(call lnot,$(CONFIG_ARM_V7M)) += m_helper-stub.o obj-$(CONFIG_ARM_V4) += cpu_v4.o obj-$(CONFIG_ARM_V5) += cpu_v5.o From patchwork Mon Mar 16 16:06:31 2020 Content-Type: text/plain; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id o23sm553874wro.23.2020.03.16.09.08.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:08:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson , Samuel Ortiz Subject: [PATCH v3 16/19] target/arm: Do not build TCG objects when TCG is off Date: Mon, 16 Mar 2020 17:06:31 +0100 Message-Id: <20200316160634.3386-17-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Samuel Ortiz We can now safely turn all TCG dependent build off when CONFIG_TCG is off. This allows building ARM binaries with --disable-tcg. Signed-off-by: Samuel Ortiz [PMD: Heavily rebased during 18 months] Signed-off-by: Philippe Mathieu-Daudé --- target/arm/Makefile.objs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 993899d731..0178431549 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -60,8 +60,6 @@ ifeq ($(CONFIG_TCG),y) obj-$(CONFIG_SEMIHOSTING) += arm-semi.o obj-$(call lnot,$(CONFIG_SEMIHOSTING)) += arm-semi-stub.o -endif # CONFIG_TCG - obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o obj-y += crypto_helper.o @@ -80,3 +78,5 @@ obj-$(CONFIG_SOFTMMU) += psci.o obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o obj-$(TARGET_AARCH64) += pauth_helper.o + +endif # CONFIG_TCG From patchwork Mon Mar 16 16:06:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440679 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B6BFA139A for ; Mon, 16 Mar 2020 16:14:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9767F2071C for ; Mon, 16 Mar 2020 16:14:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="S82D8Yof" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732075AbgCPQOV (ORCPT ); Mon, 16 Mar 2020 12:14:21 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:47959 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732062AbgCPQOV (ORCPT ); Mon, 16 Mar 2020 12:14:21 -0400 X-Greylist: delayed 457 seconds by postgrey-1.27 at vger.kernel.org; Mon, 16 Mar 2020 12:14:21 EDT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375260; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kMtlamo7Zl3wCiVgcr8iciiwh4khJI79F07LAInMKRc=; b=S82D8YofBZZxBHKff+KXXUNL32EI4mq5wct+Dv2jBoaD96A772iuz/zmxDC2K+QOwCHBO5 p30l/k4sLNPWBfiXUObLHCo9Z32afm+3kXkkYahv33evV5MXXfLGfCb4gTcv9rSIJMdH2z fAw+r/zqkqxjgmkUXWrYSXfqFNcudmk= Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-210-l8UuJ0x_OCuyPrEX8w-EiQ-1; Mon, 16 Mar 2020 12:08:12 -0400 X-MC-Unique: l8UuJ0x_OCuyPrEX8w-EiQ-1 Received: by mail-wm1-f69.google.com with SMTP id p4so5071050wmp.0 for ; Mon, 16 Mar 2020 09:08:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kMtlamo7Zl3wCiVgcr8iciiwh4khJI79F07LAInMKRc=; b=fFXCXWWbb1itZ9HueJuxm9TrLyF+BzXF65QXdi6R3P4kvg7bkCtETZuTBv1lNWSV7S CUc5P5wgq8E9N7WgAUHqOlfrpcOpwHCKGmVCx4eg18/Y9Y3RGf1YeAG+8eg/+t7Sg2By //43xeYjoYeJR3JSRqxKkHwGHcK/oGBChj/p3cwC4rY/a8CARm46FexJJQPwEvCCFGZr HC8Fhl+B8RYH43SDsvmvnFyrQOgGFbrdgQsZMWVC7ZQJr5RIFjoN79YWvpVB+WxA8CK5 ccYlfFyB4Nj8lsOd2gbqrpUdOD9JjzEYhInHaYD7el65qRqrVamawnuYU3FB+kDByNan p7AQ== X-Gm-Message-State: ANhLgQ0IlVF9ECtBsEQ+qnyEQ0PmEsmDo7XOfgrb1Mehkn8JKTHDqqHZ sNa+6mtY3nDxpm9G6qPwFUT2KNv52eV3HmYd2IdyGYtUO8sUV6PjR0i+sGbvuDrPb74M1X827hJ hL0a+XFfaIkUH X-Received: by 2002:a1c:3241:: with SMTP id y62mr29793851wmy.66.1584374890988; Mon, 16 Mar 2020 09:08:10 -0700 (PDT) X-Google-Smtp-Source: ADFU+vuQxAMoxg+u/+lPk/pzDgAO3wAjX2ARHQMgEZz41ANJhw8Gpk7UQYNDXjdjZkbYOg+VPhVfcg== X-Received: by 2002:a1c:3241:: with SMTP id y62mr29793824wmy.66.1584374890780; Mon, 16 Mar 2020 09:08:10 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id 127sm70683wmd.38.2020.03.16.09.08.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:08:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM Date: Mon, 16 Mar 2020 17:06:32 +0100 Message-Id: <20200316160634.3386-18-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When building a KVM-only QEMU, the 'virt' machine is a good default :) Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d0903d8544..8e801cd15f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -1,5 +1,6 @@ config ARM_VIRT bool + default y if KVM imply PCI_DEVICES imply TEST_DEVICES imply VFIO_AMD_XGBE From patchwork Mon Mar 16 16:06:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440697 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6BEF017E6 for ; Mon, 16 Mar 2020 16:18:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4D04620679 for ; Mon, 16 Mar 2020 16:18:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="E43LbxCR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732036AbgCPQSk (ORCPT ); Mon, 16 Mar 2020 12:18:40 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:33408 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731864AbgCPQSk (ORCPT ); Mon, 16 Mar 2020 12:18:40 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375519; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Q9pxkDoDUc80lR6q2sbnb9Lu1UrGguk51WkG66GGoIk=; b=E43LbxCRHuyvwwMDzDB/qkKFpNpj+FRhE2xXMnH2NYXwJKWle3Uu2rEXVakix4aevfSl2z VRrhqHj0uf+5HVt8nwx1/nm15MY01eElE207N3lqNrr16RXWoibqFj8vi7oJ+/79pweEUp YWy/EQx5SCMf7JM/eWoCM0Ct0skEClU= Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-30-19tdrR8MPKKS0_ipBoRQOg-1; Mon, 16 Mar 2020 12:08:19 -0400 X-MC-Unique: 19tdrR8MPKKS0_ipBoRQOg-1 Received: by mail-ed1-f70.google.com with SMTP id w23so4879103edu.18 for ; Mon, 16 Mar 2020 09:08:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q9pxkDoDUc80lR6q2sbnb9Lu1UrGguk51WkG66GGoIk=; b=s2Ahc0re6+PiCYMryeviKn0p1kAjdh3P0b3n6+Ubs/qVrNK04LSY+gACIk0fNl3Low CCngmrT+w/2ftTSCfNwwqeEPdGFy5Q0gnEiiD2bHyzdsSrGzYDCdVdpTFL0VUoE7I5Lh jZ2Ilq/klZBqKszDPhaIswefEx8P08Zo8CBevfn3VRLU9qpT0Wet56md0CZoqpzdYEIO W90LGe35eO7uc/ihEOKXcpYpryO5XI8GVe1V552UMenCGpyWvX3m5NtMswtBuFq4Pl7H viUlE0bTkk8XLc5aGTDffgjm8R+lunP5iR9QJuYeBGecVjxKFeFNcax77/sxiEXfYt0D ze4w== X-Gm-Message-State: ANhLgQ1wOnbRTHWuGacynidecgO3JSoSYsoD+V4n4xIsSk6Qi+CeDUK+ 3dgu6FQ/hKfU8kG8bfHjUA8d1+61HJTUMpv0ZT5IxPur46jmG6//oL/9jRhsfAurDk66j/YytS8 5iF4hBXTs+Yt4 X-Received: by 2002:aa7:c716:: with SMTP id i22mr639023edq.205.1584374897542; Mon, 16 Mar 2020 09:08:17 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtucDPtYCUUmNKo1v786732XgsbrhpkRJ66ECnTqKEicI6pa/tNzUTcvXKFSS8tLcL/QhoQsA== X-Received: by 2002:adf:b3d6:: with SMTP id x22mr99071wrd.242.1584374896425; Mon, 16 Mar 2020 09:08:16 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id x13sm268246wmj.5.2020.03.16.09.08.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:08:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson , Stefano Stabellini , Anthony Perard , Paul Durrant , xen-devel@lists.xenproject.org Subject: [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen Date: Mon, 16 Mar 2020 17:06:33 +0100 Message-Id: <20200316160634.3386-19-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Xen on ARM does not use QEMU machines [*]. Disable the 'virt' machine there to avoid odd errors such: CC i386-softmmu/hw/cpu/a15mpcore.o hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM Signed-off-by: Philippe Mathieu-Daudé --- Cc: Stefano Stabellini Cc: Anthony Perard Cc: Paul Durrant Cc: xen-devel@lists.xenproject.org --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 8e801cd15f..69a8e30125 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -1,5 +1,6 @@ config ARM_VIRT bool + depends on !XEN default y if KVM imply PCI_DEVICES imply TEST_DEVICES From patchwork Mon Mar 16 16:06:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11440683 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B845313B1 for ; Mon, 16 Mar 2020 16:14:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 992F12071C for ; Mon, 16 Mar 2020 16:14:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="DS/6rMY3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732084AbgCPQOf (ORCPT ); Mon, 16 Mar 2020 12:14:35 -0400 Received: from us-smtp-delivery-74.mimecast.com ([216.205.24.74]:29663 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731992AbgCPQOf (ORCPT ); Mon, 16 Mar 2020 12:14:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375273; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N7+HmyV0D4vFSs4ZL/u4BopejDTWdgLZjfeVHLnQ9M4=; b=DS/6rMY33zEHCE6VfPG1hhaj/nKTlvHOjuAb8PiUrheBYsuA+43m6qkycieOuMF3GaczUI EfeP6T+kRv1KPRTexamJWAhnfKimm8y22KcGvapijNaAPAzCU+t8XNpD0vXG0Otvlee4CP pQnyvgfLM0IejgYDOkHyyQg2OlQBLMY= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-421-CiUXNBgWOjOH8dLE4p7DVw-1; Mon, 16 Mar 2020 12:08:23 -0400 X-MC-Unique: CiUXNBgWOjOH8dLE4p7DVw-1 Received: by mail-wr1-f69.google.com with SMTP id p5so9176589wrj.17 for ; Mon, 16 Mar 2020 09:08:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N7+HmyV0D4vFSs4ZL/u4BopejDTWdgLZjfeVHLnQ9M4=; b=aArtDaeKkrpfx6TXb8YRQ90aIF++Cs7GUEO60YlZjVOO0VOfh4TaiOHK97q5U3pHgG 298uPuAbOMbUnIBdXw1/GYCXMvvfZ3a3uWkgdhv+jZuWquZeHf7IhL8XpXnCcC/k3/ts qWucUgqhB0apRRdB3vY/L/zIAuJHS6GZQfRgYtvvDgTd7HvdPJiS9mJQQw08N4Nu176C HBBZM6r6BYcJzzDSb5V/vWo7gbMY9E2dDea/yf6Hzt5pKR8OD841rgiAvk+EBaQjLP3V u7VBweY0lHy6XS+fVDA7HXAGhy/arpW2Q4w9dnJ/udCh9O/yxNB96G+E7ozoNcCj+j+I S52A== X-Gm-Message-State: ANhLgQ23uCp+vIY7ipTT5wifivlcovpWM8G66YTgCMIs+MZKEklVog7b IzHbYcEgiPLTryo0EW9Ej6KKu+iwMey7BZoJuEs2cZTpevc2FGxrIrY83WmCz7mALlQcl1cE2eL PZFhjFJLR0Cxl X-Received: by 2002:a1c:984a:: with SMTP id a71mr29937835wme.185.1584374902205; Mon, 16 Mar 2020 09:08:22 -0700 (PDT) X-Google-Smtp-Source: ADFU+vssyfrGmsyQfMixG6XPmVZD6SHgaog1D2LjTAVp2uFXc9h0dhfPsS644yu8c8+ZyHwycJ4JHQ== X-Received: by 2002:a1c:984a:: with SMTP id a71mr29937801wme.185.1584374901937; Mon, 16 Mar 2020 09:08:21 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id v10sm170121wml.44.2020.03.16.09.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:08:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Thomas Huth , qemu-arm@nongnu.org, Fam Zheng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Richard Henderson Subject: [PATCH v3 19/19] .travis.yml: Add a KVM-only Aarch64 job Date: Mon, 16 Mar 2020 17:06:34 +0100 Message-Id: <20200316160634.3386-20-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a job to build QEMU on Aarch64 with TCG disabled, so this configuration won't bitrot over time. Signed-off-by: Philippe Mathieu-Daudé --- Job ran for 13 min 1 sec https://travis-ci.org/github/philmd/qemu/jobs/663122258 --- .travis.yml | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/.travis.yml b/.travis.yml index b92798ac3b..ea3c0df185 100644 --- a/.travis.yml +++ b/.travis.yml @@ -450,6 +450,38 @@ jobs: - TEST_CMD="make check check-tcg V=1" - CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}" + - name: "[aarch64] GCC check (KVM)" + arch: arm64 + dist: xenial + addons: + apt_packages: + - libaio-dev + - libattr1-dev + - libcap-ng-dev + - libgcrypt20-dev + - libgnutls28-dev + - libiscsi-dev + - liblttng-ust-dev + - libnfs-dev + - libnss3-dev + - libpixman-1-dev + - libpng-dev + - librados-dev + - libseccomp-dev + - liburcu-dev + - libusb-1.0-0-dev + - libvdeplug-dev + - libvte-2.91-dev + # Tests dependencies + - genisoimage + env: + - CONFIG="--disable-containers --disable-tcg --enable-kvm --enable-fdt --disable-tools" + - TEST_CMD="make check-unit" + script: + # Only select the 'virt' machine. + - echo CONFIG_ARM_VIRT=y > ${SRC_DIR}/default-configs/aarch64-softmmu.mak + - make -j3 && travis_retry ${TEST_CMD} + - name: "[ppc64] GCC check-tcg" arch: ppc64le dist: xenial