From patchwork Thu Mar 19 07:50:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446581 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E30A139A for ; Thu, 19 Mar 2020 07:50:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7E53F20722 for ; Thu, 19 Mar 2020 07:50:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="etdFSG2I" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726793AbgCSHul (ORCPT ); Thu, 19 Mar 2020 03:50:41 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33248 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726783AbgCSHuk (ORCPT ); Thu, 19 Mar 2020 03:50:40 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oc2T114021; Thu, 19 Mar 2020 02:50:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604238; bh=L5YWy3Rk6IsInxACeN4EjPHJ7UQIXvFkql19PkmlqPM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=etdFSG2IFoqRU2c76qoioed+5B8ogcsi8UwpxadKEORyxEEr90a+pRLQVfddAK69M yRp3SAN7XbobVc45xYEoJ5yXLHP7Jz/3dJXnAzkIr4tj5KPKTqH6uysBr696Fo3Ddy rM9ofZAzCNXeTAuFWzxieDiZzTqNJsX8Ymlj8LCY= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7oc4f118700 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:50:38 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:37 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:37 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqe047151; Thu, 19 Mar 2020 02:50:35 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen , Subject: [PATCH v2 01/19] media: ti-vpe: cal: fix DMA memory corruption Date: Thu, 19 Mar 2020 09:50:05 +0200 Message-ID: <20200319075023.22151-2-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org When the CAL driver stops streaming, it will shut everything down without waiting for the current frame to finish. This leaves the CAL DMA in a slightly undefined state, and when CAL DMA is enabled when the stream is started the next time, the old DMA transfer will continue. It is not clear if the old DMA transfer continues with the exact settings of the original transfer, or is it a mix of old and new settings, but in any case the end result is memory corruption as the destination memory address is no longer valid. I could not find any way to ensure that any old DMA transfer would be discarded, except perhaps full CAL reset. But we cannot do a full reset when one port is getting enabled, as that would reset both ports. This patch tries to make sure that the DMA transfer is finished properly when the stream is being stopped. I say "tries", as, as mentioned above, I don't see a way to force the DMA transfer to finish. I believe this fixes the corruptions for normal cases, but if for some reason the DMA of the final frame would stall a lot, resulting in timeout in the code waiting for the DMA to finish, we'll again end up with unfinished DMA transfer. However, I don't know what could cause such a timeout. Signed-off-by: Tomi Valkeinen Cc: stable@vger.kernel.org Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 6c8f3702eac0..9dd6de14189b 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -412,6 +412,8 @@ struct cal_ctx { struct cal_buffer *cur_frm; /* Pointer pointing to next v4l2_buffer */ struct cal_buffer *next_frm; + + bool dma_act; }; static const struct cal_fmt *find_format_by_pix(struct cal_ctx *ctx, @@ -942,6 +944,7 @@ static void csi2_lane_config(struct cal_ctx *ctx) static void csi2_ppi_enable(struct cal_ctx *ctx) { + reg_write(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port), BIT(3)); reg_write_field(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port), CAL_GEN_ENABLE, CAL_CSI2_PPI_CTRL_IF_EN_MASK); } @@ -1204,15 +1207,25 @@ static irqreturn_t cal_irq(int irq_cal, void *data) if (isportirqset(irqst2, 1)) { ctx = dev->ctx[0]; + spin_lock(&ctx->slock); + ctx->dma_act = false; + if (ctx->cur_frm != ctx->next_frm) cal_process_buffer_complete(ctx); + + spin_unlock(&ctx->slock); } if (isportirqset(irqst2, 2)) { ctx = dev->ctx[1]; + spin_lock(&ctx->slock); + ctx->dma_act = false; + if (ctx->cur_frm != ctx->next_frm) cal_process_buffer_complete(ctx); + + spin_unlock(&ctx->slock); } } @@ -1228,6 +1241,7 @@ static irqreturn_t cal_irq(int irq_cal, void *data) dma_q = &ctx->vidq; spin_lock(&ctx->slock); + ctx->dma_act = true; if (!list_empty(&dma_q->active) && ctx->cur_frm == ctx->next_frm) cal_schedule_next_buffer(ctx); @@ -1239,6 +1253,7 @@ static irqreturn_t cal_irq(int irq_cal, void *data) dma_q = &ctx->vidq; spin_lock(&ctx->slock); + ctx->dma_act = true; if (!list_empty(&dma_q->active) && ctx->cur_frm == ctx->next_frm) cal_schedule_next_buffer(ctx); @@ -1711,10 +1726,27 @@ static void cal_stop_streaming(struct vb2_queue *vq) struct cal_ctx *ctx = vb2_get_drv_priv(vq); struct cal_dmaqueue *dma_q = &ctx->vidq; struct cal_buffer *buf, *tmp; + unsigned long timeout; unsigned long flags; int ret; + bool dma_act; csi2_ppi_disable(ctx); + + /* wait for stream and dma to finish */ + dma_act = true; + timeout = jiffies + msecs_to_jiffies(500); + while (dma_act && time_before(jiffies, timeout)) { + msleep(50); + + spin_lock_irqsave(&ctx->slock, flags); + dma_act = ctx->dma_act; + spin_unlock_irqrestore(&ctx->slock, flags); + } + + if (dma_act) + ctx_err(ctx, "failed to disable dma cleanly\n"); + disable_irqs(ctx); csi2_phy_deinit(ctx); From patchwork Thu Mar 19 07:50:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446583 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E96B2139A for ; Thu, 19 Mar 2020 07:50:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CA47F20740 for ; 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Thu, 19 Mar 2020 02:50:39 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:38 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:38 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqf047151; Thu, 19 Mar 2020 02:50:37 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 02/19] media: ti-vpe: cal: improve enable_irqs Date: Thu, 19 Mar 2020 09:50:06 +0200 Message-ID: <20200319075023.22151-3-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org IRQENABLE_SET registers are (usually) not meant to be read, only written to. The current driver needlessly uses read-modify-write cycle to enable IRQ bits. The read-modify-write has no bad side effects here, but it's still better to clean this up by only using write. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 9dd6de14189b..76d55c76d938 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -706,16 +706,16 @@ static void cal_quickdump_regs(struct cal_dev *dev) */ static void enable_irqs(struct cal_ctx *ctx) { + u32 val; + /* Enable IRQ_WDMA_END 0/1 */ - reg_write_field(ctx->dev, - CAL_HL_IRQENABLE_SET(2), - CAL_HL_IRQ_ENABLE, - CAL_HL_IRQ_MASK(ctx->csi2_port)); + val = 0; + set_field(&val, CAL_HL_IRQ_ENABLE, CAL_HL_IRQ_MASK(ctx->csi2_port)); + reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(2), val); /* Enable IRQ_WDMA_START 0/1 */ - reg_write_field(ctx->dev, - CAL_HL_IRQENABLE_SET(3), - CAL_HL_IRQ_ENABLE, - CAL_HL_IRQ_MASK(ctx->csi2_port)); + val = 0; + set_field(&val, CAL_HL_IRQ_ENABLE, CAL_HL_IRQ_MASK(ctx->csi2_port)); + reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(3), val); /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */ reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0xFF000000); } From patchwork Thu Mar 19 07:50:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446585 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05E50139A for ; Thu, 19 Mar 2020 07:50:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DAE3B20740 for ; Thu, 19 Mar 2020 07:50:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="f/cUcBGe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726825AbgCSHuo (ORCPT ); Thu, 19 Mar 2020 03:50:44 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33268 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726666AbgCSHun (ORCPT ); Thu, 19 Mar 2020 03:50:43 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7ofkd114035; Thu, 19 Mar 2020 02:50:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604241; bh=OYoh55qtmfyODFvPJ89VFKI4w8Oz23RJFVZbbMTzlYw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f/cUcBGeiKXcCvwAiZgHx0WFld+89CyRDXI5IsM+uAoJFu2efKA89BCm2SWsdLZFH U8PPa44BN/MOm/4OTooTFNk3MS1A1XT4Yn0rAXY0fgu1UoawVdUJlMKF5szmiO67L/ tIwHlDQOO5dD7PN9rcjGphCOtusmltSdzHMuhCUs= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7of0Q026383; Thu, 19 Mar 2020 02:50:41 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:40 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:40 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqg047151; Thu, 19 Mar 2020 02:50:39 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 03/19] media: ti-vpe: cal: fix use of wrong macro Date: Thu, 19 Mar 2020 09:50:07 +0200 Message-ID: <20200319075023.22151-4-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org i913_errata() sets a bit to 1 in PHY_REG10, but for some reason uses CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE for the bit value. The value of that macro is 1, so it works, but is still wrong. Fix this to 1. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 76d55c76d938..c418296df0f8 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -645,8 +645,7 @@ static void i913_errata(struct cal_dev *dev, unsigned int port) { u32 reg10 = reg_read(dev->cc[port], CAL_CSI2_PHY_REG10); - set_field(®10, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE, - CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK); + set_field(®10, 1, CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK); cal_dbg(1, dev, "CSI2_%d_REG10 = 0x%08x\n", port, reg10); reg_write(dev->cc[port], CAL_CSI2_PHY_REG10, reg10); From patchwork Thu Mar 19 07:50:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446587 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B3B8013B1 for ; Thu, 19 Mar 2020 07:50:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 934572076C for ; Thu, 19 Mar 2020 07:50:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Vx0dcDru" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726845AbgCSHuq (ORCPT ); Thu, 19 Mar 2020 03:50:46 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33278 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726666AbgCSHup (ORCPT ); Thu, 19 Mar 2020 03:50:45 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7ogd4114045; Thu, 19 Mar 2020 02:50:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604242; bh=g/9shvgeOXqlaZO0ZQlp+0TnLZUEk9yDroAc3WOOoyY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Vx0dcDruqGbv5DNbEYXql5LYfsQDfp2YeMYGuRVXwomjzibomYrDTAvxh7975L1sc kpn/ORF8mY3pnDdZ/Uub7yrtosl2tyyvSPnhwI2ekV5V9yFcUohF7r7KDlaangd6Ah FCReSiV6MkAtOLIx57tmqc2CYUeY1P+9D+XWbp3I= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7ogY8129264 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:50:42 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:42 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:42 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqh047151; Thu, 19 Mar 2020 02:50:41 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 04/19] media: ti-vpe: cal: use runtime_resume for errata handling Date: Thu, 19 Mar 2020 09:50:08 +0200 Message-ID: <20200319075023.22151-5-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org We need to do errata handling every time CAL is being enabled. The code is currently in cal_runtime_get(), which is not the correct place for it. Move the code to cal_runtime_resume, which is called every time CAL is enabled. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 36 ++++++++++++++++++----------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index c418296df0f8..4fe37f284b54 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -653,20 +653,7 @@ static void i913_errata(struct cal_dev *dev, unsigned int port) static int cal_runtime_get(struct cal_dev *dev) { - int r; - - r = pm_runtime_get_sync(&dev->pdev->dev); - - if (dev->flags & DRA72_CAL_PRE_ES2_LDO_DISABLE) { - /* - * Apply errata on both port eveytime we (re-)enable - * the clock - */ - i913_errata(dev, 0); - i913_errata(dev, 1); - } - - return r; + return pm_runtime_get_sync(&dev->pdev->dev); } static inline void cal_runtime_put(struct cal_dev *dev) @@ -2409,11 +2396,32 @@ static const struct of_device_id cal_of_match[] = { MODULE_DEVICE_TABLE(of, cal_of_match); #endif +static int cal_runtime_resume(struct device *dev) +{ + struct cal_dev *caldev = dev_get_drvdata(dev); + + if (caldev->flags & DRA72_CAL_PRE_ES2_LDO_DISABLE) { + /* + * Apply errata on both port everytime we (re-)enable + * the clock + */ + i913_errata(caldev, 0); + i913_errata(caldev, 1); + } + + return 0; +} + +static const struct dev_pm_ops cal_pm_ops = { + .runtime_resume = cal_runtime_resume, +}; + static struct platform_driver cal_pdrv = { .probe = cal_probe, .remove = cal_remove, .driver = { .name = CAL_MODULE_NAME, + .pm = &cal_pm_ops, .of_match_table = of_match_ptr(cal_of_match), }, }; From patchwork Thu Mar 19 07:50:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446589 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 290F8139A for ; Thu, 19 Mar 2020 07:50:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0967C20757 for ; Thu, 19 Mar 2020 07:50:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="NYk7SHpv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726846AbgCSHus (ORCPT ); Thu, 19 Mar 2020 03:50:48 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:36982 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725768AbgCSHus (ORCPT ); Thu, 19 Mar 2020 03:50:48 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7ojDQ085577; Thu, 19 Mar 2020 02:50:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604245; bh=q9JRt66cxiu4lE9l2J/M3c2tFSZE7BGDc6A89OcpcmM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NYk7SHpvmKFLbW8n2Aq9kG5WrauRU1zKu4FMUV97QpHafdmYS7VQjoNyNYeoNi9hl islO6Yrehn61Ki7OuCqJUAAhsbNS8Lb80l8fW49oIZdQl7wkbqESU1IYlh8sjdUiWZ voW/6EYrQfpOeqU7psBvFSRO6Q08OH8BpiNm/npg= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7oj8X118909 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:50:45 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:44 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:44 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqi047151; Thu, 19 Mar 2020 02:50:42 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 05/19] media: ti-vpe: cal: drop cal_runtime_get/put Date: Thu, 19 Mar 2020 09:50:09 +0200 Message-ID: <20200319075023.22151-6-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Now that cal_runtime_get and cal_runtime_put are only direct wrappers to pm_runtime_get/put, we can drop cal_runtime_get and cal_runtime_put. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 4fe37f284b54..4f9dee3474ba 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -651,16 +651,6 @@ static void i913_errata(struct cal_dev *dev, unsigned int port) reg_write(dev->cc[port], CAL_CSI2_PHY_REG10, reg10); } -static int cal_runtime_get(struct cal_dev *dev) -{ - return pm_runtime_get_sync(&dev->pdev->dev); -} - -static inline void cal_runtime_put(struct cal_dev *dev) -{ - pm_runtime_put_sync(&dev->pdev->dev); -} - static void cal_quickdump_regs(struct cal_dev *dev) { cal_info(dev, "CAL Registers @ 0x%pa:\n", &dev->res->start); @@ -1666,7 +1656,7 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) goto err; } - cal_runtime_get(ctx->dev); + pm_runtime_get_sync(&ctx->dev->pdev->dev); csi2_ctx_config(ctx); pix_proc_config(ctx); @@ -1681,7 +1671,7 @@ static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) if (ret) { v4l2_subdev_call(ctx->sensor, core, s_power, 0); ctx_err(ctx, "stream on failed in subdev\n"); - cal_runtime_put(ctx->dev); + pm_runtime_put_sync(&ctx->dev->pdev->dev); goto err; } @@ -1761,7 +1751,7 @@ static void cal_stop_streaming(struct vb2_queue *vq) ctx->next_frm = NULL; spin_unlock_irqrestore(&ctx->slock, flags); - cal_runtime_put(ctx->dev); + pm_runtime_put_sync(&ctx->dev->pdev->dev); } static const struct vb2_ops cal_video_qops = { @@ -2316,14 +2306,14 @@ static int cal_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); - ret = cal_runtime_get(dev); + ret = pm_runtime_get_sync(&pdev->dev); if (ret) goto runtime_disable; /* Just check we can actually access the module */ cal_get_hwinfo(dev); - cal_runtime_put(dev); + pm_runtime_put_sync(&pdev->dev); return 0; @@ -2351,7 +2341,7 @@ static int cal_remove(struct platform_device *pdev) cal_dbg(1, dev, "Removing %s\n", CAL_MODULE_NAME); - cal_runtime_get(dev); + pm_runtime_get_sync(&pdev->dev); for (i = 0; i < CAL_NUM_CONTEXT; i++) { ctx = dev->ctx[i]; @@ -2367,7 +2357,7 @@ static int cal_remove(struct platform_device *pdev) } } - cal_runtime_put(dev); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); return 0; From patchwork Thu Mar 19 07:50:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446591 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B278A139A for ; Thu, 19 Mar 2020 07:50:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9349F2072C for ; Thu, 19 Mar 2020 07:50:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vgbtRks8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726859AbgCSHuu (ORCPT ); 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Thu, 19 Mar 2020 02:50:45 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:45 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqj047151; Thu, 19 Mar 2020 02:50:44 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 06/19] media: ti-vpe: cal: catch error irqs and print errors Date: Thu, 19 Mar 2020 09:50:10 +0200 Message-ID: <20200319075023.22151-7-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org CAL reports various errors via IRQs, which are not handled at all by the current driver. Add code to enable and catch those IRQs and print errors. This will make it much easier to notice and debug issues with sensors. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 46 +++++++++++++++++++++++- drivers/media/platform/ti-vpe/cal_regs.h | 6 ++++ 2 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 4f9dee3474ba..838215a3f230 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -684,6 +684,21 @@ static void enable_irqs(struct cal_ctx *ctx) { u32 val; + const u32 cio_err_mask = + CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK | + CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK | + CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK | + CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK; + + /* Enable CIO error irqs */ + reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(1), + CAL_HL_IRQ_CIO_MASK(ctx->csi2_port)); + reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_IRQENABLE(ctx->csi2_port), + cio_err_mask); + + /* Always enable OCPO error */ + reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(1), CAL_HL_IRQ_OCPO_ERR_MASK); + /* Enable IRQ_WDMA_END 0/1 */ val = 0; set_field(&val, CAL_HL_IRQ_ENABLE, CAL_HL_IRQ_MASK(ctx->csi2_port)); @@ -700,6 +715,12 @@ static void disable_irqs(struct cal_ctx *ctx) { u32 val; + /* Disable CIO error irqs */ + reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(1), + CAL_HL_IRQ_CIO_MASK(ctx->csi2_port)); + reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_IRQENABLE(ctx->csi2_port), + 0); + /* Disable IRQ_WDMA_END 0/1 */ val = 0; set_field(&val, CAL_HL_IRQ_CLEAR, CAL_HL_IRQ_MASK(ctx->csi2_port)); @@ -1171,7 +1192,30 @@ static irqreturn_t cal_irq(int irq_cal, void *data) struct cal_dev *dev = (struct cal_dev *)data; struct cal_ctx *ctx; struct cal_dmaqueue *dma_q; - u32 irqst2, irqst3; + u32 irqst1, irqst2, irqst3; + + irqst1 = reg_read(dev, CAL_HL_IRQSTATUS(1)); + if (irqst1) { + int i; + + reg_write(dev, CAL_HL_IRQSTATUS(1), irqst1); + + if (irqst1 & CAL_HL_IRQ_OCPO_ERR_MASK) + dev_err_ratelimited(&dev->pdev->dev, "OCPO ERROR\n"); + + for (i = 1; i <= 2; ++i) { + if (irqst1 & CAL_HL_IRQ_CIO_MASK(i)) { + u32 cio_stat = reg_read(dev, + CAL_CSI2_COMPLEXIO_IRQSTATUS(i)); + + dev_err_ratelimited(&dev->pdev->dev, + "CIO%d error: %#08x\n", i, cio_stat); + + reg_write(dev, CAL_CSI2_COMPLEXIO_IRQSTATUS(i), + cio_stat); + } + } + } /* Check which DMA just finished */ irqst2 = reg_read(dev, CAL_HL_IRQSTATUS(2)); diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti-vpe/cal_regs.h index 0b76d1186074..2d71f1e86e2a 100644 --- a/drivers/media/platform/ti-vpe/cal_regs.h +++ b/drivers/media/platform/ti-vpe/cal_regs.h @@ -158,6 +158,11 @@ #define CAL_HL_IRQ_ENABLED 0x1 #define CAL_HL_IRQ_PENDING 0x1 +#define CAL_HL_IRQ_OCPO_ERR_MASK BIT(6) + +#define CAL_HL_IRQ_CIO_MASK(i) BIT(16 + ((i)-1) * 8) +#define CAL_HL_IRQ_VC_MASK(i) BIT(17 + ((i)-1) * 8) + #define CAL_PIX_PROC_EN_MASK BIT(0) #define CAL_PIX_PROC_EXTRACT_MASK GENMASK(4, 1) #define CAL_PIX_PROC_EXTRACT_B6 0x0 @@ -414,6 +419,7 @@ #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK BIT(17) #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK BIT(18) #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK BIT(19) +#define CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK GENMASK(19, 0) #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK BIT(20) #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK BIT(21) #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK BIT(22) From patchwork Thu Mar 19 07:50:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446593 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 43106139A for ; Thu, 19 Mar 2020 07:50:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 242E020740 for ; Thu, 19 Mar 2020 07:50:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="qbThSh44" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726867AbgCSHux (ORCPT ); Thu, 19 Mar 2020 03:50:53 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:40554 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725768AbgCSHux (ORCPT ); Thu, 19 Mar 2020 03:50:53 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7omMX123759; Thu, 19 Mar 2020 02:50:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604248; bh=6r+lXAe1oJNbFgzO5QTQlBz+chqnz1NhWKFPn8NHLt8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qbThSh44Wr9NJR7UGVx8iAFBm16A52YvC6/v8li9WiAfOpyTSj216xE3IrlAbFWm/ dN2sI/zOMMd1acAXJA33HfVIZXhtLq8AlkdKdvVNEZ5eYYoVg2iEq9PywfPfHNUPAj LwR9nNRS6vpkh5Vuzdmi7dCuLH2Ot6vYV3FhwDcM= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7omHQ035686 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:50:48 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:48 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:47 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqk047151; Thu, 19 Mar 2020 02:50:46 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 07/19] media: ti-vpe: cal: print errors on timeouts Date: Thu, 19 Mar 2020 09:50:11 +0200 Message-ID: <20200319075023.22151-8-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The driver does not print any errors on ComplexIO reset timeout or when waiting for stop-state, making it difficult to debug and notice problems. Add error prints for these cases. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 838215a3f230..b070c56f8d80 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -844,6 +844,11 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx) reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i, (i >= 250) ? "(timeout)" : ""); + if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) != + CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED) + ctx_err(ctx, "Timeout waiting for Complex IO reset done\n"); + /* 4. G. Wait for all enabled lane to reach stop state */ for (i = 0; i < 10; i++) { if (reg_read_field(ctx->dev, @@ -857,6 +862,9 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx) ctx->csi2_port, reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)), (i >= 10) ? "(timeout)" : ""); + if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), + CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0) + ctx_err(ctx, "Timeout waiting for stop state\n"); ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x (Bit(31,28) should be set!)\n", (ctx->csi2_port - 1), reg_read(ctx->cc, CAL_CSI2_PHY_REG1)); From patchwork Thu Mar 19 07:50:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446595 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 28B0113B1 for ; Thu, 19 Mar 2020 07:50:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 095BE20780 for ; Thu, 19 Mar 2020 07:50:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="H3lC2Aa1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726879AbgCSHuy (ORCPT ); Thu, 19 Mar 2020 03:50:54 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:37020 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726623AbgCSHuy (ORCPT ); Thu, 19 Mar 2020 03:50:54 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7onNE085592; Thu, 19 Mar 2020 02:50:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604249; bh=vZpbOU2dWm3Rvn6RhCOAQJcdEMOrD6Hl2qkg3kgwkxo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=H3lC2Aa1UkEBk8qeG+FB4CAOo69fSh5yg37fN1ZLjLyI+Q8WVC7XI9WDxlGSV/ZB3 6QSlk9BS3IOzSunLxq8hT7LMTNWDAVmrkMTtX30tc2SQJSgB+gyHMqZH36ILF8Qm8v XxfUwtnOBMQ1NlXlqg4l+nXh7W2OiZZc9Km3B+po= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7onwl026552; Thu, 19 Mar 2020 02:50:49 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:49 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:49 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXql047151; Thu, 19 Mar 2020 02:50:48 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 08/19] media: ti-vpe: cal: simplify irq handling Date: Thu, 19 Mar 2020 09:50:12 +0200 Message-ID: <20200319075023.22151-9-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Instead of having identical code block to handle irqs for the two CAL ports, we can have a for loop and a single code block. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 68 +++++++++++------------------ 1 file changed, 25 insertions(+), 43 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index b070c56f8d80..ba82f0887875 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -1228,64 +1228,46 @@ static irqreturn_t cal_irq(int irq_cal, void *data) /* Check which DMA just finished */ irqst2 = reg_read(dev, CAL_HL_IRQSTATUS(2)); if (irqst2) { + int i; + /* Clear Interrupt status */ reg_write(dev, CAL_HL_IRQSTATUS(2), irqst2); - /* Need to check both port */ - if (isportirqset(irqst2, 1)) { - ctx = dev->ctx[0]; - - spin_lock(&ctx->slock); - ctx->dma_act = false; - - if (ctx->cur_frm != ctx->next_frm) - cal_process_buffer_complete(ctx); - - spin_unlock(&ctx->slock); - } - - if (isportirqset(irqst2, 2)) { - ctx = dev->ctx[1]; + for (i = 1; i <= 2; ++i) { + if (isportirqset(irqst2, i)) { + ctx = dev->ctx[i - 1]; - spin_lock(&ctx->slock); - ctx->dma_act = false; + spin_lock(&ctx->slock); + ctx->dma_act = false; - if (ctx->cur_frm != ctx->next_frm) - cal_process_buffer_complete(ctx); + if (ctx->cur_frm != ctx->next_frm) + cal_process_buffer_complete(ctx); - spin_unlock(&ctx->slock); + spin_unlock(&ctx->slock); + } } } /* Check which DMA just started */ irqst3 = reg_read(dev, CAL_HL_IRQSTATUS(3)); if (irqst3) { + int i; + /* Clear Interrupt status */ reg_write(dev, CAL_HL_IRQSTATUS(3), irqst3); - /* Need to check both port */ - if (isportirqset(irqst3, 1)) { - ctx = dev->ctx[0]; - dma_q = &ctx->vidq; - - spin_lock(&ctx->slock); - ctx->dma_act = true; - if (!list_empty(&dma_q->active) && - ctx->cur_frm == ctx->next_frm) - cal_schedule_next_buffer(ctx); - spin_unlock(&ctx->slock); - } - - if (isportirqset(irqst3, 2)) { - ctx = dev->ctx[1]; - dma_q = &ctx->vidq; - - spin_lock(&ctx->slock); - ctx->dma_act = true; - if (!list_empty(&dma_q->active) && - ctx->cur_frm == ctx->next_frm) - cal_schedule_next_buffer(ctx); - spin_unlock(&ctx->slock); + for (i = 1; i <= 2; ++i) { + if (isportirqset(irqst3, i)) { + ctx = dev->ctx[i - 1]; + dma_q = &ctx->vidq; + + spin_lock(&ctx->slock); + ctx->dma_act = true; + if (!list_empty(&dma_q->active) && + ctx->cur_frm == ctx->next_frm) + cal_schedule_next_buffer(ctx); + spin_unlock(&ctx->slock); + } } } From patchwork Thu Mar 19 07:50:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446597 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7BC9213B1 for ; Thu, 19 Mar 2020 07:50:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5AE4B20722 for ; Thu, 19 Mar 2020 07:50:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="iog//wzy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726881AbgCSHuz (ORCPT ); Thu, 19 Mar 2020 03:50:55 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:37028 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725768AbgCSHuz (ORCPT ); Thu, 19 Mar 2020 03:50:55 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7opT5085606; Thu, 19 Mar 2020 02:50:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604251; bh=rL1PcGk8xTaMgm9Sl7HMN8UMmTyxhCuVs6EGG5joWiU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iog//wzyj0Z59BCQ4B1D+KSeLVr0Zc0/h5/Zt9eR2J1Rarh/bV+G45vAkPF9cKeoI 5JEN97FSvwsB7DCOX0b/lh2Igl54DN7c8Jik4J2gKlfbVNeVuV6vEfrZCE2r9dDs4/ Mv5mXVZWWjA4FjqeVbuX3ueP5CFKdO6rMvT6BUqE= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7op2J035759 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:50:51 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:51 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:51 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqm047151; Thu, 19 Mar 2020 02:50:49 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 09/19] media: ti-vpe: cal: remove useless CAL_GEN_* macros Date: Thu, 19 Mar 2020 09:50:13 +0200 Message-ID: <20200319075023.22151-10-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org These macros only obfuscate the code, so drop them. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 20 ++++++++------------ drivers/media/platform/ti-vpe/cal_regs.h | 9 --------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index ba82f0887875..53072afbaf4e 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -777,10 +777,8 @@ static void csi2_phy_init(struct cal_ctx *ctx) /* 3.B. Program Stop States */ val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)); - set_field(&val, CAL_GEN_ENABLE, - CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK); - set_field(&val, CAL_GEN_DISABLE, - CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK); + set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK); + set_field(&val, 0, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK); set_field(&val, 407, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK); reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val); ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n", @@ -789,8 +787,7 @@ static void csi2_phy_init(struct cal_ctx *ctx) /* 4. Force FORCERXMODE */ val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)); - set_field(&val, CAL_GEN_ENABLE, - CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK); + set_field(&val, 1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK); reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val); ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n", ctx->csi2_port, @@ -853,8 +850,7 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx) for (i = 0; i < 10; i++) { if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), - CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == - CAL_GEN_DISABLE) + CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0) break; usleep_range(1000, 1100); } @@ -951,13 +947,13 @@ static void csi2_ppi_enable(struct cal_ctx *ctx) { reg_write(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port), BIT(3)); reg_write_field(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port), - CAL_GEN_ENABLE, CAL_CSI2_PPI_CTRL_IF_EN_MASK); + 1, CAL_CSI2_PPI_CTRL_IF_EN_MASK); } static void csi2_ppi_disable(struct cal_ctx *ctx) { reg_write_field(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port), - CAL_GEN_DISABLE, CAL_CSI2_PPI_CTRL_IF_EN_MASK); + 0, CAL_CSI2_PPI_CTRL_IF_EN_MASK); } static void csi2_ctx_config(struct cal_ctx *ctx) @@ -1032,7 +1028,7 @@ static void pix_proc_config(struct cal_ctx *ctx) set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK); set_field(&val, pack, CAL_PIX_PROC_PACK_MASK); set_field(&val, ctx->csi2_port, CAL_PIX_PROC_CPORT_MASK); - set_field(&val, CAL_GEN_ENABLE, CAL_PIX_PROC_EN_MASK); + set_field(&val, 1, CAL_PIX_PROC_EN_MASK); reg_write(ctx->dev, CAL_PIX_PROC(ctx->csi2_port), val); ctx_dbg(3, ctx, "CAL_PIX_PROC(%d) = 0x%08x\n", ctx->csi2_port, reg_read(ctx->dev, CAL_PIX_PROC(ctx->csi2_port))); @@ -1052,7 +1048,7 @@ static void cal_wr_dma_config(struct cal_ctx *ctx, CAL_WR_DMA_CTRL_MODE_MASK); set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR, CAL_WR_DMA_CTRL_PATTERN_MASK); - set_field(&val, CAL_GEN_ENABLE, CAL_WR_DMA_CTRL_STALL_RD_MASK); + set_field(&val, 1, CAL_WR_DMA_CTRL_STALL_RD_MASK); reg_write(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port), val); ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->csi2_port, reg_read(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port))); diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti-vpe/cal_regs.h index 2d71f1e86e2a..3b3150aaf343 100644 --- a/drivers/media/platform/ti-vpe/cal_regs.h +++ b/drivers/media/platform/ti-vpe/cal_regs.h @@ -100,15 +100,6 @@ /* CAL Control Module Core Camerrx Control register offsets */ #define CM_CTRL_CORE_CAMERRX_CONTROL 0x000 -/********************************************************************* -* Generic value used in various field below -*********************************************************************/ - -#define CAL_GEN_DISABLE 0 -#define CAL_GEN_ENABLE 1 -#define CAL_GEN_FALSE 0 -#define CAL_GEN_TRUE 1 - /********************************************************************* * Field Definition Macros *********************************************************************/ From patchwork Thu Mar 19 07:50:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446599 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 62814139A for ; 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Thu, 19 Mar 2020 02:50:51 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 10/19] media: ti-vpe: cal: remove useless IRQ defines Date: Thu, 19 Mar 2020 09:50:14 +0200 Message-ID: <20200319075023.22151-11-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Remove a bunch of IRQ defines, of which only CAL_HL_IRQ_ENABLE and CAL_HL_IRQ_CLEAR are used, and these defines only end up obfuscating code. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 8 ++++---- drivers/media/platform/ti-vpe/cal_regs.h | 6 ------ 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 53072afbaf4e..979f9027a232 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -701,11 +701,11 @@ static void enable_irqs(struct cal_ctx *ctx) /* Enable IRQ_WDMA_END 0/1 */ val = 0; - set_field(&val, CAL_HL_IRQ_ENABLE, CAL_HL_IRQ_MASK(ctx->csi2_port)); + set_field(&val, 1, CAL_HL_IRQ_MASK(ctx->csi2_port)); reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(2), val); /* Enable IRQ_WDMA_START 0/1 */ val = 0; - set_field(&val, CAL_HL_IRQ_ENABLE, CAL_HL_IRQ_MASK(ctx->csi2_port)); + set_field(&val, 1, CAL_HL_IRQ_MASK(ctx->csi2_port)); reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(3), val); /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */ reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0xFF000000); @@ -723,11 +723,11 @@ static void disable_irqs(struct cal_ctx *ctx) /* Disable IRQ_WDMA_END 0/1 */ val = 0; - set_field(&val, CAL_HL_IRQ_CLEAR, CAL_HL_IRQ_MASK(ctx->csi2_port)); + set_field(&val, 1, CAL_HL_IRQ_MASK(ctx->csi2_port)); reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(2), val); /* Disable IRQ_WDMA_START 0/1 */ val = 0; - set_field(&val, CAL_HL_IRQ_CLEAR, CAL_HL_IRQ_MASK(ctx->csi2_port)); + set_field(&val, 1, CAL_HL_IRQ_MASK(ctx->csi2_port)); reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(3), val); /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */ reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0); diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti-vpe/cal_regs.h index 3b3150aaf343..6a235abc25b1 100644 --- a/drivers/media/platform/ti-vpe/cal_regs.h +++ b/drivers/media/platform/ti-vpe/cal_regs.h @@ -142,12 +142,6 @@ #define CAL_HL_IRQ_EOI_LINE_NUMBER_EOI0 0 #define CAL_HL_IRQ_MASK(m) BIT((m) - 1) -#define CAL_HL_IRQ_NOACTION 0x0 -#define CAL_HL_IRQ_ENABLE 0x1 -#define CAL_HL_IRQ_CLEAR 0x1 -#define CAL_HL_IRQ_DISABLED 0x0 -#define CAL_HL_IRQ_ENABLED 0x1 -#define CAL_HL_IRQ_PENDING 0x1 #define CAL_HL_IRQ_OCPO_ERR_MASK BIT(6) From patchwork Thu Mar 19 07:50:15 2020 Content-Type: text/plain; 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Thu, 19 Mar 2020 02:50:54 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqo047151; Thu, 19 Mar 2020 02:50:53 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 11/19] media: ti-vpe: cal: use reg_write_field Date: Thu, 19 Mar 2020 09:50:15 +0200 Message-ID: <20200319075023.22151-12-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Simplify the code by using reg_write_field() where trivially possible. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 34 ++++++++++++----------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 979f9027a232..5208dfde6fb5 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -761,10 +761,9 @@ static void csi2_phy_init(struct cal_ctx *ctx) camerarx_phy_enable(ctx); /* 2. Reset complex IO - Do not wait for reset completion */ - val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); - set_field(&val, CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL, - CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK); - reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); + reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL, + CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK); ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x De-assert Complex IO Reset\n", ctx->csi2_port, reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port))); @@ -786,18 +785,16 @@ static void csi2_phy_init(struct cal_ctx *ctx) reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port))); /* 4. Force FORCERXMODE */ - val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)); - set_field(&val, 1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK); - reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val); + reg_write_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), + 1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK); ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n", ctx->csi2_port, reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port))); /* E. Power up the PHY using the complex IO */ - val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); - set_field(&val, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON, - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); - reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); + reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON, + CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); /* F. Wait for power up completion */ for (i = 0; i < 10; i++) { @@ -869,13 +866,11 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx) static void csi2_phy_deinit(struct cal_ctx *ctx) { int i; - u32 val; /* Power down the PHY using the complex IO */ - val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); - set_field(&val, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF, - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); - reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); + reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF, + CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); /* Wait for power down completion */ for (i = 0; i < 10; i++) { @@ -892,10 +887,9 @@ static void csi2_phy_deinit(struct cal_ctx *ctx) (i >= 10) ? "(timeout)" : ""); /* Assert Comple IO Reset */ - val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); - set_field(&val, CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL, - CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK); - reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val); + reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL, + CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK); /* Wait for power down completion */ for (i = 0; i < 10; i++) { From patchwork Thu Mar 19 07:50:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446603 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1845F13B1 for ; Thu, 19 Mar 2020 07:51:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ECD7320732 for ; Thu, 19 Mar 2020 07:51:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nc+xsV5E" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726913AbgCSHvA (ORCPT ); Thu, 19 Mar 2020 03:51:00 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:40592 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726892AbgCSHu7 (ORCPT ); Thu, 19 Mar 2020 03:50:59 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7ouGt123802; Thu, 19 Mar 2020 02:50:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604257; bh=s5RIzkUXdXgS/5uYg+EaZUGNkT6uauDdwwxvpe+7FRk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nc+xsV5E4v/DeWeJcHURBQvfknk3S+mUIEib5F6eMUNHdA17eL0/u1pMpDCBMeWXI AiXqYLOFtnJ5LAMSYXOGUgLUn9tAW7mXQWwiz9dBAdr7zhc2Eue+X5iKDncH+NeMy7 DvThr/Ij44d2Bh9jHa/bZjZTHLYfclYKZxxCxjfQ= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7ouJV026714; Thu, 19 Mar 2020 02:50:56 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:56 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:56 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqp047151; Thu, 19 Mar 2020 02:50:55 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 12/19] media: ti-vpe: cal: cleanup CIO power enable/disable Date: Thu, 19 Mar 2020 09:50:16 +0200 Message-ID: <20200319075023.22151-13-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Move the code to enable and disable ComplexIO power to its own function. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 67 +++++++++++++---------------- 1 file changed, 31 insertions(+), 36 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 5208dfde6fb5..ed32b199aabe 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -733,11 +733,39 @@ static void disable_irqs(struct cal_ctx *ctx) reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0); } +static void csi2_cio_power(struct cal_ctx *ctx, bool enable) +{ + u32 target_state; + unsigned int i; + + target_state = enable ? CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON : + CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF; + + reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + target_state, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); + + for (i = 0; i < 10; i++) { + u32 current_state; + + current_state = reg_read_field(ctx->dev, + CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), + CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK); + + if (current_state == target_state) + break; + + usleep_range(1000, 1100); + } + + if (i == 10) + ctx_err(ctx, "Failed to power %s complexio\n", + enable ? "up" : "down"); +} + static void csi2_phy_config(struct cal_ctx *ctx); static void csi2_phy_init(struct cal_ctx *ctx) { - int i; u32 val; /* Steps @@ -792,23 +820,7 @@ static void csi2_phy_init(struct cal_ctx *ctx) reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port))); /* E. Power up the PHY using the complex IO */ - reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON, - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); - - /* F. Wait for power up completion */ - for (i = 0; i < 10; i++) { - if (reg_read_field(ctx->dev, - CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), - CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK) == - CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON) - break; - usleep_range(1000, 1100); - } - ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Powered UP %s\n", - ctx->csi2_port, - reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), - (i >= 10) ? "(timeout)" : ""); + csi2_cio_power(ctx, true); } static void csi2_wait_for_phy(struct cal_ctx *ctx) @@ -867,24 +879,7 @@ static void csi2_phy_deinit(struct cal_ctx *ctx) { int i; - /* Power down the PHY using the complex IO */ - reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF, - CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); - - /* Wait for power down completion */ - for (i = 0; i < 10; i++) { - if (reg_read_field(ctx->dev, - CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), - CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK) == - CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF) - break; - usleep_range(1000, 1100); - } - ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Powered Down %s\n", - ctx->csi2_port, - reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), - (i >= 10) ? "(timeout)" : ""); + csi2_cio_power(ctx, false); /* Assert Comple IO Reset */ reg_write_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), From patchwork Thu Mar 19 07:50:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446605 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E733139A for ; Thu, 19 Mar 2020 07:51:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4FC3720732 for ; Thu, 19 Mar 2020 07:51:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ThiNLjZ+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726934AbgCSHvC (ORCPT ); Thu, 19 Mar 2020 03:51:02 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:52682 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726905AbgCSHvC (ORCPT ); Thu, 19 Mar 2020 03:51:02 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7owdK083733; Thu, 19 Mar 2020 02:50:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604258; bh=b6IefihV/5IIyU+kvdug75KLHe4nMyKkG+AmBLiRkQc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ThiNLjZ+KSRqibdBImbmNmW1Dzkp+M6XG2CmLsgrNCq2aKrZLf1Elqamtulv5Kxqr CJfm4knTiy48lHRmB/TOH3+YiWcvTx4Azo99rYNMe7/Wrdolnp0s06tQhDBtgB0do8 YyoDtK6Hxsd1T4BKQreBe8+uDuWCSOoOUoa1+yXg= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7owQ8035938 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:50:58 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:50:58 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:50:58 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqq047151; Thu, 19 Mar 2020 02:50:56 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 13/19] media: ti-vpe: cal: fix dummy read to phy Date: Thu, 19 Mar 2020 09:50:17 +0200 Message-ID: <20200319075023.22151-14-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org After ComplexIO reset, a dummy read to PHY is needed as per CAL spec to finish the reset. Currently the driver reads a ComplexIO register, not PHY register. Fix this. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index ed32b199aabe..e6f766ba3079 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -796,8 +796,8 @@ static void csi2_phy_init(struct cal_ctx *ctx) ctx->csi2_port, reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port))); - /* Dummy read to allow SCP to complete */ - val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)); + /* Dummy read to allow SCP reset to complete */ + reg_read(ctx->cc, CAL_CSI2_PHY_REG0); /* 3.A. Program Phy Timing Parameters */ csi2_phy_config(ctx); From patchwork Thu Mar 19 07:50:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446607 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E9E2139A for ; Thu, 19 Mar 2020 07:51:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4E0022072C for ; Thu, 19 Mar 2020 07:51:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="qGMoJvix" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726968AbgCSHvD (ORCPT ); Thu, 19 Mar 2020 03:51:03 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:37062 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726936AbgCSHvD (ORCPT ); Thu, 19 Mar 2020 03:51:03 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7p02a085657; Thu, 19 Mar 2020 02:51:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604260; bh=+2JsNYs3ag5maY0Ds0ySy+/gb1saX5yLBelqJfEJPdQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qGMoJvixktl2TePoS7oPcdhQqjZn0q9IJXkKtAOZNZ6mzNfZ9yvSTxqaWwlEGAGw7 4GKhXjxGfIY99BcTw5dQvAy4/GiCMljkyRVSuxv/RvZyRMHrv4MGeppnUK6cSHBueK KT0nf9oAuuhFo+ytYimPs1wfe6oz0k3YASlESi9c= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7p0qN119224 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:51:00 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:51:00 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:51:00 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqr047151; Thu, 19 Mar 2020 02:50:58 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 14/19] media: ti-vpe: cal: program number of lines properly Date: Thu, 19 Mar 2020 09:50:18 +0200 Message-ID: <20200319075023.22151-15-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org CAL_CSI2_CTX register has LINES field, which, according to the documentation, should be programmed to the number of lines transmitted by the camera. If the number of lines is unknown, it can be set to 0. The driver sets the field to 0 for some reason, even if we know the number of lines. This patch sets the number of lines properly, which will allow the HW to discard extra lines (if the sensor would send such for some reason), and, according to documentation: "This leads to regular video timings and avoids potential artifacts". Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index e6f766ba3079..a59931ba3ed7 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -962,8 +962,7 @@ static void csi2_ctx_config(struct cal_ctx *ctx) set_field(&val, 0x1, CAL_CSI2_CTX_DT_MASK); /* Virtual Channel from the CSI2 sensor usually 0! */ set_field(&val, ctx->virtual_channel, CAL_CSI2_CTX_VC_MASK); - /* NUM_LINES_PER_FRAME => 0 means auto detect */ - set_field(&val, 0, CAL_CSI2_CTX_LINES_MASK); + set_field(&val, ctx->v_fmt.fmt.pix.height, CAL_CSI2_CTX_LINES_MASK); set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK); set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE, CAL_CSI2_CTX_PACK_MODE_MASK); From patchwork Thu Mar 19 07:50:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 797501894 for ; Thu, 19 Mar 2020 07:51:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5A2662072D for ; Thu, 19 Mar 2020 07:51:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="csPEoJ+x" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726970AbgCSHvF (ORCPT ); Thu, 19 Mar 2020 03:51:05 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33322 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726905AbgCSHvF (ORCPT ); Thu, 19 Mar 2020 03:51:05 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7p2ex114134; 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Thu, 19 Mar 2020 02:51:02 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqs047151; Thu, 19 Mar 2020 02:51:00 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 15/19] media: ti-vpe: cal: set DMA max seg size Date: Thu, 19 Mar 2020 09:50:19 +0200 Message-ID: <20200319075023.22151-16-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Set DMA max seg size correctly to get rid of warnings on 64 bit platforms: DMA-API: cal 6f03000.cal: mapping sg segment longer than device claims to support [len=720896] [max=65536] Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index a59931ba3ed7..b1b9616b12b6 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -2322,6 +2322,8 @@ static int cal_probe(struct platform_device *pdev) return -ENODEV; } + vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); + pm_runtime_enable(&pdev->dev); ret = pm_runtime_get_sync(&pdev->dev); @@ -2336,6 +2338,8 @@ static int cal_probe(struct platform_device *pdev) return 0; runtime_disable: + vb2_dma_contig_clear_max_seg_size(&pdev->dev); + pm_runtime_disable(&pdev->dev); for (i = 0; i < CAL_NUM_CONTEXT; i++) { ctx = dev->ctx[i]; @@ -2378,6 +2382,8 @@ static int cal_remove(struct platform_device *pdev) pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); + vb2_dma_contig_clear_max_seg_size(&pdev->dev); + return 0; } From patchwork Thu Mar 19 07:50:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446613 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D5AF6139A for ; Thu, 19 Mar 2020 07:51:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B5A0320740 for ; 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Thu, 19 Mar 2020 02:51:05 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:51:04 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:51:03 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqt047151; Thu, 19 Mar 2020 02:51:02 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 16/19] media: ti-vpe: cal: move code to separate functions Date: Thu, 19 Mar 2020 09:50:20 +0200 Message-ID: <20200319075023.22151-17-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org To make csi2_wait_for_phy() more readable, move code to separate functions. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 38 ++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index b1b9616b12b6..ed68ad58121e 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -823,20 +823,10 @@ static void csi2_phy_init(struct cal_ctx *ctx) csi2_cio_power(ctx, true); } -static void csi2_wait_for_phy(struct cal_ctx *ctx) +static void csi2_wait_complexio_reset(struct cal_ctx *ctx) { int i; - /* Steps - * 2. Wait for completion of reset - * Note if the external sensor is not sending byte clock, - * the reset will timeout - * 4.Force FORCERXMODE - * G. Wait for all enabled lane to reach stop state - * H. Disable pull down using pad control - */ - - /* 2. Wait for reset completion */ for (i = 0; i < 250; i++) { if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), @@ -855,7 +845,12 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx) CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED) ctx_err(ctx, "Timeout waiting for Complex IO reset done\n"); - /* 4. G. Wait for all enabled lane to reach stop state */ +} + +static void csi2_wait_stop_state(struct cal_ctx *ctx) +{ + int i; + for (i = 0; i < 10; i++) { if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), @@ -867,9 +862,28 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx) ctx->csi2_port, reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)), (i >= 10) ? "(timeout)" : ""); + if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0) ctx_err(ctx, "Timeout waiting for stop state\n"); +} + +static void csi2_wait_for_phy(struct cal_ctx *ctx) +{ + /* Steps + * 2. Wait for completion of reset + * Note if the external sensor is not sending byte clock, + * the reset will timeout + * 4.Force FORCERXMODE + * G. Wait for all enabled lane to reach stop state + * H. Disable pull down using pad control + */ + + /* 2. Wait for reset completion */ + csi2_wait_complexio_reset(ctx); + + /* 4. G. Wait for all enabled lane to reach stop state */ + csi2_wait_stop_state(ctx); ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x (Bit(31,28) should be set!)\n", (ctx->csi2_port - 1), reg_read(ctx->cc, CAL_CSI2_PHY_REG1)); From patchwork Thu Mar 19 07:50:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446615 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1280C13B1 for ; Thu, 19 Mar 2020 07:51:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E713220724 for ; Thu, 19 Mar 2020 07:51:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="BszZPuDI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726983AbgCSHvJ (ORCPT ); Thu, 19 Mar 2020 03:51:09 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:52710 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726905AbgCSHvI (ORCPT ); Thu, 19 Mar 2020 03:51:08 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7p5tT083789; Thu, 19 Mar 2020 02:51:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604266; bh=Q+QFukMwNhwDN3SHaEzSg2QOCbg9qA17WjnFw9ZuQz8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BszZPuDIrSxduKPFD7B1Wwasly6tL/hYVRmJ53C4VqlV04WwSkmFmvHQsZbSVhmaJ 8+mUQ+vsPXKy0FwtVARJXrJ0rF7d0BcsjUTJ0yKZAezV2ioSQ35DFupAW9vV5yzI7+ DYiUbw1vQp0URqMaVxlhnQPgfVfD5nm96EIOt8Wo= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7p5N1036611 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:51:05 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:51:05 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:51:05 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqu047151; Thu, 19 Mar 2020 02:51:04 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 17/19] media: ti-vpe: cal: improve wait for CIO resetdone Date: Thu, 19 Mar 2020 09:50:21 +0200 Message-ID: <20200319075023.22151-18-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Sometimes there is a timeout when waiting for the 'ComplexIO Reset Done'. Testing shows that sometimes we need to wait more than what the current code does. It is not clear how long this wait can be, but it is based on how quickly the sensor provides a valid clock, and how quickly CAL syncs to it. Change the code to make it more obvious how long we'll wait, and set a wider range for usleep_range. Increase the timeout to 750ms. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index ed68ad58121e..0dc7892881e7 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -825,20 +825,17 @@ static void csi2_phy_init(struct cal_ctx *ctx) static void csi2_wait_complexio_reset(struct cal_ctx *ctx) { - int i; + unsigned long timeout; - for (i = 0; i < 250; i++) { + timeout = jiffies + msecs_to_jiffies(750); + while (time_before(jiffies, timeout)) { if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) == CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED) break; - usleep_range(1000, 1100); + usleep_range(500, 5000); } - ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done (%d) %s\n", - ctx->csi2_port, - reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i, - (i >= 250) ? "(timeout)" : ""); if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) != From patchwork Thu Mar 19 07:50:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446617 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 825DA13B1 for ; Thu, 19 Mar 2020 07:51:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6358F2072C for ; Thu, 19 Mar 2020 07:51:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ldsKJl9P" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726986AbgCSHvL (ORCPT ); Thu, 19 Mar 2020 03:51:11 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33334 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726462AbgCSHvK (ORCPT ); Thu, 19 Mar 2020 03:51:10 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7p8Ru114236; Thu, 19 Mar 2020 02:51:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604268; bh=jdWXGCtwSJlVPHlp6NdT3+malgYS6cXlA0SFsXGKnXc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ldsKJl9PNtg70IorETpnqdEKZLfetOLJtfYrDLNg2LPjkT7QQmwTq88F8/UmYfdGv PiHHEF9Nkpw4PkEShl0hZJI2ak+Rhm9OyVM+Bbqd6BNAx0vETiYfe1JcPelJdwkPHZ OqZ3r1nLNgOeIWfJQo9qXvDWJIa5ZirXJS9CppgU= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7p7Ks130385 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:51:08 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:51:07 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:51:07 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqv047151; Thu, 19 Mar 2020 02:51:06 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 18/19] media: ti-vpe: cal: improve wait for stop-state Date: Thu, 19 Mar 2020 09:50:22 +0200 Message-ID: <20200319075023.22151-19-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Sometimes there is a timeout when waiting for the Stop-State. Testing shows that sometimes we need to wait more than what the current code does. It is not clear how long this wait can be, but it is based on how quickly the sensor provides a valid clock, and how quickly CAL syncs to it. Change the code to make it more obvious how long we'll wait, and set a wider range for usleep_range. Increase the timeout to 750ms. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 0dc7892881e7..0f90078ee8c2 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -846,19 +846,16 @@ static void csi2_wait_complexio_reset(struct cal_ctx *ctx) static void csi2_wait_stop_state(struct cal_ctx *ctx) { - int i; + unsigned long timeout; - for (i = 0; i < 10; i++) { + timeout = jiffies + msecs_to_jiffies(750); + while (time_before(jiffies, timeout)) { if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0) break; - usleep_range(1000, 1100); + usleep_range(500, 5000); } - ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Stop State Reached %s\n", - ctx->csi2_port, - reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)), - (i >= 10) ? "(timeout)" : ""); if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0) From patchwork Thu Mar 19 07:50:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11446619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 55A36139A for ; Thu, 19 Mar 2020 07:51:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 35CCE20740 for ; Thu, 19 Mar 2020 07:51:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="IuULNwr8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726988AbgCSHvM (ORCPT ); Thu, 19 Mar 2020 03:51:12 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33340 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726462AbgCSHvM (ORCPT ); Thu, 19 Mar 2020 03:51:12 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02J7p9B8114243; Thu, 19 Mar 2020 02:51:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584604269; bh=p97UI6EDj7hgYrW1qXw0+zf9DM7cjNU4Hx4vrT+fQf4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IuULNwr8Mecx8ah915ZrO3LzNWSxY8oOt8RiqRDHztud6id4IlQNDWEqgRJOWVkij Yn6ArrSv8LEOMCs08po2hdRQttyYk+tN0CA6H2yg0ofJEtGXKWK4nGo13NVtXdXXbx z1kDi6k3PzGhv7qwD9EQrQR1S5mOSHZ8b7WGHUzQ= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02J7p9FL120356 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Mar 2020 02:51:09 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Mar 2020 02:51:09 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Mar 2020 02:51:09 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02J7oXqw047151; Thu, 19 Mar 2020 02:51:07 -0500 From: Tomi Valkeinen To: , Benoit Parrot CC: Mauro Carvalho Chehab , Laurent Pinchart , Hans Verkuil , Tomi Valkeinen Subject: [PATCH v2 19/19] media: ti-vpe: cal: fix stop state timeout Date: Thu, 19 Mar 2020 09:50:23 +0200 Message-ID: <20200319075023.22151-20-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200319075023.22151-1-tomi.valkeinen@ti.com> References: <20200319075023.22151-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The stop-state timeout needs to be over 100us as per CSI spec. With the CAL fclk of 266 MHZ on DRA76, with the current value the driver uses, the timeout is 24us. Too small timeout will cause failure to enable the streaming. Also, the fclk can be different on other SoCs, as is the case with AM65x where the fclk is 250 MHz. This patch fixes the timeout by calculating it correctly based on the fclk rate. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- drivers/media/platform/ti-vpe/cal.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 0f90078ee8c2..d935c628597b 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -6,6 +6,7 @@ * Benoit Parrot, */ +#include #include #include #include @@ -340,6 +341,7 @@ static const struct cal_data am654_cal_data = { * all instances. */ struct cal_dev { + struct clk *fclk; int irq; void __iomem *base; struct resource *res; @@ -767,6 +769,7 @@ static void csi2_phy_config(struct cal_ctx *ctx); static void csi2_phy_init(struct cal_ctx *ctx) { u32 val; + u32 sscounter; /* Steps * 1. Configure D-PHY mode and enable required lanes @@ -803,10 +806,20 @@ static void csi2_phy_init(struct cal_ctx *ctx) csi2_phy_config(ctx); /* 3.B. Program Stop States */ + /* + * The stop-state-counter is based on fclk cycles, and we always use + * the x16 and x4 settings, so stop-state-timeout = + * fclk-cycle * 16 * 4 * counter. + * + * Stop-state-timeout must be more than 100us as per CSI2 spec, so we + * calculate a timeout that's 100us (rounding up). + */ + sscounter = DIV_ROUND_UP(clk_get_rate(ctx->dev->fclk), 10000 * 16 * 4); + val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)); set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK); - set_field(&val, 0, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK); - set_field(&val, 407, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK); + set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK); + set_field(&val, sscounter, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK); reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val); ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n", ctx->csi2_port, @@ -2257,6 +2270,12 @@ static int cal_probe(struct platform_device *pdev) /* save pdev pointer */ dev->pdev = pdev; + dev->fclk = devm_clk_get(&pdev->dev, "fck"); + if (IS_ERR(dev->fclk)) { + dev_err(&pdev->dev, "cannot get CAL fclk\n"); + return PTR_ERR(dev->fclk); + } + syscon_camerrx = syscon_regmap_lookup_by_phandle(parent, "ti,camerrx-control"); ret = of_property_read_u32_index(parent, "ti,camerrx-control", 1,