From patchwork Thu Mar 19 10:20:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Bharadiya X-Patchwork-Id: 11446999 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C600692A for ; Thu, 19 Mar 2020 10:30:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AEC7920722 for ; Thu, 19 Mar 2020 10:30:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AEC7920722 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B1CA26E9E3; Thu, 19 Mar 2020 10:30:52 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0DE556E9E2; Thu, 19 Mar 2020 10:30:51 +0000 (UTC) IronPort-SDR: B8+zt+rdAlZ7cj/xMv80p373MuQqAfZstYbIagwoirExe3ltx0XzjnLW+si4PHUBgN0I7XkNSO 2Eus8VjXWLFg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2020 03:30:50 -0700 IronPort-SDR: eRNdOmkBiQ9YzlRHD6BlxNVPBHpUoYCU4vf9hVtTj14Rt+gxJJ1dWsWy1LOgmBgVPy4K0iAjIe D9ZMu3PmZDYw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,571,1574150400"; d="scan'208";a="263687076" Received: from plaxmina-desktop.iind.intel.com ([10.145.162.62]) by orsmga002.jf.intel.com with ESMTP; 19 Mar 2020 03:30:45 -0700 From: Pankaj Bharadiya To: sameer.lattannavar@intel.com, jani.nikula@linux.intel.com, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, ville.syrjala@linux.intel.com, daniels@collabora.com, Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie Subject: [PATCH v2 1/5] drm: Introduce plane and CRTC scaling filter properties Date: Thu, 19 Mar 2020 15:50:59 +0530 Message-Id: <20200319102103.28895-2-pankaj.laxminarayan.bharadiya@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> References: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pankaj.laxminarayan.bharadiya@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Introduce new plane and CRTC scaling filter properties to allow userspace to select the driver's default scaling filter or Nearest-neighbor(NN) filter for upscaling operations on CRTC and plane. Drivers can set up this property for a plane by calling drm_plane_enable_scaling_filter() and for a CRTC by calling drm_crtc_enable_scaling_filter(). NN filter works by filling in the missing color values in the upscaled image with that of the coordinate-mapped nearest source pixel value. NN filter for integer multiple scaling can be particularly useful for for pixel art games that rely on sharp, blocky images to deliver their distinctive look. changes since v1: * None changes since RFC: * Add separate properties for plane and CRTC (Ville) Signed-off-by: Shashank Sharma Signed-off-by: Ankit Nautiyal Signed-off-by: Pankaj Bharadiya --- drivers/gpu/drm/drm_atomic_uapi.c | 8 ++++++++ drivers/gpu/drm/drm_crtc.c | 33 +++++++++++++++++++++++++++++++ drivers/gpu/drm/drm_mode_config.c | 26 ++++++++++++++++++++++++ drivers/gpu/drm/drm_plane.c | 33 +++++++++++++++++++++++++++++++ include/drm/drm_crtc.h | 13 ++++++++++++ include/drm/drm_mode_config.h | 12 +++++++++++ include/drm/drm_plane.h | 13 ++++++++++++ 7 files changed, 138 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index a1e5e262bae2..3c72ab52ff62 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -435,6 +435,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, return ret; } else if (property == config->prop_vrr_enabled) { state->vrr_enabled = val; + } else if (property == config->crtc_scaling_filter_property) { + state->scaling_filter = val; } else if (property == config->degamma_lut_property) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->degamma_lut, @@ -503,6 +505,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; else if (property == config->prop_out_fence_ptr) *val = 0; + else if (property == config->crtc_scaling_filter_property) + *val = state->scaling_filter; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else @@ -583,6 +587,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, sizeof(struct drm_rect), &replaced); return ret; + } else if (property == config->plane_scaling_filter_property) { + state->scaling_filter = val; } else if (plane->funcs->atomic_set_property) { return plane->funcs->atomic_set_property(plane, state, property, val); @@ -641,6 +647,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane, } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; + } else if (property == config->plane_scaling_filter_property) { + *val = state->scaling_filter; } else if (plane->funcs->atomic_get_property) { return plane->funcs->atomic_get_property(plane, state, property, val); } else { diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 4936e1080e41..c8d387891dd5 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -748,3 +748,36 @@ int drm_mode_crtc_set_obj_prop(struct drm_mode_object *obj, return ret; } + +/** + * DOC: CRTC scaling filter property + * + * SCALING_FILTER: + * + * Indicates scaling filter to be used for CRTC scaler + * + * The value of this property can be one of the following: + * Default: + * Driver's default scaling filter + * Nearest Neighbor: + * Nearest Neighbor scaling filter + * + * Drivers can set up this property for a CRTC by calling + * drm_crtc_enable_scaling_filter() + */ + +/** + * drm_crtc_enable_scaling_filter - Enables CRTC scaling filter property. + * @crtc: CRTC on which to enable scaling filter property. + * + * This function lets driver to enable the scaling filter property on a CRTC. + */ +void drm_crtc_enable_scaling_filter(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + + drm_object_attach_property(&crtc->base, + dev->mode_config.crtc_scaling_filter_property, + 0); +} +EXPORT_SYMBOL(drm_crtc_enable_scaling_filter); diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index e1ec1bb7068d..483705581930 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -214,6 +214,16 @@ static const struct drm_prop_enum_list drm_plane_type_enum_list[] = { { DRM_PLANE_TYPE_CURSOR, "Cursor" }, }; +static const struct drm_prop_enum_list drm_crtc_scaling_filter_enum_list[] = { + { DRM_CRTC_SCALING_FILTER_DEFAULT, "Default" }, + { DRM_CRTC_SCALING_FILTER_NEAREST_NEIGHBOR, "Nearest Neighbor" }, +}; + +static const struct drm_prop_enum_list drm_plane_scaling_filter_enum_list[] = { + { DRM_PLANE_SCALING_FILTER_DEFAULT, "Default" }, + { DRM_PLANE_SCALING_FILTER_NEAREST_NEIGHBOR, "Nearest Neighbor" }, +}; + static int drm_mode_create_standard_properties(struct drm_device *dev) { struct drm_property *prop; @@ -370,6 +380,22 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.modifiers_property = prop; + prop = drm_property_create_enum(dev, 0, + "SCALING_FILTER", + drm_crtc_scaling_filter_enum_list, + ARRAY_SIZE(drm_crtc_scaling_filter_enum_list)); + if (!prop) + return -ENOMEM; + dev->mode_config.crtc_scaling_filter_property = prop; + + prop = drm_property_create_enum(dev, 0, + "SCALING_FILTER", + drm_plane_scaling_filter_enum_list, + ARRAY_SIZE(drm_plane_scaling_filter_enum_list)); + if (!prop) + return -ENOMEM; + dev->mode_config.plane_scaling_filter_property = prop; + return 0; } diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index d6ad60ab0d38..f71cf50a4ef9 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -1221,3 +1221,36 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev, return ret; } + +/** + * DOC: Plane scaling filter property + * + * SCALING_FILTER: + * + * Indicates scaling filter to be used for plane scaler + * + * The value of this property can be one of the following: + * Default: + * Driver's default scaling filter + * Nearest Neighbor: + * Nearest Neighbor scaling filter + * + * Drivers can set up this property for a plane by calling + * drm_plane_enable_scaling_filter() + */ + +/** + * drm_plane_enable_scaling_filter - Enables plane scaling filter property. + * @plane: Plane on which to enable scaling filter property. + * + * This function lets driver to enable the scaling filter property on a plane. + */ +void drm_plane_enable_scaling_filter(struct drm_plane *plane) +{ + struct drm_device *dev = plane->dev; + + drm_object_attach_property(&plane->base, + dev->mode_config.plane_scaling_filter_property, + 0); +} +EXPORT_SYMBOL(drm_plane_enable_scaling_filter); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 59b51a09cae6..3187df6874d4 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -76,6 +76,10 @@ struct drm_atomic_state; struct drm_crtc_helper_funcs; struct drm_plane_helper_funcs; +enum drm_crtc_scaling_filter { + DRM_CRTC_SCALING_FILTER_DEFAULT, + DRM_CRTC_SCALING_FILTER_NEAREST_NEIGHBOR, +}; /** * struct drm_crtc_state - mutable CRTC state * @@ -296,6 +300,13 @@ struct drm_crtc_state { */ u32 target_vblank; + /** + * @scaling_filter: + * + * Scaling filter mode to be applied + */ + enum drm_crtc_scaling_filter scaling_filter; + /** * @async_flip: * @@ -1266,4 +1277,6 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev, #define drm_for_each_crtc(crtc, dev) \ list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) +void drm_crtc_enable_scaling_filter(struct drm_crtc *crtc); + #endif /* __DRM_CRTC_H__ */ diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 3bcbe30339f0..2b394561359b 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -914,6 +914,18 @@ struct drm_mode_config { */ struct drm_property *modifiers_property; + /** + * @crtc_scaling_filter_property: CRTC property to apply a particular + * filter while scaling. + */ + struct drm_property *crtc_scaling_filter_property; + + /** + * @plane_scaling_filter_property: Plane property to apply a particular + * filter while scaling. + */ + struct drm_property *plane_scaling_filter_property; + /* cursor size */ uint32_t cursor_width, cursor_height; diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 3f396d94afe4..f75cee8c4ffa 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -35,6 +35,10 @@ struct drm_crtc; struct drm_printer; struct drm_modeset_acquire_ctx; +enum drm_plane_scaling_filter { + DRM_PLANE_SCALING_FILTER_DEFAULT, + DRM_PLANE_SCALING_FILTER_NEAREST_NEIGHBOR, +}; /** * struct drm_plane_state - mutable plane state * @@ -214,6 +218,13 @@ struct drm_plane_state { */ bool visible; + /** + * @scaling_filter: + * + * Scaling filter mode to be applied + */ + enum drm_plane_scaling_filter scaling_filter; + /** * @commit: Tracks the pending commit to prevent use-after-free conditions, * and for async plane updates. @@ -862,4 +873,6 @@ drm_plane_get_damage_clips(const struct drm_plane_state *state) state->fb_damage_clips->data : NULL); } +void drm_plane_enable_scaling_filter(struct drm_plane *plane); + #endif From patchwork Thu Mar 19 10:21:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Bharadiya X-Patchwork-Id: 11447001 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 66CD3913 for ; Thu, 19 Mar 2020 10:30:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4F7C920739 for ; Thu, 19 Mar 2020 10:30:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4F7C920739 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA6586E9E4; Thu, 19 Mar 2020 10:30:56 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 941206E9E4; Thu, 19 Mar 2020 10:30:55 +0000 (UTC) IronPort-SDR: BDW95vAe1OJ+RAMXW/8SjCOXbJr89ugMQcXkmOkNb5+sBVEnFTmLPMzo8Co2K1QMdMaohK+1eM ojbFoySdgceA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2020 03:30:55 -0700 IronPort-SDR: AssF+72ULaqNumOZPFRliT1O0dDfvZQ++Kf/bCPTQzfW7wnqmxIVpBQn8/4tZ6DpI4/9fU6u3P Po5+7aJ7ztSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,571,1574150400"; d="scan'208";a="263687098" Received: from plaxmina-desktop.iind.intel.com ([10.145.162.62]) by orsmga002.jf.intel.com with ESMTP; 19 Mar 2020 03:30:50 -0700 From: Pankaj Bharadiya To: sameer.lattannavar@intel.com, jani.nikula@linux.intel.com, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, ville.syrjala@linux.intel.com, daniels@collabora.com, David Airlie , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Subject: [PATCH v2 2/5] drm/drm-kms.rst: Add plane and CRTC scaling filter property documentation Date: Thu, 19 Mar 2020 15:51:00 +0530 Message-Id: <20200319102103.28895-3-pankaj.laxminarayan.bharadiya@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> References: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pankaj.laxminarayan.bharadiya@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add documentation for newly introduced KMS plane and CRTC scaling filter properties. changes since v1: * None changes since RFC: * Add separate documentation for plane and CRTC. Signed-off-by: Pankaj Bharadiya --- Documentation/gpu/drm-kms.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 906771e03103..b0335e9d887c 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -509,6 +509,18 @@ Variable Refresh Properties .. kernel-doc:: drivers/gpu/drm/drm_connector.c :doc: Variable refresh properties +Plane Scaling Filter Property +----------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_plane.c + :doc: Plane scaling filter property + +CRTC Scaling Filter Property +----------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_crtc.c + :doc: CRTC scaling filter property + Existing KMS Properties ----------------------- From patchwork Thu Mar 19 10:21:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Bharadiya X-Patchwork-Id: 11447005 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A490192A for ; Thu, 19 Mar 2020 10:31:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8D85420752 for ; Thu, 19 Mar 2020 10:31:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8D85420752 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B65026E9E5; Thu, 19 Mar 2020 10:31:02 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 79D266E9E5; Thu, 19 Mar 2020 10:31:01 +0000 (UTC) IronPort-SDR: C07zixydLjdKQiaC52bmvXcQ1k4s/ve0OF43vlVEm6zRTAhzXRNvzXa+3TI2f72H3x1dwhSj6x zmrzOTMcHPtQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2020 03:31:00 -0700 IronPort-SDR: 6WiRqcyaeNZTwkIhFBqtoBI0VziQdFjTjpP1kEOBqXeiPXEJEuluKUNhwxl/fsCoIHOU3ilUa2 0qUqGhURC3GA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,571,1574150400"; d="scan'208";a="263687115" Received: from plaxmina-desktop.iind.intel.com ([10.145.162.62]) by orsmga002.jf.intel.com with ESMTP; 19 Mar 2020 03:30:55 -0700 From: Pankaj Bharadiya To: sameer.lattannavar@intel.com, jani.nikula@linux.intel.com, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, ville.syrjala@linux.intel.com, daniels@collabora.com, Joonas Lahtinen , Rodrigo Vivi , David Airlie Subject: [PATCH v2 3/5] drm/i915: Introduce scaling filter related registers and bit fields. Date: Thu, 19 Mar 2020 15:51:01 +0530 Message-Id: <20200319102103.28895-4-pankaj.laxminarayan.bharadiya@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> References: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pankaj.laxminarayan.bharadiya@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Introduce scaler registers and bit fields needed to configure the scaling filter in prgrammed mode and configure scaling filter coefficients. changes since v1: * None changes since RFC: * Parametrize scaler coeffient macros by 'set' (Ville) Signed-off-by: Shashank Sharma Signed-off-by: Ankit Nautiyal Signed-off-by: Pankaj Bharadiya --- drivers/gpu/drm/i915/i915_reg.h | 48 +++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9c53fe918be6..d40f12d2a6b5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7205,6 +7205,7 @@ enum { #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) #define PS_FILTER_MASK (3 << 23) #define PS_FILTER_MEDIUM (0 << 23) +#define PS_FILTER_PROGRAMMED (1 << 23) #define PS_FILTER_EDGE_ENHANCE (2 << 23) #define PS_FILTER_BILINEAR (3 << 23) #define PS_VERT3TAP (1 << 21) @@ -7219,6 +7220,10 @@ enum { #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) #define PS_PLANE_Y_SEL_MASK (7 << 5) #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) +#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4) +#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3) +#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2) +#define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1) #define _PS_PWR_GATE_1A 0x68160 #define _PS_PWR_GATE_2A 0x68260 @@ -7281,6 +7286,25 @@ enum { #define _PS_ECC_STAT_2B 0x68AD0 #define _PS_ECC_STAT_1C 0x691D0 +#define _PS_COEF_SET0_INDEX_1A 0x68198 +#define _PS_COEF_SET0_INDEX_2A 0x68298 +#define _PS_COEF_SET0_INDEX_1B 0x68998 +#define _PS_COEF_SET0_INDEX_2B 0x68A98 +#define _PS_COEF_SET1_INDEX_1A 0x681A0 +#define _PS_COEF_SET1_INDEX_2A 0x682A0 +#define _PS_COEF_SET1_INDEX_1B 0x689A0 +#define _PS_COEF_SET1_INDEX_2B 0x68AA0 +#define PS_COEE_INDEX_AUTO_INC (1 << 10) + +#define _PS_COEF_SET0_DATA_1A 0x6819C +#define _PS_COEF_SET0_DATA_2A 0x6829C +#define _PS_COEF_SET0_DATA_1B 0x6899C +#define _PS_COEF_SET0_DATA_2B 0x68A9C +#define _PS_COEF_SET1_DATA_1A 0x681A4 +#define _PS_COEF_SET1_DATA_2A 0x682A4 +#define _PS_COEF_SET1_DATA_1B 0x689A4 +#define _PS_COEF_SET1_DATA_2B 0x68AA4 + #define _ID(id, a, b) _PICK_EVEN(id, a, b) #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ @@ -7310,6 +7334,30 @@ enum { _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) +#define _SKL_PS_COEF_INDEX_SET0(pipe, id) _ID(pipe, \ + _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A), \ + _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B)) + +#define _SKL_PS_COEF_INDEX_SET1(pipe, id) _ID(pipe, \ + _ID(id, _PS_COEF_SET1_INDEX_1A, _PS_COEF_SET1_INDEX_2A), \ + _ID(id, _PS_COEF_SET1_INDEX_1B, _PS_COEF_SET1_INDEX_2B)) + +#define _SKL_PS_COEF_DATA_SET0(pipe, id) _ID(pipe, \ + _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A), \ + _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B)) + +#define _SKL_PS_COEF_DATA_SET1(pipe, id) _ID(pipe, \ + _ID(id, _PS_COEF_SET1_DATA_1A, _PS_COEF_SET1_DATA_2A), \ + _ID(id, _PS_COEF_SET1_DATA_1B, _PS_COEF_SET1_DATA_2B)) + +#define SKL_PS_COEF_INDEX_SET(pipe, id, set) \ + _MMIO_PIPE(set, _SKL_PS_COEF_INDEX_SET0(pipe, id), \ + _SKL_PS_COEF_INDEX_SET1(pipe, id)) + +#define SKL_PS_COEF_DATA_SET(pipe, id, set) \ + _MMIO_PIPE(set, _SKL_PS_COEF_DATA_SET0(pipe, id), \ + _SKL_PS_COEF_DATA_SET1(pipe, id)) + /* legacy palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 From patchwork Thu Mar 19 10:21:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Bharadiya X-Patchwork-Id: 11447013 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E27492A for ; Thu, 19 Mar 2020 10:31:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 071F120722 for ; Thu, 19 Mar 2020 10:31:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 071F120722 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C8DCD6E9E6; Thu, 19 Mar 2020 10:31:13 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id B6F906E9E6; Thu, 19 Mar 2020 10:31:11 +0000 (UTC) IronPort-SDR: pClGOHzgxCuJL7XbDGrnHpRE91peQ5ZNcP53FpbGImkxVJnvKcCv777n8YdGfDr7rHlYb1CQ01 9gr4RYogOMkA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2020 03:31:11 -0700 IronPort-SDR: oov1QraYWCiBK/QdrelOp4g/Kb/A0K4lUWvUbUg+od/PBloLmSQtsxeMZqwN0T0BJxTaC37cK/ aMW9gkOdpYww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,571,1574150400"; d="scan'208";a="263687168" Received: from plaxmina-desktop.iind.intel.com ([10.145.162.62]) by orsmga002.jf.intel.com with ESMTP; 19 Mar 2020 03:31:04 -0700 From: Pankaj Bharadiya To: sameer.lattannavar@intel.com, jani.nikula@linux.intel.com, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, ville.syrjala@linux.intel.com, daniels@collabora.com, Joonas Lahtinen , Rodrigo Vivi , David Airlie , Chris Wilson , Maarten Lankhorst , =?utf-8?q?Jos=C3=A9_?= =?utf-8?q?Roberto_de_Souza?= , Imre Deak , Lucas De Marchi , Matt Roper Subject: [PATCH v2 4/5] drm/i915/display: Add Nearest-neighbor based integer scaling support Date: Thu, 19 Mar 2020 15:51:02 +0530 Message-Id: <20200319102103.28895-5-pankaj.laxminarayan.bharadiya@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> References: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pankaj.laxminarayan.bharadiya@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Integer scaling (IS) is a nearest-neighbor upscaling technique that simply scales up the existing pixels by an integer (i.e., whole number) multiplier.Nearest-neighbor (NN) interpolation works by filling in the missing color values in the upscaled image with that of the coordinate-mapped nearest source pixel value. Both IS and NN preserve the clarity of the original image. Integer scaling is particularly useful for pixel art games that rely on sharp, blocky images to deliver their distinctive look. Introduce skl_scaler_setup_nearest_neighbor_filter() function which configures the scaler filter coefficients to enable nearest-neighbor filtering. Bspec: 49247 changes since v1: * Rearrange skl_scaler_setup_nearest_neighbor_filter() to iterate the registers directly instead of the phases and taps (Ville) changes since RFC: * Refine the skl_scaler_setup_nearest_neighbor_filter() logic (Ville) Signed-off-by: Shashank Sharma Signed-off-by: Ankit Nautiyal Signed-off-by: Pankaj Bharadiya --- drivers/gpu/drm/i915/display/intel_display.c | 72 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.h | 2 + 2 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 8f23c4d51c33..791dd908aa89 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6237,6 +6237,78 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) skl_detach_scaler(crtc, i); } +static int skl_coef_tap(int i) +{ + return i % 7; +} + +static u16 skl_nearest_filter_coef(int t) +{ + return t == 3 ? 0x0800 : 0x3000; +} + +/** + * Theory behind setting nearest-neighbor integer scaling: + * + * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set. + * The letter represents the filter tap (D is the center tap) and the number + * represents the coefficient set for a phase (0-16). + * + * +------------+------------------------+------------------------+ + * |Index value | Data value coeffient 1 | Data value coeffient 2 | + * +------------+------------------------+------------------------+ + * | 00h | B0 | A0 | + * +------------+------------------------+------------------------+ + * | 01h | D0 | C0 | + * +------------+------------------------+------------------------+ + * | 02h | F0 | E0 | + * +------------+------------------------+------------------------+ + * | 03h | A1 | G0 | + * +------------+------------------------+------------------------+ + * | 04h | C1 | B1 | + * +------------+------------------------+------------------------+ + * | ... | ... | ... | + * +------------+------------------------+------------------------+ + * | 38h | B16 | A16 | + * +------------+------------------------+------------------------+ + * | 39h | D16 | C16 | + * +------------+------------------------+------------------------+ + * | 3Ah | F16 | C16 | + * +------------+------------------------+------------------------+ + * | 3Bh | Reserved | G16 | + * +------------+------------------------+------------------------+ + * + * To enable nearest-neighbor scaling: program scaler coefficents with + * the center tap (Dxx) values set to 1 and all other values set to 0 as per + * SCALER_COEFFICIENT_FORMAT + * + */ + +void skl_scaler_setup_nearest_neighbor_filter(struct drm_i915_private *dev_priv, + enum pipe pipe, int id, int set) +{ + int i; + + /*enable the index auto increment.*/ + intel_de_write_fw(dev_priv, + SKL_PS_COEF_INDEX_SET(pipe, id, set), + PS_COEE_INDEX_AUTO_INC); + + for (i = 0; i < 17 * 7; i += 2) { + u32 tmp; + int t; + + t = skl_coef_tap(i); + tmp = skl_nearest_filter_coef(t); + + t = skl_coef_tap(i+1); + tmp |= skl_nearest_filter_coef(t)<<16; + + intel_de_write_fw(dev_priv, SKL_PS_COEF_DATA_SET(pipe, id, set), + tmp); + } +} + static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index adb1225a3480..88f3c77f6806 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -587,6 +587,8 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); +void skl_scaler_setup_nearest_neighbor_filter(struct drm_i915_private *dev_priv, + enum pipe pipe, int id, int set); void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); From patchwork Thu Mar 19 10:21:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Bharadiya X-Patchwork-Id: 11447017 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C738913 for ; Thu, 19 Mar 2020 10:31:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5483620722 for ; Thu, 19 Mar 2020 10:31:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5483620722 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E6626E9ED; Thu, 19 Mar 2020 10:31:24 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35E966E9EB; Thu, 19 Mar 2020 10:31:22 +0000 (UTC) IronPort-SDR: Dk+KQPi2u6T/SACnIaliriMpBYJTQBb0AwfUkBv7mpAzmN6tApN/UtVxXWvoz4NHsVT/rB926+ fxBtFlHMEXGg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2020 03:31:21 -0700 IronPort-SDR: 2yAgaLiSalpvvuCVrGpew6siNmtzlE5IqF5XykfZlWaW0dWmXrZTn2DEE8PM1bW2PuMZElqFKw KFxFk/aK2q7Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,571,1574150400"; d="scan'208";a="263687200" Received: from plaxmina-desktop.iind.intel.com ([10.145.162.62]) by orsmga002.jf.intel.com with ESMTP; 19 Mar 2020 03:31:15 -0700 From: Pankaj Bharadiya To: sameer.lattannavar@intel.com, jani.nikula@linux.intel.com, daniel@ffwll.ch, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, ville.syrjala@linux.intel.com, daniels@collabora.com, Joonas Lahtinen , Rodrigo Vivi , David Airlie , Chris Wilson , Maarten Lankhorst , =?utf-8?q?Jos=C3=A9_?= =?utf-8?q?Roberto_de_Souza?= , Imre Deak , Uma Shankar Subject: [PATCH v2 5/5] drm/i915: Enable scaling filter for plane and CRTC Date: Thu, 19 Mar 2020 15:51:03 +0530 Message-Id: <20200319102103.28895-6-pankaj.laxminarayan.bharadiya@intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> References: <20200319102103.28895-1-pankaj.laxminarayan.bharadiya@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pankaj.laxminarayan.bharadiya@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" GEN >= 10 hardware supports the programmable scaler filter. Attach scaling filter property for CRTC and plane for GEN >= 10 hardwares and program scaler filter based on the selected filter type. changes since v1: * None Changes since RFC: * Enable properties for GEN >= 10 platforms (Ville) * Do not round off the crtc co-ordinate (Danial Stone, Ville) * Add new functions to handle scaling filter setup (Ville) * Remove coefficient set 0 hardcoding. Signed-off-by: Shashank Sharma Signed-off-by: Ankit Nautiyal Signed-off-by: Pankaj Bharadiya --- drivers/gpu/drm/i915/display/intel_display.c | 32 ++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_sprite.c | 31 ++++++++++++++++++- 2 files changed, 60 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 791dd908aa89..4b3387ee332e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6309,6 +6309,25 @@ void skl_scaler_setup_nearest_neighbor_filter(struct drm_i915_private *dev_priv, } } +static u32 +skl_scaler_crtc_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe, + int id, int set, enum drm_crtc_scaling_filter filter) +{ + u32 scaler_filter_ctl = PS_FILTER_MEDIUM; + + if (filter == DRM_CRTC_SCALING_FILTER_NEAREST_NEIGHBOR) { + skl_scaler_setup_nearest_neighbor_filter(dev_priv, pipe, id, + set); + scaler_filter_ctl = PS_FILTER_PROGRAMMED | + PS_UV_VERT_FILTER_SELECT(set) | + PS_UV_HORZ_FILTER_SELECT(set) | + PS_Y_VERT_FILTER_SELECT(set) | + PS_Y_HORZ_FILTER_SELECT(set); + + } + return scaler_filter_ctl; +} + static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -6316,12 +6335,14 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; + const struct drm_crtc_state *state = &crtc_state->uapi; if (crtc_state->pch_pfit.enabled) { u16 uv_rgb_hphase, uv_rgb_vphase; int pfit_w, pfit_h, hscale, vscale; unsigned long irqflags; int id; + int scaler_filter_ctl; if (drm_WARN_ON(&dev_priv->drm, crtc_state->scaler_state.scaler_id < 0)) @@ -6340,8 +6361,12 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN | - PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); + scaler_filter_ctl = + skl_scaler_crtc_setup_filter(dev_priv, pipe, id, 0, + state->scaling_filter); + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), + PS_SCALER_EN | scaler_filter_ctl | + scaler_state->scalers[id].mode); intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), @@ -16777,6 +16802,9 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc; } + if (INTEL_GEN(dev_priv) >= 10) + drm_crtc_enable_scaling_filter(&crtc->base); + intel_color_init(crtc); intel_crtc_crc_init(crtc); diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index deda351719db..ac3fd9843ace 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -395,6 +395,26 @@ skl_plane_max_stride(struct intel_plane *plane, return min(8192 * cpp, 32768); } +static u32 +skl_scaler_plane_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe, + int id, int set, + enum drm_plane_scaling_filter filter) +{ + u32 scaler_filter_ctl = PS_FILTER_MEDIUM; + + if (filter == DRM_PLANE_SCALING_FILTER_NEAREST_NEIGHBOR) { + skl_scaler_setup_nearest_neighbor_filter(dev_priv, pipe, id, + set); + scaler_filter_ctl = PS_FILTER_PROGRAMMED | + PS_UV_VERT_FILTER_SELECT(set) | + PS_UV_HORZ_FILTER_SELECT(set) | + PS_Y_VERT_FILTER_SELECT(set) | + PS_Y_HORZ_FILTER_SELECT(set); + + } + return scaler_filter_ctl; +} + static void skl_program_scaler(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, @@ -406,6 +426,7 @@ skl_program_scaler(struct intel_plane *plane, int scaler_id = plane_state->scaler_id; const struct intel_scaler *scaler = &crtc_state->scaler_state.scalers[scaler_id]; + const struct drm_plane_state *state = &plane_state->uapi; int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); @@ -413,6 +434,7 @@ skl_program_scaler(struct intel_plane *plane, u16 y_hphase, uv_rgb_hphase; u16 y_vphase, uv_rgb_vphase; int hscale, vscale; + int scaler_filter_ctl; hscale = drm_rect_calc_hscale(&plane_state->uapi.src, &plane_state->uapi.dst, @@ -439,8 +461,12 @@ skl_program_scaler(struct intel_plane *plane, uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); } + scaler_filter_ctl = + skl_scaler_plane_setup_filter(dev_priv, pipe, scaler_id, 0, + state->scaling_filter); intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), - PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); + PS_SCALER_EN | PS_PLANE_SEL(plane->id) | + scaler->mode | scaler_filter_ctl); intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), @@ -3121,6 +3147,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, drm_plane_create_zpos_immutable_property(&plane->base, plane_id); + if (INTEL_GEN(dev_priv) >= 10) + drm_plane_enable_scaling_filter(&plane->base); + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); return plane;