From patchwork Thu Mar 19 19:02:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447859 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10D361874 for ; Thu, 19 Mar 2020 19:04:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DAB9B20739 for ; Thu, 19 Mar 2020 19:04:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ECmU0Xxw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727467AbgCSTEM (ORCPT ); Thu, 19 Mar 2020 15:04:12 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:37153 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726934AbgCSTEL (ORCPT ); Thu, 19 Mar 2020 15:04:11 -0400 Received: by mail-lj1-f196.google.com with SMTP id r24so3795425ljd.4; Thu, 19 Mar 2020 12:04:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YgrnrQFFVJkPVyCPGIj1GI9WnQxmQkvq9NhOsXcVAbA=; b=ECmU0XxwXSI70KKvGsy7SSWOxzjVDigZIS1zhCHmoCSkkdBerok36Zcp4jtQmcR+Ke fE5c6sAJsAeF9G9h2eu6iYLf+1VlgZqGjur9GmTFxbjLXs7OLBmuhmbw2bvN3hglP4rO 3oevNoiqXZZnsd3AoaMQugcqvQAaP/f0EnfGjkuj4W8qZ7S05pqq7JCN1ba81DNpJ2Q5 7zfUXpTeCWxHp4frDgUyYKyL294trJRLa0XMLeIRfU2hvozlojdLbZ6oEZBSpUipc353 U7dUPrZI2dw43SxZGAMftIUabAKENwqx+1eU1bC/AJyYt48hAP3KBAwxRWGJN4GtfTLh 7oSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YgrnrQFFVJkPVyCPGIj1GI9WnQxmQkvq9NhOsXcVAbA=; b=ftbUak+TNu/uxT/rmQgkebfrJfRernlW/ET23mFNk3gWKf9j9788vZCkKEmbOs2fka 5aE4nPwQFpbEJHotw5b5Ob4C8Gx9E2ef+BJXfh4f2Zk0ptmtsRln7TdqWyJy0cE3VlDf v1S+nBwq+apU9nHYS52GC5DQNs4lq2MPpTR6ZbURR0PMMinpQWnot4jE6ZCjv30irNES FA5OeK3/SsD2p7z/IJV+l7N9HEatCNE8JEzU+bDd7dFvFN9yUdYstbTx+TRFCEJJAg9E V3ZcU1LvfMXvg1zPIKuURAOoOzDqo++fNL416rL2HojMC2zgdsgkycf3IeN8ppMPJDns z0Ww== X-Gm-Message-State: ANhLgQ3JluWDDPgvHytyIkPMHVJc+1WbH+e71dBFOgDgvIXd+/ArGai4 uDjsqbVQMvzIKYpa+peAgsY= X-Google-Smtp-Source: ADFU+vt9o2I9V5Jq3wL1CSCXlsfMz7TrD6NEUChGGTN0MHJ0/uTmJjEiwtBKzYdg0LCyCHfXRWh4Zg== X-Received: by 2002:a2e:a312:: with SMTP id l18mr3087159lje.229.1584644647907; Thu, 19 Mar 2020 12:04:07 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:07 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 01/12] clk: tegra: Add custom CCLK implementation Date: Thu, 19 Mar 2020 22:02:18 +0300 Message-Id: <20200319190229.32200-2-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK. This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver. Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-tegra-super-cclk.c | 178 +++++++++++++++++++++++ drivers/clk/tegra/clk.h | 11 +- 3 files changed, 188 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 1f7c30f87ece..0bb4a5f23fcb 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -13,6 +13,7 @@ obj-y += clk-super.o obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o obj-y += clk-tegra-fixed.o +obj-y += clk-tegra-super-cclk.o obj-y += clk-tegra-super-gen4.o obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c new file mode 100644 index 000000000000..7bcb9e8d0860 --- /dev/null +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on clk-super.c + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Based on older tegra20-cpufreq driver by Colin Cross + * Copyright (C) 2010 Google, Inc. + * + * Author: Dmitry Osipenko + * Copyright (C) 2019 GRATE-DRIVER project + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define PLLP_INDEX 4 +#define PLLX_INDEX 8 + +#define SUPER_CDIV_ENB BIT(31) + +static u8 cclk_super_get_parent(struct clk_hw *hw) +{ + return tegra_clk_super_ops.get_parent(hw); +} + +static int cclk_super_set_parent(struct clk_hw *hw, u8 index) +{ + return tegra_clk_super_ops.set_parent(hw, index); +} + +static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); +} + +static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + if (cclk_super_get_parent(hw) == PLLX_INDEX) + return parent_rate; + + return tegra_clk_super_ops.recalc_rate(hw, parent_rate); +} + +static int cclk_super_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *pllp_hw = clk_hw_get_parent_by_index(hw, PLLP_INDEX); + struct clk_hw *pllx_hw = clk_hw_get_parent_by_index(hw, PLLX_INDEX); + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + unsigned long pllp_rate; + long rate = req->rate; + + if (WARN_ON_ONCE(!pllp_hw || !pllx_hw)) + return -EINVAL; + + /* + * Switch parent to PLLP for all CCLK rates that are suitable for PLLP. + * PLLX will be disabled in this case, saving some power. + */ + pllp_rate = clk_hw_get_rate(pllp_hw); + + if (rate <= pllp_rate) { + if (super->flags & TEGRA20_SUPER_CLK) + rate = pllp_rate; + else + rate = tegra_clk_super_ops.round_rate(hw, rate, + &pllp_rate); + + req->best_parent_rate = pllp_rate; + req->best_parent_hw = pllp_hw; + req->rate = rate; + } else { + rate = clk_hw_round_rate(pllx_hw, rate); + req->best_parent_rate = rate; + req->best_parent_hw = pllx_hw; + req->rate = rate; + } + + if (WARN_ON_ONCE(rate <= 0)) + return -EINVAL; + + return 0; +} + +static const struct clk_ops tegra_cclk_super_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .set_rate = cclk_super_set_rate, + .recalc_rate = cclk_super_recalc_rate, + .determine_rate = cclk_super_determine_rate, +}; + +static const struct clk_ops tegra_cclk_super_mux_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .determine_rate = cclk_super_determine_rate, +}; + +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock) +{ + struct tegra_clk_super_mux *super; + struct clk *clk; + struct clk_init_data init; + u32 val; + + super = kzalloc(sizeof(*super), GFP_KERNEL); + if (!super) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.parent_names = parent_names; + init.num_parents = num_parents; + + super->reg = reg; + super->lock = lock; + super->width = 4; + super->flags = clk_super_flags; + super->hw.init = &init; + + if (super->flags & TEGRA20_SUPER_CLK) { + init.ops = &tegra_cclk_super_mux_ops; + } else { + init.ops = &tegra_cclk_super_ops; + + super->frac_div.reg = reg + 4; + super->frac_div.shift = 16; + super->frac_div.width = 8; + super->frac_div.frac_width = 1; + super->frac_div.lock = lock; + super->div_ops = &tegra_clk_frac_div_ops; + } + + /* + * Tegra30+ has the following CPUG clock topology: + * + * +---+ +-------+ +-+ +-+ +-+ + * PLLP+->+ +->+DIVIDER+->+0| +-------->+0| ------------->+0| + * | | +-------+ | | | +---+ | | | | | + * PLLC+->+MUX| | +->+ | S | | +->+ | +->+CPU + * ... | | | | | | K | | | | +-------+ | | + * PLLX+->+-->+------------>+1| +->+ I +->+1| +->+ DIV2 +->+1| + * +---+ +++ | P | +++ |SKIPPER| +++ + * ^ | P | ^ +-------+ ^ + * | | E | | | + * PLLX_SEL+--+ | R | | OVERHEAT+--+ + * +---+ | + * | + * SUPER_CDIV_ENB+--+ + * + * Tegra20 is similar, but simpler. It doesn't have the divider and + * thermal DIV2 skipper. + * + * At least for now we're not going to use clock-skipper, hence let's + * ensure that it is disabled. + */ + val = readl_relaxed(reg + 4); + val &= ~SUPER_CDIV_ENB; + writel_relaxed(val, reg + 4); + + clk = clk_register(NULL, &super->hw); + if (IS_ERR(clk)) + kfree(super); + + return clk; +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 2c9a68302e02..412d4b47ecfd 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -729,8 +729,10 @@ struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates * that this is LP cluster clock. * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5 - * super mux parent using PLLP branches. To use PLLP branches to CPU, need - * to configure additional bit PLLP_OUT_CPU in the clock registers. + * super mux parent using PLLP branches. To use PLLP branches to CPU, need + * to configure additional bit PLLP_OUT_CPU in the clock registers. + * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super + * clocks, it only has a clock-skipper. */ struct tegra_clk_super_mux { struct clk_hw hw; @@ -748,6 +750,7 @@ struct tegra_clk_super_mux { #define TEGRA_DIVIDER_2 BIT(0) #define TEGRA210_CPU_CLK BIT(1) +#define TEGRA20_SUPER_CLK BIT(2) extern const struct clk_ops tegra_clk_super_ops; struct clk *tegra_clk_register_super_mux(const char *name, @@ -758,6 +761,10 @@ struct clk *tegra_clk_register_super_clk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Thu Mar 19 19:02:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447861 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 451CE1894 for ; Thu, 19 Mar 2020 19:04:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1AABD20739 for ; Thu, 19 Mar 2020 19:04:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hdZiJC4z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727540AbgCSTEP (ORCPT ); Thu, 19 Mar 2020 15:04:15 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:38170 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726589AbgCSTEM (ORCPT ); Thu, 19 Mar 2020 15:04:12 -0400 Received: by mail-lf1-f67.google.com with SMTP id n13so2575483lfh.5; Thu, 19 Mar 2020 12:04:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AlGN/9KxfqGP1gha8cnpAV1qjiffCVac50q6n9Lx2fc=; b=hdZiJC4z0SdQqSyWftZwUgVtGcjthk7l45qSR1wQTB9u37zfMyrwHIx5GlsSx57aLs 0/RU9gjAKCJipg32LTOoe7jX1MYQ3m0KR7IHp5sz8cwbI7TMsSeHDHDkGVVnAqiJD6nO mfEJILqQ4G2BpCOnwLEIXbzYjl2FeVGpkwmPSnkQNRxUybXap2Si5WpBgIxXwoBIeAUA iJaa8SzoCu4wY4Ak2F5kL/8yaRo1G+v7BcW0rdcRKEmkNGcfRjqxLo0Zr+zkeGU3LvlP wx3Rw9lbhv+fTstB2uF8xRam24n5N9AaQNCDAz9oK91qo4QvyFgU5msjGp+BwBtV1PSV YhpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AlGN/9KxfqGP1gha8cnpAV1qjiffCVac50q6n9Lx2fc=; b=P6t3ooIo2HN3hIP+l5RTr65n3M/cEdMOOdlHNBe5XKPh/XlbHEHUkLYFFPZ5VdgGNY iEAtGOsHSlzzkD/uwMOdfwhqPGTjCAtSwZvE4JezV2t/ODAYNN6XRMGgrUSszkVeXfEd OCAjPpQAyBIRyldTcgZp53tz2f8/3Zr1bOQdTCU6JUx/UtsSJqbcTPedTxo3o4Stcwi6 f5oVG8eiRaWQTTpnZgKwm0PxCIO8ycfxbVUVq4UtNZCNMLOdjhiRPtQ188e4pOALEIxR uu2nuEI8e9PiFuv7R+0OwBO9eV8QjtiIvisFVUtNywg2f20BykuGyoXJz8gbLMWdqS9E 37rw== X-Gm-Message-State: ANhLgQ0wuS+iJYT5KzCLtbuXtU+BuCq2AYHey4b8114YFMzrz8TkG3XM w2grvQX2RGdui9EkpdS3ZYg= X-Google-Smtp-Source: ADFU+vt1ZXbG+Xg7AuEkHJu+k3N6+eh1nkUz9bxUj9O/sc9v+WC6JGwJKZXoUTupdzN3gYl+JvVjtQ== X-Received: by 2002:ac2:4145:: with SMTP id c5mr3009914lfi.19.1584644649164; Thu, 19 Mar 2020 12:04:09 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:08 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 02/12] clk: tegra: pll: Add pre/post rate-change hooks Date: Thu, 19 Mar 2020 22:02:19 +0300 Message-Id: <20200319190229.32200-3-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org There is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-pll.c | 12 +++++++++++- drivers/clk/tegra/clk.h | 6 ++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 531c2b3d814e..0b212cf2e794 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -744,13 +744,19 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, state = clk_pll_is_enabled(hw); + if (state && pll->params->pre_rate_change) { + ret = pll->params->pre_rate_change(); + if (WARN_ON(ret)) + return ret; + } + _get_pll_mnp(pll, &old_cfg); if (state && pll->params->defaults_set && pll->params->dyn_ramp && (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { ret = pll->params->dyn_ramp(pll, cfg); if (!ret) - return 0; + goto done; } if (state) { @@ -772,6 +778,10 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, pll_clk_start_ss(pll); } +done: + if (state && pll->params->post_rate_change) + pll->params->post_rate_change(); + return ret; } diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 412d4b47ecfd..e67c19eadb19 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -266,6 +266,10 @@ struct tegra_clk_pll; * disabled. * @dyn_ramp: Callback which can be used to define a custom * dynamic ramp function for a given PLL. + * @pre_rate_change: Callback which is invoked just before changing + * PLL's rate. + * @post_rate_change: Callback which is invoked right after changing + * PLL's rate. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -342,6 +346,8 @@ struct tegra_clk_pll_params { void (*set_defaults)(struct tegra_clk_pll *pll); int (*dyn_ramp)(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg); + int (*pre_rate_change)(void); + void (*post_rate_change)(void); }; #define TEGRA_PLL_USE_LOCK BIT(0) From patchwork Thu Mar 19 19:02:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447903 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2DCB16CA for ; Thu, 19 Mar 2020 19:05:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 03B332072D for ; Thu, 19 Mar 2020 19:05:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Jv1nnxbM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727389AbgCSTE4 (ORCPT ); Thu, 19 Mar 2020 15:04:56 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:40077 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726934AbgCSTEP (ORCPT ); Thu, 19 Mar 2020 15:04:15 -0400 Received: by mail-lj1-f194.google.com with SMTP id 19so3760963ljj.7; Thu, 19 Mar 2020 12:04:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YQCiOS4Pyn9ED/MgeohcKz78uGXYycVKqXoXcDIM5iY=; b=Jv1nnxbM/OsQc82UxjrfUi2g2dHNGyoVgg5OkVxcxKfYIZbC5n+m32dkr4geTnRB/g jbEpd6oauDLjEjdZ27p1373wdu8IJmdAjzbV+FV27TQ7AibA0FvX7fpM71X0rJ06+wzV GDQgpf/qy/7QNO04+jvB83vVBpr47VmIaQqCAkaV36kfJUjpRmKNfUh8J71rHEnBLPUr VgXcb/9386+NQlZKl+RbH33hlbPeprXV8spb4YTxYDKxQWaI2Ta9kpTlPsm+jPQPYiqz Gxs9ukwLavsQWNQCiZkiVa0FSQlrYLni3lVGybYhH80dfLBCXyNUG1HqPWX2tLoPIw+/ Sr/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YQCiOS4Pyn9ED/MgeohcKz78uGXYycVKqXoXcDIM5iY=; b=LZd8pwLBmgCR2u3Fq7PlLdDCZQKsYrOVMdQgtNyU6MrFWNCYCzsDnJSvLgf+ZzKvec Ih1FYR/IDXklyP1eGaZ2EgXIQvMVN1hQv8vsb8IHATJJupQOhIZ05sKAIaKWi+9C5BE+ 2ADgL/etDrPXsyGavA9y2u8sZU3sHJo3bKQY+rWc6I+VVtVZRGu7/8T0NZyJxfFTyaek wn7vOGhjD9NEavKeMuGtVf3BZ3CUH9F2Y7QFazTdBaZekvwPnhjaqhBvlrIBqQWMulj8 c80FoIYJP30c16j+v3ukTvd0vlTR7xFz5/BCBkm2VnmmcFU2lUCCxYjuQhZy8gX+nQK1 FYZQ== X-Gm-Message-State: ANhLgQ2GDZkdFZAAMhgDFIPlvDMSlUjESb3l1NOWuaDg9EVBfU+tiJWT ik5iEEHv5ZrMg6Q/3+UhOvU= X-Google-Smtp-Source: ADFU+vtqJqyB9vPFtt9Xrh9pbzmrwmwrz/OOytKPu7fJKEQJa4/uVeXn4zJCxQGP+Vln8fAuCeKv5A== X-Received: by 2002:a2e:99d6:: with SMTP id l22mr2962336ljj.231.1584644650609; Thu, 19 Mar 2020 12:04:10 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:10 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 03/12] clk: tegra: cclk: Add helpers for handling PLLX rate changes Date: Thu, 19 Mar 2020 22:02:20 +0300 Message-Id: <20200319190229.32200-4-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index 7bcb9e8d0860..a03119c30456 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -25,6 +25,9 @@ #define SUPER_CDIV_ENB BIT(31) +static struct tegra_clk_super_mux *cclk_super; +static bool cclk_on_pllx; + static u8 cclk_super_get_parent(struct clk_hw *hw) { return tegra_clk_super_ops.get_parent(hw); @@ -115,6 +118,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name, struct clk_init_data init; u32 val; + if (WARN_ON(cclk_super)) + return ERR_PTR(-EBUSY); + super = kzalloc(sizeof(*super), GFP_KERNEL); if (!super) return ERR_PTR(-ENOMEM); @@ -173,6 +179,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name, clk = clk_register(NULL, &super->hw); if (IS_ERR(clk)) kfree(super); + else + cclk_super = super; return clk; } + +int tegra_cclk_pre_pllx_rate_change(void) +{ + if (IS_ERR_OR_NULL(cclk_super)) + return -EINVAL; + + if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX) + cclk_on_pllx = true; + else + cclk_on_pllx = false; + + /* + * CPU needs to be temporarily re-parented away from PLLX if PLLX + * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs. + */ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX); + + return 0; +} + +void tegra_cclk_post_pllx_rate_change(void) +{ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX); +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index e67c19eadb19..8ca215955bfa 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -771,6 +771,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +int tegra_cclk_pre_pllx_rate_change(void); +void tegra_cclk_post_pllx_rate_change(void); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Thu Mar 19 19:02:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447899 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7334C1667 for ; Thu, 19 Mar 2020 19:04:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 49D9C2072C for ; Thu, 19 Mar 2020 19:04:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lr3jIRYy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727567AbgCSTER (ORCPT ); Thu, 19 Mar 2020 15:04:17 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:42292 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727532AbgCSTEP (ORCPT ); Thu, 19 Mar 2020 15:04:15 -0400 Received: by mail-lf1-f65.google.com with SMTP id t21so2554245lfe.9; Thu, 19 Mar 2020 12:04:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EYtwxh3M0WCDakQMYK6DovCpFCADDGOR6efWhY9EA5A=; b=lr3jIRYyhBT4KmYsOY3VhhCZZB2LkOgGOGd5DeAjpZ9V+xz6sClDAXin4nBvsXqCmu wHBBexrwWsfCchcXviHX0il3ngcfyRyVSV8MhcH5b/0rMTj49tFssKtcfvIwTGlulB0c xx7B6akVM4AvVJ04tz0OH8cPB0RnDdwpRU7hHLWbwEMLcuKspBmGfRLhOb590E7kt5PW jg3sC7qg9F7OKhFIEAoqZNl7dfwm+7nVyQ6bC+gg5TF9xLKNx5/o1oVrosfGJWQsZf1O 4vgastk/Z/Tms/TcYdUcEbh6A0vywfsj9YCzHbkI34tXYgdYmp4T81F0HqH4PPqqtAzI wEfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EYtwxh3M0WCDakQMYK6DovCpFCADDGOR6efWhY9EA5A=; b=g73DsK8PqBRlEXti8OAg3cL1DDjLVqTEGuaG0MuLQQWi5oe+mXLdLk/lZbxaGnsmti XlEpkVrO+mFVtRO2/G0d6WYy347xBx0s0r+BoHm4eqoECezf5vwOOiyUoeSFDx1Dky+W WEk48Yf6SKF7GczHqlY3sf2Uq9H3A7QqPZeegYmoXFw3Adh0AhmQpDYtv0cWIYSkr/zW 0bsIcI0uyZ6XLTAUsHeXKGfiurI8PC0Zkm5ydGzd+PpYRgpcapM0+ciEHQfucoJba1Nn 6UHiBQuii3tJ2xCiJ5RvoIc4jQ/fxv/CkJAWg64WTBXKrI2sc3dyrhFBndvsU5OYV+Fg I7Sg== X-Gm-Message-State: ANhLgQ3NfpoD9vKAmjv/pj3j1EVlDAy+VmSxrQd587Iyb3c0AFQpOBnQ +fVppYALLTkoYV8KISEbvxaKwxj4 X-Google-Smtp-Source: ADFU+vtBwRJ6EJ+7CZAsKbNUCuVjCzTZlGUgAHK4g8oqA0XRRkDZZTh7ycJg+SYDnFURJnBa4V+XfQ== X-Received: by 2002:a19:4a12:: with SMTP id x18mr2953940lfa.161.1584644651906; Thu, 19 Mar 2020 12:04:11 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:11 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 04/12] clk: tegra20: Use custom CCLK implementation Date: Thu, 19 Mar 2020 22:02:21 +0300 Message-Id: <20200319190229.32200-5-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 085feb04e913..3efc651b42e3 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -391,6 +391,8 @@ static struct tegra_clk_pll_params pll_x_params = { .lock_delay = 300, .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params = { @@ -702,9 +704,10 @@ static void tegra20_super_clk_init(void) struct clk *clk; /* CCLK */ - clk = tegra_clk_register_super_mux("cclk", cclk_parents, + clk = tegra_clk_register_super_cclk("cclk", cclk_parents, ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, - clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); + clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK, + NULL); clks[TEGRA20_CLK_CCLK] = clk; /* SCLK */ From patchwork Thu Mar 19 19:02:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447867 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE3106CA for ; Thu, 19 Mar 2020 19:04:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB24D20752 for ; Thu, 19 Mar 2020 19:04:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pfRDJg2z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727599AbgCSTER (ORCPT ); Thu, 19 Mar 2020 15:04:17 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:35725 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727525AbgCSTEQ (ORCPT ); Thu, 19 Mar 2020 15:04:16 -0400 Received: by mail-lj1-f193.google.com with SMTP id u12so3807535ljo.2; Thu, 19 Mar 2020 12:04:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ODK6Kk27PrnQOcFwDD//72uI90JfjAQ39Nvujl8BUsc=; b=pfRDJg2z9wrKPiHrbHUuqoEe7njI8jZ5ZMZwH6oC1qfo7Xxy68z07cM7Cy0IPhyw5d spTeJzZ0YBLtM3Jz1rrFYZAPyJQl03lu+YZaX1M2uqVmdwAD+xeLy/4+iuQvCCdQjaBU +kpqzGItC0P3717T1WpXEr2A8eEhkclIBC00gGR42EzcqmSbIAB6ZSTQogVhV57y9TbT a7TDuCyUiFr1DjvhChaFijxBFOUU4uMgj0CGNmMR2AuHtPfMHZ+n4QGW6bcXFRLuXmer dPFUQyBaRd145d8jjd6bI1DRoSJ5kq5MJMtpfceyJKruf/vmb5eiYNaWlQyiDUtmTlHR Kk/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ODK6Kk27PrnQOcFwDD//72uI90JfjAQ39Nvujl8BUsc=; b=qxO13vGJkbZk311IGua/XTlPlZj5f9BddGm1A35qycVc95ONoi1MPGVVKPIlevG1DG +O9OyXXQkczqL8qFPXT6xsVHCMyLeNSuPHyI4746MtY98vM/zsZ0gviQpQE8gvCPt5uI ozzDTtxqa+ZJarjfTzAc01P/aslnr64YmYv5Es3SO3wy+3I/kqBTlv3ALOVDVN8VWcrs u9U3TVsJHF+qimPfWlbhlKx4D2gxR877g2cWQ++PE+8rip3JEMSfIUgrMo0xpTlSZQwb DAnwuoVqvwnYRpQqwnXGjDoG2geUAjTvLpa/TYVVGVpjAE6gb8zHHM0W6P4Aa+CKHGVS inVQ== X-Gm-Message-State: ANhLgQ3CQYj6v0KsjatAK2YePam91Xhk0bKS0kBNqz6wdFioikDGbcgP MwXLyKjq5c7ZE0KHcBvbdNY= X-Google-Smtp-Source: ADFU+vu/OkZ/e8wr4dxL0lZawKNIvBrUkaPvsqSLQ1B07/+runsfIKJWJW7mKOYeXA2qecrb+BuvLg== X-Received: by 2002:a2e:b0f0:: with SMTP id h16mr2952495ljl.48.1584644653682; Thu, 19 Mar 2020 12:04:13 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:13 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 05/12] clk: tegra30: Use custom CCLK implementation Date: Thu, 19 Mar 2020 22:02:22 +0300 Message-Id: <20200319190229.32200-6-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra30 SoCs to use that implementation. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra30.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 3255f82e61b5..37244a7e68c2 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = { .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params __ro_after_init = { @@ -926,11 +928,11 @@ static void __init tegra30_super_clk_init(void) clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); /* CCLKG */ - clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, + clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), CLK_SET_RATE_PARENT, clk_base + CCLKG_BURST_POLICY, - 0, 4, 0, 0, NULL); + 0, NULL); clks[TEGRA30_CLK_CCLK_G] = clk; /* From patchwork Thu Mar 19 19:02:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447871 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1CCD6CA for ; Thu, 19 Mar 2020 19:04:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9FB2B20767 for ; Thu, 19 Mar 2020 19:04:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fgDbP8zs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727425AbgCSTEZ (ORCPT ); Thu, 19 Mar 2020 15:04:25 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:45534 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727605AbgCSTES (ORCPT ); Thu, 19 Mar 2020 15:04:18 -0400 Received: by mail-lj1-f194.google.com with SMTP id y17so3738483ljk.12; Thu, 19 Mar 2020 12:04:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QuRqkZzuBA2/gmQ7xtdmACyr3vk58NcEc2vx8jtn50U=; b=fgDbP8zsUAW9bA62o3tLbYLIVEbM2eTutxjzwU3WD7St4VHgYg6sc3FbITh2C1JgJ1 DIkXLFmvcV8rb6MQgtt2svBglbhbtkJVwK3X3rItTf6xPcPlKk6Bv6HznqLmPT3eZWkt 0Q+k1X62dpHvSIFnda1AdpsbIySHIrKRxEZMcnJ9Qh8pHXH3ovG464TFpb0wVFtTIX2I AyYcJHwC0sExsxh2uyFX8VBDQ16yq39jEJ79q9XZ9xVCiSJyBc2Jx2BLIe1fc5qQ3wY8 BSusDPzzRov1m5N3QvM35ET8xF1LACtVdUjEkc3jhDZmFTMS23ak2dKVpOXxhqoRUEwY GvoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QuRqkZzuBA2/gmQ7xtdmACyr3vk58NcEc2vx8jtn50U=; b=H+BoippxQhAlY+EmTat5nFJcZyWk7oEdODyXrkRnIpZeV8QvoGnVRHjqpg9cu0XvWu iCQf2z3j71cnvOX9B925c/3CjtVqj99ZhgXKQ908BN0FkJrJBzKQ+G0DDhNGVpQxRybw KlNW/cKphg5Fvi2Guc46eapNZSrpBKwwJ77dSdABH4B/iqms4UzohCuoER95OfH+vHYg 9nFw8S6/YmTqY2rH4QtHOadD0n4dpMcYmwEcPtWhC4o/6YJI1jULa+EcFalsx3WHkRyi xdqjHswDSlYtFpo0/ZBpgzi3pmpluEZS3LJdM2sHK/6KtSKgAyuQkQcBE4C53qRsTeBm fU1w== X-Gm-Message-State: ANhLgQ0lAZNJj5NDfc+m5sVfg/OmhM43efcqRYa/U9J+NOofdAz0anto baRxbJGxDBqQc595gS1PvLo= X-Google-Smtp-Source: ADFU+vsyNXvrrCmF9RHJb8MzXpeuDppLJbR+WLUOx2J32CGevDmUiS8+zyoVSdTm79PbsRfRxQS9cw== X-Received: by 2002:a05:651c:1190:: with SMTP id w16mr3019696ljo.119.1584644654870; Thu, 19 Mar 2020 12:04:14 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:14 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 06/12] ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124 Date: Thu, 19 Mar 2020 22:02:23 +0300 Message-Id: <20200319190229.32200-7-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The early-resume code shall not switch CPU to PLLX because PLLX configuration could be unstable or PLLX should be simply disabled if CPU enters into suspend running off some other PLL (the case if CPUFREQ driver is active). The actual burst policy is restored by the clock drivers. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/sleep-tegra30.S | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index e7bcf7dc4675..9942265ed650 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -398,11 +398,8 @@ _pll_m_c_x_done: ldr r4, [r5, #0x1C] @ restore SCLK_BURST str r4, [r0, #CLK_RESET_SCLK_BURST] - cmp r10, #TEGRA30 - movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX - movteq r4, #:upper16:((1 << 28) | (0x8)) - movwne r4, #:lower16:((1 << 28) | (0xe)) - movtne r4, #:upper16:((1 << 28) | (0xe)) + movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP + movt r4, #:upper16:((1 << 28) | (0x4)) str r4, [r0, #CLK_RESET_CCLK_BURST] /* Restore pad power state to normal */ From patchwork Thu Mar 19 19:02:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447885 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFD776CA for ; Thu, 19 Mar 2020 19:04:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CEAF02070A for ; Thu, 19 Mar 2020 19:04:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RY2paf91" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727733AbgCSTE0 (ORCPT ); Thu, 19 Mar 2020 15:04:26 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:36155 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727634AbgCSTET (ORCPT ); Thu, 19 Mar 2020 15:04:19 -0400 Received: by mail-lj1-f194.google.com with SMTP id g12so3798190ljj.3; Thu, 19 Mar 2020 12:04:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xuQCFAUGgCNgfRWuRofqyV6Hacg6YekuN6dbxQCNP6M=; b=RY2paf91r5jWzSsQNP0zg+H0SLHwnzcSyzLAd6c0M+q22ayiEhFdHhwEH6NgeZaIoo lm7T7ath6xuVnESAC8jjH9rQCs52R70pEXBGdgstnEWQePXZo359EqVl+VL94Jc2zfNP pFfFbPBeUZIA3DU/RxsfgqwnKMFT2Zeg9jYrMWsWjsUzLgHI5jmc4b1wAwOQwTp2x5YU YnWTziG6x5/aTumOvNYJbvOgn1PsObQaOxcSucSxWPUiKxdvL49vzeyQPJqwhC7+UU2w hUqIx1ns5LkZLkmXWWMooozHfUZi+ibu1hBEh+EmfbZ3+Fjo/f3ikxxyJDIwn24LDjvq sBDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xuQCFAUGgCNgfRWuRofqyV6Hacg6YekuN6dbxQCNP6M=; b=blDl6PVVEaWXO44i7giNqBSKBABfIdj/Y/3JV+RV8HhFHsDB5QCyXdCxmVycFnJ5HQ Beh/hRYhEnR+EzFTk2YsBQz2d2MxloRQtE8t3BtsTQ1wbxUnC+IOFKQ6RB4T0EUzAe04 2Be0ROIxc8v7vgpK9VZ2ZhscZ7LIYI5eI1QjvvuflPbu2Z+GeGNlVlgTZNz5M+GwfWLb 5OJ67i7Tpm6wbIXngTL0WRcj5VniNM+l2UyhysVBKwrA5xkHPDgWtfAhI9h6E79SsMQr D2z65wfIB5zXI1W91GOJOv/ckfmeGEEJGNmvPEBmIsN8ZdaZFSWqr+DN4K0cAiTo7WWd Prsg== X-Gm-Message-State: ANhLgQ2D+bIGcmIGU2JWZxaiL57SA0DwxYDJHaESu/9IxUPLNlgMth8U 1lhFSah+f7P7gPMfJFb9pi0= X-Google-Smtp-Source: ADFU+vuAcWsH2NpVCmk1A29yzI5t9CR3MACNcvLowJJ5OPnvquLwIHYssOw/2X3SNkhRKIDFN3uADQ== X-Received: by 2002:a05:651c:2007:: with SMTP id s7mr3146298ljo.214.1584644656425; Thu, 19 Mar 2020 12:04:16 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:15 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 07/12] ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30 Date: Thu, 19 Mar 2020 22:02:24 +0300 Message-Id: <20200319190229.32200-8-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org PLLX may be kept disabled if cpufreq driver selects some other clock for CPU. In that case PLLX will be disabled later in the resume path by the CLK driver, which also can enable PLLX if necessary by itself. Thus there is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do not manage PLLX on resume and thus they are left untouched by this patch. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/sleep-tegra30.S | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 9942265ed650..2667bcdb5dc6 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -361,7 +361,6 @@ _no_pll_iddq_exit: pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC - pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC _pll_m_c_x_done: pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC @@ -371,12 +370,18 @@ _pll_m_c_x_done: pll_locked r1, r0, CLK_RESET_PLLP_BASE pll_locked r1, r0, CLK_RESET_PLLA_BASE pll_locked r1, r0, CLK_RESET_PLLC_BASE - pll_locked r1, r0, CLK_RESET_PLLX_BASE + /* + * CPUFreq driver could select other PLL for CPU. PLLX will be + * enabled by the Tegra30 CLK driver on an as-needed basis, see + * tegra30_cpu_clock_resume(). + */ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 cmp r1, #TEGRA30 beq 1f + pll_locked r1, r0, CLK_RESET_PLLX_BASE + ldr r1, [r0, #CLK_RESET_PLLP_BASE] bic r1, r1, #(1<<31) @ disable PllP bypass str r1, [r0, #CLK_RESET_PLLP_BASE] From patchwork Thu Mar 19 19:02:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447887 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D5D96CA for ; Thu, 19 Mar 2020 19:04:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF840208E4 for ; Thu, 19 Mar 2020 19:04:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="oSCaS/SY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727709AbgCSTE0 (ORCPT ); Thu, 19 Mar 2020 15:04:26 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:34432 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727532AbgCSTEU (ORCPT ); Thu, 19 Mar 2020 15:04:20 -0400 Received: by mail-lj1-f195.google.com with SMTP id s13so3803315ljm.1; Thu, 19 Mar 2020 12:04:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6NDM3y718xZuy8aOtgXuzMNzfqLpqznJlVGk7yDXVsI=; b=oSCaS/SYuXxnhdgHKyWrJhoZyTBX5rU/amUONz2Ljsi/UiU7X9UhOb6QOCdMI9hK7Z Eg3hP/HymfYWM547Fz875jonQgbas/3ZQDC5ZoVellGkCAKC6iMxYLEZy2J7oCaiNMfO UH4+I/++JolujZGrZ3u0P+NaL0MOs+O3UH/4W41YsdjdP1mZUck7aEbkFrKmt4kg3fnB 2jashczYx/oyzhIf+uB/NYO8Tg0tUBEML5MWUDykUxQUfPDf9IHYoI+AHBCMt/kHYmjr vx/lyT/ODByTEil/EPM2sM0/6PQi+94rfHaMEwPA5tI7OD+29A1P2F3RZQ9M0GSYohnw TdNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6NDM3y718xZuy8aOtgXuzMNzfqLpqznJlVGk7yDXVsI=; b=USLp0Dj/KUc5kAXvkiCGWeoVwZ/TmDqEfeqkYMmoc9dR/x/d1dsL/Fls0eV3CYIvnJ ngv9rrHN73I4yu1nY3qT/CuMP3R+/WdOdPklMhkEbHdgD2jGwyqWY1+EYAjVPgGrANza HWFADgzF37GZXNsTY5xFlRJPh5Cb/IHUxi0aTzwMwnj2xZat8vRrXU2rZdSmQGoqEL7c dUOQAQVrCdMN5IMNO7T9NMGjgWZ8y05taKEUsBiiFFQAQUY3JJNqSLsEbrgpSB8/kitW G4tbbPgMYAO0tCtWBtDktRpAhgiApP/cMiErnLWmUm1r/SDT2Hp93H1ycW0KVYUpyNot d+Vg== X-Gm-Message-State: ANhLgQ3ZBGjC3CMQZRrV63OjFrwm1uwDXIjT54tiQ1k/o5ZwcYgQWNQj q3/mWv3SLm5tM6eL5NbIt9Q= X-Google-Smtp-Source: ADFU+vsT7jEftmMyIkFi6InTDoQcYx/pXDz1dObMgQwcHj/ITyzMDqlO3CNcFOHP4By0rSwhidK8Pg== X-Received: by 2002:a2e:860e:: with SMTP id a14mr2934829lji.218.1584644658471; Thu, 19 Mar 2020 12:04:18 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:17 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 08/12] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Date: Thu, 19 Mar 2020 22:02:25 +0300 Message-Id: <20200319190229.32200-9-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs. Acked-by: Viresh Kumar Reviewed-by: Rob Herring Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko --- .../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file mode 100644 index 000000000000..daeca6ae6b76 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt @@ -0,0 +1,56 @@ +Binding for NVIDIA Tegra20 CPUFreq +================================== + +Required properties: +- clocks: Must contain an entry for the CPU clock. + See ../clocks/clock-bindings.txt for details. +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + On Tegra20: + 1. CPU process ID mask + 2. SoC speedo ID mask + + On Tegra30: + 1. CPU process ID mask + 2. CPU speedo ID mask + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +- opp-microvolt: CPU voltage triplet. + +Optional properties: +- cpu-supply: Phandle to the CPU power supply. + +Example: + regulators { + cpu_reg: regulator0 { + regulator-name = "vdd_cpu"; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@456000000 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + ... + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&cpu_reg>; + #cooling-cells = <2>; + }; + }; From patchwork Thu Mar 19 19:02:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447893 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74D886CA for ; Thu, 19 Mar 2020 19:04:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4B60A2075E for ; Thu, 19 Mar 2020 19:04:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WslMzcFW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727692AbgCSTEZ (ORCPT ); Thu, 19 Mar 2020 15:04:25 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:44247 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727523AbgCSTEY (ORCPT ); Thu, 19 Mar 2020 15:04:24 -0400 Received: by mail-lj1-f195.google.com with SMTP id w4so3749428lji.11; Thu, 19 Mar 2020 12:04:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HcVPDM5Q0ZZN5Y36SDXsAjsWRFoKQJoeMe3Md7vNsro=; b=WslMzcFWS38Q9VwchRNANkQG/cd68B43Y7+vFOOWphfw8Ex6g2jemYTe9dF17qbnYK 5qwnfdom6iYnJQA4oQZTo7D0tdehphbU1+IXanqxV42riTaZhqbSgs8aoXm4vUyxmzHY CvJC0R2dhrOQ1tITLYm1xhEpm8ANzezSxIaIO+W6U8fu4Qagc3V+bC4/nwg8hFuhrl2b fubJZRvPLm5Ks7SpcCc2gfaJGQZYSWsma+yWFKp4CA7mjbkrMgp0Oq7DF/Rleo/NZXSh qGFQPwrgpXHt75QqU1N4HVP+KsNxT2+3lwAAm7Wl34fsRNsFW2IqrFkOCEv6yJVyTNaC wzBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HcVPDM5Q0ZZN5Y36SDXsAjsWRFoKQJoeMe3Md7vNsro=; b=g40+yjpBTAuKCxrj368nJNweJuBXVRKvrswrkkMy6oTIcEllYO2WqpKRzzlCj1NkJj 15iqkDG/u0/v0rYsV5kY6C5Dw6HRTyCXMeuE9bjR2AS5mtANMuCywMsEyFB8Hta5oLF8 hSje+3raLtViKRIwlAmUbBaI0cQmrklSaaMGJX3dLF50aSvTyyejY10gsRKls1SVxIgR X/Zfa6g17hmUhvUBrUMZ8q8zlaB9XK0GwqLLySFxgEa+Mp43L1Y2UvZkIKZfXQI9DJ6r bQ/PVSCoiOAGeC+JZSJZQHFDneBuCo+mivco/8Gk7I9a/sgCPQx9EL+t+/JyWRgekfUB VNgw== X-Gm-Message-State: ANhLgQ1IiK795eNTZlKHYSxJ0Q68jHgIBAmhkm4SQcHmB8OhnVgJlfXe 4BoDh5iKRiZTjz5GnKdCbpA= X-Google-Smtp-Source: ADFU+vvQL/Zg/Vyf+W2DmbkM2tVmUj0h68q9r8nGoxNsGUOmv/NKb5RCb88yUseLggRBMLSGFrJmbA== X-Received: by 2002:a2e:81c9:: with SMTP id s9mr2997125ljg.95.1584644660383; Thu, 19 Mar 2020 12:04:20 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:19 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 09/12] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Date: Thu, 19 Mar 2020 22:02:26 +0300 Message-Id: <20200319190229.32200-10-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Re-parenting to intermediate clock is supported now by the clock driver and thus there is no need in a customized CPUFreq driver, all that code is common for both Tegra20 and Tegra30. The available CPU freqs are now specified in device-tree in a form of OPPs, all users should update their device-trees. Acked-by: Viresh Kumar Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/cpufreq/Kconfig.arm | 6 +- drivers/cpufreq/tegra20-cpufreq.c | 217 ++++++++---------------------- 2 files changed, 59 insertions(+), 164 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 3858d86cf409..92a6a5089979 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -295,11 +295,11 @@ config ARM_TANGO_CPUFREQ default y config ARM_TEGRA20_CPUFREQ - tristate "Tegra20 CPUFreq support" - depends on ARCH_TEGRA + tristate "Tegra20/30 CPUFreq support" + depends on ARCH_TEGRA && CPUFREQ_DT default y help - This adds the CPUFreq driver support for Tegra20 SOCs. + This adds the CPUFreq driver support for Tegra20/30 SOCs. config ARM_TEGRA124_CPUFREQ bool "Tegra124 CPUFreq support" diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c index f84ecd22f488..8c893043953e 100644 --- a/drivers/cpufreq/tegra20-cpufreq.c +++ b/drivers/cpufreq/tegra20-cpufreq.c @@ -7,201 +7,96 @@ * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation */ -#include -#include +#include +#include #include #include #include +#include #include +#include #include -static struct cpufreq_frequency_table freq_table[] = { - { .frequency = 216000 }, - { .frequency = 312000 }, - { .frequency = 456000 }, - { .frequency = 608000 }, - { .frequency = 760000 }, - { .frequency = 816000 }, - { .frequency = 912000 }, - { .frequency = 1000000 }, - { .frequency = CPUFREQ_TABLE_END }, -}; - -struct tegra20_cpufreq { - struct device *dev; - struct cpufreq_driver driver; - struct clk *cpu_clk; - struct clk *pll_x_clk; - struct clk *pll_p_clk; - bool pll_x_prepared; -}; +#include +#include -static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy, - unsigned int index) +static bool cpu0_node_has_opp_v2_prop(void) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - - /* - * Don't switch to intermediate freq if: - * - we are already at it, i.e. policy->cur == ifreq - * - index corresponds to ifreq - */ - if (freq_table[index].frequency == ifreq || policy->cur == ifreq) - return 0; - - return ifreq; -} + struct device_node *np = of_cpu_device_node_get(0); + bool ret = false; -static int tegra_target_intermediate(struct cpufreq_policy *policy, - unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - int ret; - - /* - * Take an extra reference to the main pll so it doesn't turn - * off when we move the cpu off of it as enabling it again while we - * switch to it from tegra_target() would take additional time. - * - * When target-freq is equal to intermediate freq we don't need to - * switch to an intermediate freq and so this routine isn't called. - * Also, we wouldn't be using pll_x anymore and must not take extra - * reference to it, as it can be disabled now to save some power. - */ - clk_prepare_enable(cpufreq->pll_x_clk); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - if (ret) - clk_disable_unprepare(cpufreq->pll_x_clk); - else - cpufreq->pll_x_prepared = true; + if (of_get_property(np, "operating-points-v2", NULL)) + ret = true; + of_node_put(np); return ret; } -static int tegra_target(struct cpufreq_policy *policy, unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned long rate = freq_table[index].frequency; - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - int ret; - - /* - * target freq == pll_p, don't need to take extra reference to pll_x_clk - * as it isn't used anymore. - */ - if (rate == ifreq) - return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - - ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000); - /* Restore to earlier frequency on error, i.e. pll_x */ - if (ret) - dev_err(cpufreq->dev, "Failed to change pll_x to %lu\n", rate); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); - /* This shouldn't fail while changing or restoring */ - WARN_ON(ret); - - /* - * Drop count to pll_x clock only if we switched to intermediate freq - * earlier while transitioning to a target frequency. - */ - if (cpufreq->pll_x_prepared) { - clk_disable_unprepare(cpufreq->pll_x_clk); - cpufreq->pll_x_prepared = false; - } - - return ret; -} - -static int tegra_cpu_init(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_prepare_enable(cpufreq->cpu_clk); - - /* FIXME: what's the actual transition time? */ - cpufreq_generic_init(policy, freq_table, 300 * 1000); - policy->clk = cpufreq->cpu_clk; - policy->suspend_freq = freq_table[0].frequency; - return 0; -} - -static int tegra_cpu_exit(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_disable_unprepare(cpufreq->cpu_clk); - return 0; -} - static int tegra20_cpufreq_probe(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq; + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; + struct device *cpu_dev; + u32 versions[2]; int err; - cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL); - if (!cpufreq) - return -ENOMEM; + if (!cpu0_node_has_opp_v2_prop()) { + dev_err(&pdev->dev, "operating points not found\n"); + dev_err(&pdev->dev, "please update your device tree\n"); + return -ENODEV; + } + + if (of_machine_is_compatible("nvidia,tegra20")) { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.soc_speedo_id); + } else { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.cpu_speedo_id); + } + + dev_info(&pdev->dev, "hardware version 0x%x 0x%x\n", + versions[0], versions[1]); - cpufreq->cpu_clk = clk_get_sys(NULL, "cclk"); - if (IS_ERR(cpufreq->cpu_clk)) - return PTR_ERR(cpufreq->cpu_clk); + cpu_dev = get_cpu_device(0); + if (WARN_ON(!cpu_dev)) + return -ENODEV; - cpufreq->pll_x_clk = clk_get_sys(NULL, "pll_x"); - if (IS_ERR(cpufreq->pll_x_clk)) { - err = PTR_ERR(cpufreq->pll_x_clk); - goto put_cpu; + opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2); + err = PTR_ERR_OR_ZERO(opp_table); + if (err) { + dev_err(&pdev->dev, "failed to set supported hw: %d\n", err); + return err; } - cpufreq->pll_p_clk = clk_get_sys(NULL, "pll_p"); - if (IS_ERR(cpufreq->pll_p_clk)) { - err = PTR_ERR(cpufreq->pll_p_clk); - goto put_pll_x; + cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0); + err = PTR_ERR_OR_ZERO(cpufreq_dt); + if (err) { + dev_err(&pdev->dev, + "failed to create cpufreq-dt device: %d\n", err); + goto err_put_supported_hw; } - cpufreq->dev = &pdev->dev; - cpufreq->driver.get = cpufreq_generic_get; - cpufreq->driver.attr = cpufreq_generic_attr; - cpufreq->driver.init = tegra_cpu_init; - cpufreq->driver.exit = tegra_cpu_exit; - cpufreq->driver.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK; - cpufreq->driver.verify = cpufreq_generic_frequency_table_verify; - cpufreq->driver.suspend = cpufreq_generic_suspend; - cpufreq->driver.driver_data = cpufreq; - cpufreq->driver.target_index = tegra_target; - cpufreq->driver.get_intermediate = tegra_get_intermediate; - cpufreq->driver.target_intermediate = tegra_target_intermediate; - snprintf(cpufreq->driver.name, CPUFREQ_NAME_LEN, "tegra"); - - err = cpufreq_register_driver(&cpufreq->driver); - if (err) - goto put_pll_p; - - platform_set_drvdata(pdev, cpufreq); + platform_set_drvdata(pdev, cpufreq_dt); return 0; -put_pll_p: - clk_put(cpufreq->pll_p_clk); -put_pll_x: - clk_put(cpufreq->pll_x_clk); -put_cpu: - clk_put(cpufreq->cpu_clk); +err_put_supported_hw: + dev_pm_opp_put_supported_hw(opp_table); return err; } static int tegra20_cpufreq_remove(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq = platform_get_drvdata(pdev); + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; - cpufreq_unregister_driver(&cpufreq->driver); + cpufreq_dt = platform_get_drvdata(pdev); + platform_device_unregister(cpufreq_dt); - clk_put(cpufreq->pll_p_clk); - clk_put(cpufreq->pll_x_clk); - clk_put(cpufreq->cpu_clk); + opp_table = dev_pm_opp_get_opp_table(get_cpu_device(0)); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_opp_table(opp_table); return 0; } From patchwork Thu Mar 19 19:02:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447889 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E61E21667 for ; Thu, 19 Mar 2020 19:04:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C570C2070A for ; Thu, 19 Mar 2020 19:04:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="feeFqaI4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727699AbgCSTEZ (ORCPT ); Thu, 19 Mar 2020 15:04:25 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:36054 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727279AbgCSTEY (ORCPT ); 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[94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:21 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 10/12] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Date: Thu, 19 Mar 2020 22:02:27 +0300 Message-Id: <20200319190229.32200-11-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully supported by that driver. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index f1ce2857a251..3882a6c66969 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -96,6 +96,10 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available()) platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && + of_machine_is_compatible("nvidia,tegra30")) + platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { From patchwork Thu Mar 19 19:02:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2C5D51894 for ; Thu, 19 Mar 2020 19:04:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 01FFF20754 for ; Thu, 19 Mar 2020 19:04:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="d1qtGLvq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727744AbgCSTE0 (ORCPT ); Thu, 19 Mar 2020 15:04:26 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:43853 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727525AbgCSTEZ (ORCPT ); Thu, 19 Mar 2020 15:04:25 -0400 Received: by mail-lf1-f68.google.com with SMTP id n20so2557022lfl.10; Thu, 19 Mar 2020 12:04:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NCItyd8yjMwPtwwQd4zzBNEoARaFlEvxh+OiOGd8HtY=; b=d1qtGLvqLnU4YGXDa+6ltiSnOsN+uAC2wfCdh4DfRhRb4yiJlWqp3But/WMhc9h2FN 0vBG2xchq3N/jf0HJGpqlMPpiVF7pTM5qs78TJaAc0wsDzZ5Jx/j92qfuJi0G3n9btzk GemnM26fj2voN77S85eLhsxb+n1zLB9fNGsl3gMpy5R0BwcAZNEqv0WRvwvFupg5zULG xqtPJ+EzGotxRDPxuPanWXH/DsIQnBJRDgLU3v4uRb/U/4EOfWXKClTiY48+2cRcABxo iRm558gtm8TVqt8gdg9Xgvyc7m23XXUznEGkc0wgstJwOf2Zj/ppbcMRvRUw3ZaIJ9// +7Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NCItyd8yjMwPtwwQd4zzBNEoARaFlEvxh+OiOGd8HtY=; b=RIdNXd1IpOGJCJA0KvaxPXHQgwGx5jxI6H5Q30cYYwemwQ5k3qbc7tRlZfCBZiRZRw 4vij9Kjus7xopug/wuLTJ1WqIalSY0SSgugoFrHcvX96hhUr51v2PS/cg3qEM2GW9DTZ 8X6U+r3rIx2KfOPnY04fZNUdmChYMwx3TqCE0zkSwI8L2FoQgOHnFKfhM+j8QtG3eTTv QJ2GZUWPNZo0U6WtqdaFb62zR7AdxoxVzOLdKScB+bsL30KjN1/UeQc3c0jb4HIS0RIx KxuFoeg0yjafyanj5U2prPHzSbeMurBnLS6MurqUpZHxZHnxbDglOCRbrTd+RWdYcfG7 cf1Q== X-Gm-Message-State: ANhLgQ1dFS2PDrTgCFbuEDeFlOsdl9Nu33AKGmgXQUuDcvTuV5U85gIr C+hKwyg/PZ4sXf9SJCp7BdM= X-Google-Smtp-Source: ADFU+vvxSPaWv4tBpO5i7RMaYY3eDnGk+xIwwnnb+6Co4FNBIO7VuuPcyNLUArribUaZTbJTOeXpZA== X-Received: by 2002:ac2:4552:: with SMTP id j18mr3054551lfm.89.1584644663187; Thu, 19 Mar 2020 12:04:23 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:22 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 11/12] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Date: Thu, 19 Mar 2020 22:02:28 +0300 Message-Id: <20200319190229.32200-12-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Set min/max voltage and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 45ef6002b225..a143cac22340 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1806,9 +1806,14 @@ vdd2_reg: vdd2 { vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; vio_reg: vio { @@ -1868,17 +1873,22 @@ ldo8_reg: ldo8 { }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; + + nvidia,tegra-core-regulator; }; }; From patchwork Thu Mar 19 19:02:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11447879 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E79771667 for ; Thu, 19 Mar 2020 19:04:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C70D62072C for ; Thu, 19 Mar 2020 19:04:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="La/uSPx8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727800AbgCSTE2 (ORCPT ); Thu, 19 Mar 2020 15:04:28 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:35735 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727605AbgCSTE2 (ORCPT ); Thu, 19 Mar 2020 15:04:28 -0400 Received: by mail-lf1-f65.google.com with SMTP id m15so2585204lfp.2; Thu, 19 Mar 2020 12:04:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FzD7KM1adJ8Gdad+SjbdNnB2giwK8d8O4lhpA1iChjI=; b=La/uSPx8FTVei4FU1VbWMVxuNbaBvJfMTXeORDKylSu+QXDz+dxViJJlI31XLVT5fl KADAGdkDgWWfN63q0601+IsmlJVBm4EHCl4LWxvjMiOf255nzjLer+RTZqMkhVzSe0rM Q0sMbTnR6J+HgVFsZOYnjh+4FApTXfv0TxEqfTLQRg72QMPTrWcSpoZxdp2g8SkxFxs+ dLKBK4l0yEs7mnnMHD07skmYV9KkeYkvJjmLun/S1cWMHO+dPSK+yDD01dVeQQOrn/84 tnrh/Kws8GJU+XW2RSWWpqwa/Itc5fa0fkbV10PDe21uUPITgwmZqCJ3jnQrf3XAySqP m0Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FzD7KM1adJ8Gdad+SjbdNnB2giwK8d8O4lhpA1iChjI=; b=X9MMtvrhf7ElfqQipc/TAcQaw9SHQUUcHvJNKt5cVhmAYir6jRQ57j20LWXQiLz/Tu 4xh8xSG1nGIkrRoFbAxi//UgBEO5X1tpDyMPS97oMdGPoKnYZc0Dc/Hyrh4cxmhaBVBQ xODKCKgDV1xwjKbvV8MFw73OcS8UbVXSLxBWBOzbxjLJDp0cgVbkbJ0cH1EEOr8hXy+n XdP8inDcZLICnkMp3d1bzzWJPPpJgv605MmmajS/wgG7INJMMVefA/O24dv44oHj4FhO 2bTYPXS3OHvGpVo9TLjGtBF7qWbJDSXqXaTzEfpc5sPOidoKkXp7qAnL3S7UsNHIYh4t kjuA== X-Gm-Message-State: ANhLgQ0LDqDBMI5dYhZJyF/x0FjVO454urARoIHxQ8sk3v4XqV35Al5W JbreBYcRcml/Px5zyLTxXpI= X-Google-Smtp-Source: ADFU+vvXgwoXHt8F4Hhxl+v/+A9sCmOkV1/dC6+JllXYIW1tUhx3W7HUxzuvar+MVCBV61kah2kmcA== X-Received: by 2002:a05:6512:68b:: with SMTP id t11mr3063580lfe.214.1584644664509; Thu, 19 Mar 2020 12:04:24 -0700 (PDT) Received: from localhost.localdomain (94-29-39-224.dynamic.spd-mgts.ru. [94.29.39.224]) by smtp.gmail.com with ESMTPSA id k14sm2025380lfg.96.2020.03.19.12.04.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2020 12:04:23 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , =?utf-8?b?TWljaGHFgiBNaXJv?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 12/12] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Date: Thu, 19 Mar 2020 22:02:29 +0300 Message-Id: <20200319190229.32200-13-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200319190229.32200-1-digetx@gmail.com> References: <20200319190229.32200-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index a143cac22340..6b6fd8a8058f 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" / { model = "NVIDIA Tegra30 Beaver evaluation board"; @@ -2130,4 +2132,26 @@ sound { assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, <&tegra_car TEGRA30_CLK_EXTERN1>; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };