From patchwork Fri Mar 20 17:02:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11449915 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10B9E913 for ; Fri, 20 Mar 2020 17:03:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D1A1520767 for ; Fri, 20 Mar 2020 17:03:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723795; bh=UITXrzB9HG0g5JWLKcduKlakk3aswFpBvQy9n9HWx98=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=JPMCry/cKO0D4VmC3NY06YFP6IAO1c483Ga6RjnL4DR0ucyI4JB4zsVHDWJWlG33T ZNDV9HWNeYoUUfoLjVxgsMz+jKh3DmuOBFYS1vK+WXMysyOCkrekqzMOjusaJux4VL WIaxZOKBA3ELDEBkMvo7fopbZ516F68myIgORxYE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727194AbgCTRDA (ORCPT ); Fri, 20 Mar 2020 13:03:00 -0400 Received: from mail.kernel.org ([198.145.29.99]:40542 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726953AbgCTRC7 (ORCPT ); Fri, 20 Mar 2020 13:02:59 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4E1152078A; Fri, 20 Mar 2020 17:02:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723778; bh=UITXrzB9HG0g5JWLKcduKlakk3aswFpBvQy9n9HWx98=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HAvRsesge6IwBepiK18PUMcLSykEcvh1/I3a6MBwVFg/2l+ym9zV2nHmzIGjvHPUI xUQGFB1gXUsYCXsn3/E/+SjH8jCq2fF18jbdXahqAfS2zK0egBQj+l3TY107VXwFbQ HrMxjef/ajg/oZKVw76vSwZ7Tb9u6gKKxUsNGxJk= From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCHv4 1/5] clk: socfpga: stratix10: use new parent data scheme Date: Fri, 20 Mar 2020 12:02:07 -0500 Message-Id: <20200320170212.21523-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320170212.21523-1-dinguyen@kernel.org> References: <20200320170212.21523-1-dinguyen@kernel.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert, where possible, the stratix10 clock driver to the new parent data scheme by specifying the parent data for clocks that have multiple parents. Signed-off-by: Dinh Nguyen --- v4: no change v3: no change v2: add fw_name --- drivers/clk/socfpga/clk-gate-s10.c | 5 +- drivers/clk/socfpga/clk-periph-s10.c | 10 +- drivers/clk/socfpga/clk-pll-s10.c | 4 +- drivers/clk/socfpga/clk-s10.c | 160 ++++++++++++++++++++++----- drivers/clk/socfpga/stratix10-clk.h | 8 +- 5 files changed, 146 insertions(+), 41 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c index 8be4722f6064..083b2ec21fdd 100644 --- a/drivers/clk/socfpga/clk-gate-s10.c +++ b/drivers/clk/socfpga/clk-gate-s10.c @@ -70,7 +70,6 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io struct clk *clk; struct socfpga_gate_clk *socfpga_clk; struct clk_init_data init; - const char * const *parent_names = clks->parent_names; const char *parent_name = clks->parent_name; socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); @@ -108,7 +107,9 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io init.flags = clks->flags; init.num_parents = clks->num_parents; - init.parent_names = parent_names ? parent_names : &parent_name; + init.parent_names = parent_name ? &parent_name : NULL; + if (init.parent_names == NULL) + init.parent_data = clks->parent_data; socfpga_clk->hw.hw.init = &init; clk = clk_register(NULL, &socfpga_clk->hw.hw); diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c index dd6d4056e9de..397b77b89b16 100644 --- a/drivers/clk/socfpga/clk-periph-s10.c +++ b/drivers/clk/socfpga/clk-periph-s10.c @@ -81,7 +81,6 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks, struct clk_init_data init; const char *name = clks->name; const char *parent_name = clks->parent_name; - const char * const *parent_names = clks->parent_names; periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL); if (WARN_ON(!periph_clk)) @@ -94,7 +93,9 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks, init.flags = clks->flags; init.num_parents = clks->num_parents; - init.parent_names = parent_names ? parent_names : &parent_name; + init.parent_names = parent_name ? &parent_name : NULL; + if (init.parent_names == NULL) + init.parent_data = clks->parent_data; periph_clk->hw.hw.init = &init; @@ -114,7 +115,6 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks struct clk_init_data init; const char *name = clks->name; const char *parent_name = clks->parent_name; - const char * const *parent_names = clks->parent_names; periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL); if (WARN_ON(!periph_clk)) @@ -137,7 +137,9 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks init.flags = clks->flags; init.num_parents = clks->num_parents; - init.parent_names = parent_names ? parent_names : &parent_name; + init.parent_names = parent_name ? &parent_name : NULL; + if (init.parent_names == NULL) + init.parent_data = clks->parent_data; periph_clk->hw.hw.init = &init; diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index a301bb22f36c..bcd3f14e9145 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -117,7 +117,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, struct socfpga_pll *pll_clk; struct clk_init_data init; const char *name = clks->name; - const char * const *parent_names = clks->parent_names; pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); if (WARN_ON(!pll_clk)) @@ -134,7 +133,8 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, init.flags = clks->flags; init.num_parents = clks->num_parents; - init.parent_names = parent_names; + init.parent_names = NULL; + init.parent_data = clks->parent_data; pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c index dea7c6c7d269..c1dfc9b34e4e 100644 --- a/drivers/clk/socfpga/clk-s10.c +++ b/drivers/clk/socfpga/clk-s10.c @@ -12,35 +12,137 @@ #include "stratix10-clk.h" -static const char * const pll_mux[] = { "osc1", "cb-intosc-hs-div2-clk", - "f2s-free-clk",}; -static const char * const cntr_mux[] = { "main_pll", "periph_pll", - "osc1", "cb-intosc-hs-div2-clk", - "f2s-free-clk"}; -static const char * const boot_mux[] = { "osc1", "cb-intosc-hs-div2-clk",}; - -static const char * const noc_free_mux[] = {"main_noc_base_clk", - "peri_noc_base_clk", - "osc1", "cb-intosc-hs-div2-clk", - "f2s-free-clk"}; - -static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"}; -static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"}; -static const char * const emac_ptp_free_mux[] = {"peri_emac_ptp_clk", "boot_clk"}; -static const char * const gpio_db_free_mux[] = {"peri_gpio_db_clk", "boot_clk"}; -static const char * const sdmmc_free_mux[] = {"main_sdmmc_clk", "boot_clk"}; -static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"}; -static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"}; -static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",}; - -static const char * const s2f_usr0_mux[] = {"f2s-free-clk", "boot_clk"}; -static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"}; -static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"}; - -static const char * const mpu_free_mux[] = {"main_mpu_base_clk", - "peri_mpu_base_clk", - "osc1", "cb-intosc-hs-div2-clk", - "f2s-free-clk"}; +static const struct clk_parent_data pll_mux[] = { + { .fw_name = "osc1", + .name = "osc1" }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk" }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk" }, +}; + +static const struct clk_parent_data cntr_mux[] = { + { .fw_name = "main_pll", + .name = "main_pll", }, + { .fw_name = "periph_pll", + .name = "periph_pll", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data boot_mux[] = { + { .fw_name = "osc1", + .name = "osc1" }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk" }, +}; + +static const struct clk_parent_data noc_free_mux[] = { + { .fw_name = "main_noc_base_clk", + .name = "main_noc_base_clk", }, + { .fw_name = "peri_noc_base_clk", + .name = "peri_noc_base_clk", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data emaca_free_mux[] = { + { .fw_name = "peri_emaca_clk", + .name = "peri_emaca_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data emacb_free_mux[] = { + { .fw_name = "peri_emacb_clk", + .name = "peri_emacb_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data emac_ptp_free_mux[] = { + { .fw_name = "peri_emac_ptp_clk", + .name = "peri_emac_ptp_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data gpio_db_free_mux[] = { + { .fw_name = "peri_gpio_db_clk", + .name = "peri_gpio_db_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data sdmmc_free_mux[] = { + { .fw_name = "main_sdmmc_clk", + .name = "main_sdmmc_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data s2f_usr1_free_mux[] = { + { .fw_name = "peri_s2f_usr1_clk", + .name = "peri_s2f_usr1_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data psi_ref_free_mux[] = { + { .fw_name = "peri_psi_ref_clk", + .name = "peri_psi_ref_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data mpu_mux[] = { + { .fw_name = "mpu_free_clk", + .name = "mpu_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data s2f_usr0_mux[] = { + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data emac_mux[] = { + { .fw_name = "emaca_free_clk", + .name = "emaca_free_clk", }, + { .fw_name = "emacb_free_clk", + .name = "emacb_free_clk", }, +}; + +static const struct clk_parent_data noc_mux[] = { + { .fw_name = "noc_free_clk", + .name = "noc_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data mpu_free_mux[] = { + { .fw_name = "main_mpu_base_clk", + .name = "main_mpu_base_clk", }, + { .fw_name = "peri_mpu_base_clk", + .name = "peri_mpu_base_clk", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; /* clocks in AO (always on) controller */ static const struct stratix10_pll_clock s10_pll_clks[] = { diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h index fcabef42249c..ffbd1fb2c8ef 100644 --- a/drivers/clk/socfpga/stratix10-clk.h +++ b/drivers/clk/socfpga/stratix10-clk.h @@ -14,7 +14,7 @@ struct stratix10_clock_data { struct stratix10_pll_clock { unsigned int id; const char *name; - const char *const *parent_names; + const struct clk_parent_data *parent_data; u8 num_parents; unsigned long flags; unsigned long offset; @@ -24,7 +24,7 @@ struct stratix10_perip_c_clock { unsigned int id; const char *name; const char *parent_name; - const char *const *parent_names; + const struct clk_parent_data *parent_data; u8 num_parents; unsigned long flags; unsigned long offset; @@ -34,7 +34,7 @@ struct stratix10_perip_cnt_clock { unsigned int id; const char *name; const char *parent_name; - const char *const *parent_names; + const struct clk_parent_data *parent_data; u8 num_parents; unsigned long flags; unsigned long offset; @@ -47,7 +47,7 @@ struct stratix10_gate_clock { unsigned int id; const char *name; const char *parent_name; - const char *const *parent_names; + const struct clk_parent_data *parent_data; u8 num_parents; unsigned long flags; unsigned long gate_reg; From patchwork Fri Mar 20 17:02:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11449919 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB5041668 for ; Fri, 20 Mar 2020 17:03:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CB3B420777 for ; Fri, 20 Mar 2020 17:03:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723797; bh=nGNWNe4gb5SNLtQ25FhIgpIFgzRIf+L0AGCdRSLeuP4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=NUqonjlgIR3gftHra+hnxJ3pQIzu85lA7IbLkG474tsYxBSSbJcNkQO2/HpyWf8fi otgXfdQpDoXpsVGv8iee6M6C5SSR9Ozats1aTb0lVt4i56YNxhQZkhVJ8OIj19wBgl mknffgwvQq0yUNzxIzCPirNiL2Azvt1ZflS45X6s= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727560AbgCTRDR (ORCPT ); Fri, 20 Mar 2020 13:03:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:40588 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727550AbgCTRDA (ORCPT ); Fri, 20 Mar 2020 13:03:00 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5BA3C2076F; Fri, 20 Mar 2020 17:02:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723779; bh=nGNWNe4gb5SNLtQ25FhIgpIFgzRIf+L0AGCdRSLeuP4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A3ZmPKVIQtj8lobfxYDECKYDuHJ4J7xjtiXmwVCtZa6w86HHju4vFQGQN0OzrQpFd Iv5Nl67LumeKcNUjLL5Tk53XyzTPesPxRc94TlfSlfQ8aYqu3BwmvJx++wTh9IIiX0 QgzrNSyJBcy2aTCZeTzcQL3nwygAowu50uOrAhDs= From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, Dinh Nguyen Subject: [PATCH 2/5] clk: socfpga: remove clk_ops enable/disable methods Date: Fri, 20 Mar 2020 12:02:08 -0500 Message-Id: <20200320170212.21523-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320170212.21523-1-dinguyen@kernel.org> References: <20200320170212.21523-1-dinguyen@kernel.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Dinh Nguyen The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them. Signed-off-by: Dinh Nguyen --- v4: no change v3: introduced --- drivers/clk/socfpga/clk-pll-a10.c | 2 -- drivers/clk/socfpga/clk-pll-s10.c | 2 -- drivers/clk/socfpga/clk-pll.c | 2 -- 3 files changed, 6 deletions(-) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 3816fc04b274..6d9395106c0c 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk = clk_register(NULL, &pll_clk->hw.hw); if (WARN_ON(IS_ERR(clk))) { diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index bcd3f14e9145..9faa80ff3b53 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk = clk_register(NULL, &pll_clk->hw.hw); if (WARN_ON(IS_ERR(clk))) { diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index dc65cc0fd3bd..a001641b2f42 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk = clk_register(NULL, &pll_clk->hw.hw); if (WARN_ON(IS_ERR(clk))) { From patchwork Fri Mar 20 17:02:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11449917 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7A007913 for ; Fri, 20 Mar 2020 17:03:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5959820777 for ; Fri, 20 Mar 2020 17:03:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723797; bh=lc8iQ1odTTopZ4PNqpMctsUDPoPbC3GQ0wUt4ERXAvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=Wg0UYYjYryyt5EPoVJoR8cZxyDRYxmfe6try/P9qYYPi7yq2MqcM2MSjdzP7wp6Vy XEsrWPSuq2hHe5OqNr7adOFTEeKj0RC5Ovw0XtohcU72/zP3Q8pefWTjqK+sOgJqOL 9Moie86mEVibiVEF10IxNa4lmTa4EN9IbHP6DD2I= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727669AbgCTRDN (ORCPT ); Fri, 20 Mar 2020 13:03:13 -0400 Received: from mail.kernel.org ([198.145.29.99]:40606 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727560AbgCTRDA (ORCPT ); Fri, 20 Mar 2020 13:03:00 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6BE8920781; Fri, 20 Mar 2020 17:02:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723780; bh=lc8iQ1odTTopZ4PNqpMctsUDPoPbC3GQ0wUt4ERXAvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qMnoMW615soDW64POvknENNvHGSJDVOVE4bmw2g0JMZESPItD3b0pksLChBn305Jo SC7uXtR/6Dr7Cm426bbftTs9jXrTpEbmM/VnIR4/MO/FMwE+M1zVRs3goTZhOWUJBq zAb7siix0JtpyYSK5Ij7Uu0tCT1V7qxWPH/JjzQU= From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, Dinh Nguyen Subject: [PATCH 3/5] clk: socfpga: add const to _ops data structures Date: Fri, 20 Mar 2020 12:02:09 -0500 Message-Id: <20200320170212.21523-4-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320170212.21523-1-dinguyen@kernel.org> References: <20200320170212.21523-1-dinguyen@kernel.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Dinh Nguyen All the static clk_ops data structure need a const. Signed-off-by: Dinh Nguyen --- v4: no change v3: introduced --- drivers/clk/socfpga/clk-pll-a10.c | 2 +- drivers/clk/socfpga/clk-pll-s10.c | 4 ++-- drivers/clk/socfpga/clk-pll.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 6d9395106c0c..db54f7d806a0 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -58,7 +58,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk) CLK_MGR_PLL_CLK_SRC_MASK; } -static struct clk_ops clk_pll_ops = { +static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, }; diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index 9faa80ff3b53..5c3e1ee44f6b 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -98,13 +98,13 @@ static int clk_pll_prepare(struct clk_hw *hwclk) return 0; } -static struct clk_ops clk_pll_ops = { +static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, .prepare = clk_pll_prepare, }; -static struct clk_ops clk_boot_ops = { +static const struct clk_ops clk_boot_ops = { .recalc_rate = clk_boot_clk_recalc_rate, .get_parent = clk_boot_get_parent, .prepare = clk_pll_prepare, diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index a001641b2f42..e5fb786843f3 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -65,7 +65,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk) CLK_MGR_PLL_CLK_SRC_MASK; } -static struct clk_ops clk_pll_ops = { +static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, }; From patchwork Fri Mar 20 17:02:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11449911 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6382214B4 for ; Fri, 20 Mar 2020 17:03:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 41E502076F for ; Fri, 20 Mar 2020 17:03:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723783; bh=Ji/Pi44Hz/cT413KkdqLBzEhDCLsBNvsODPtaDsWk/c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=1XeVVbpx+PD/gIjikUje4LDp/Wm4X90T0BdCspM3geJmB6ztBdFQ0g8b/jA7sJDNA /BZPMBYo6rrJ+CkFiLiRt6NvYombinQ/hwkbLQkfpIslzgOc6PdQZwX0WixcfYq8JH zt+9NLTSXKC92UC6fZT0PYDzjOJcLRZ8wdoyX1OM= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727582AbgCTRDC (ORCPT ); Fri, 20 Mar 2020 13:03:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:40620 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726953AbgCTRDC (ORCPT ); Fri, 20 Mar 2020 13:03:02 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8C86E20786; Fri, 20 Mar 2020 17:03:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723781; bh=Ji/Pi44Hz/cT413KkdqLBzEhDCLsBNvsODPtaDsWk/c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K9L7e++rLdFUVQAb87tHh6Tr6pfmDfMHVQh7EM5O+BAUyLdDb06dL4T+JYBZjDkDY HbhKgfWQHwjIVva+BNL3lHCB1sC3mVewS6vjLUu9M5Wg/jYt+0gg7l+dbQf2R/7YoP Fd2pXY1AUSUorV4JIwrl1KqfK3HoRKrfaX0y9vt8= From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 4/5] dt-bindings: documentation: add clock bindings information for Agilex Date: Fri, 20 Mar 2020 12:02:10 -0500 Message-Id: <20200320170212.21523-5-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320170212.21523-1-dinguyen@kernel.org> References: <20200320170212.21523-1-dinguyen@kernel.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform. Signed-off-by: Dinh Nguyen --- v4: really fix build error(comment formatting was wrong) v3: address comments from Stephen Boyd fix build error(tab removed in line 37) renamed to intel,agilex.yaml v2: convert original document to YAML --- .../bindings/clock/intel,agilex.yaml | 36 ++++++++++ include/dt-bindings/clock/agilex-clock.h | 70 +++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml create mode 100644 include/dt-bindings/clock/agilex-clock.h diff --git a/Documentation/devicetree/bindings/clock/intel,agilex.yaml b/Documentation/devicetree/bindings/clock/intel,agilex.yaml new file mode 100644 index 000000000000..5cf2ee5d6fcc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,agilex.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,agilex.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Agilex platform clock controller binding + +maintainers: + - Dinh Nguyen + +description: + The Intel Agilex Clock controller is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: intel,agilex-clkmgr + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + # Clock controller node: + - | + clkmgr: clock-controller@ffd10000 { + compatible = "intel,agilex-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h new file mode 100644 index 000000000000..f19cf8ccbdd2 --- /dev/null +++ b/include/dt-bindings/clock/agilex-clock.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019, Intel Corporation + */ + +#ifndef __AGILEX_CLOCK_H +#define __AGILEX_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX_OSC1 0 +#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX_CB_INTOSC_LS_CLK 2 +#define AGILEX_L4_SYS_FREE_CLK 3 +#define AGILEX_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX_MAIN_PLL_CLK 5 +#define AGILEX_MAIN_PLL_C0_CLK 6 +#define AGILEX_MAIN_PLL_C1_CLK 7 +#define AGILEX_MAIN_PLL_C2_CLK 8 +#define AGILEX_MAIN_PLL_C3_CLK 9 +#define AGILEX_PERIPH_PLL_CLK 10 +#define AGILEX_PERIPH_PLL_C0_CLK 11 +#define AGILEX_PERIPH_PLL_C1_CLK 12 +#define AGILEX_PERIPH_PLL_C2_CLK 13 +#define AGILEX_PERIPH_PLL_C3_CLK 14 +#define AGILEX_MPU_FREE_CLK 15 +#define AGILEX_MPU_CCU_CLK 16 +#define AGILEX_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX_L3_MAIN_FREE_CLK 18 +#define AGILEX_NOC_FREE_CLK 19 +#define AGILEX_S2F_USR0_CLK 20 +#define AGILEX_NOC_CLK 21 +#define AGILEX_EMAC_A_FREE_CLK 22 +#define AGILEX_EMAC_B_FREE_CLK 23 +#define AGILEX_EMAC_PTP_FREE_CLK 24 +#define AGILEX_GPIO_DB_FREE_CLK 25 +#define AGILEX_SDMMC_FREE_CLK 26 +#define AGILEX_S2F_USER0_FREE_CLK 27 +#define AGILEX_S2F_USER1_FREE_CLK 28 +#define AGILEX_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX_MPU_CLK 30 +#define AGILEX_MPU_L2RAM_CLK 31 +#define AGILEX_MPU_PERIPH_CLK 32 +#define AGILEX_L4_MAIN_CLK 33 +#define AGILEX_L4_MP_CLK 34 +#define AGILEX_L4_SP_CLK 35 +#define AGILEX_CS_AT_CLK 36 +#define AGILEX_CS_TRACE_CLK 37 +#define AGILEX_CS_PDBG_CLK 38 +#define AGILEX_CS_TIMER_CLK 39 +#define AGILEX_S2F_USER0_CLK 40 +#define AGILEX_EMAC0_CLK 41 +#define AGILEX_EMAC1_CLK 43 +#define AGILEX_EMAC2_CLK 44 +#define AGILEX_EMAC_PTP_CLK 45 +#define AGILEX_GPIO_DB_CLK 46 +#define AGILEX_NAND_CLK 47 +#define AGILEX_PSI_REF_CLK 48 +#define AGILEX_S2F_USER1_CLK 49 +#define AGILEX_SDMMC_CLK 50 +#define AGILEX_SPI_M_CLK 51 +#define AGILEX_USB_CLK 52 +#define AGILEX_NUM_CLKS 53 + +#endif /* __AGILEX_CLOCK_H */ From patchwork Fri Mar 20 17:02:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11449913 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2FA9114B4 for ; Fri, 20 Mar 2020 17:03:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E48B720767 for ; Fri, 20 Mar 2020 17:03:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723788; bh=hBrLxJFq/pCJo7tzbiZrMGm+GYcaamkQHQIMCA3oTXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=pXenugjJkIUt1igIhRFqp+aVxn3KfMhIXTNyH2JnYlArdjsxOCfbnUviiMFZe38cT ybzXbd2uf+QdfEUCYqwFC8d8+v/ijp/hpygRftbxGXjLGh4s4554J49Sl5TkyJVzDF MfFxrwPeAN294wKkqvQTgLfF34ymC9mtHrx3F9k0= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727618AbgCTRDD (ORCPT ); Fri, 20 Mar 2020 13:03:03 -0400 Received: from mail.kernel.org ([198.145.29.99]:40658 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727594AbgCTRDD (ORCPT ); Fri, 20 Mar 2020 13:03:03 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7F04B20784; Fri, 20 Mar 2020 17:03:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584723782; bh=hBrLxJFq/pCJo7tzbiZrMGm+GYcaamkQHQIMCA3oTXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SfiUJK+a7O6x5F3REgPLfY/FOcKbJZKYL4CKh22ezY06xFLWVsJjrJ8cQ2M3j8mSA riEV2aoeb4HaAOkM35BtgRQb5EQXN9RcVeLnvQ+08RdsA+0sH8bfsw+zv4ZpL81k1x JxVoZ2bhlo7J3r6sfkSbtC+xVd/CJrWD8pRBkvpA= From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 5/5] clk: socfpga: agilex: add clock driver for the Agilex platform Date: Fri, 20 Mar 2020 12:02:11 -0500 Message-Id: <20200320170212.21523-6-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320170212.21523-1-dinguyen@kernel.org> References: <20200320170212.21523-1-dinguyen@kernel.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org For the most part the Agilex clock structure is very similar to Stratix10, so we re-use most of the Stratix10 clock driver. Signed-off-by: Dinh Nguyen --- v4: no changes v3: Address Stephen Boyd's comments v2: update to use clk_parent_data --- drivers/clk/Makefile | 3 +- drivers/clk/socfpga/Makefile | 2 + drivers/clk/socfpga/clk-agilex.c | 454 ++++++++++++++++++++++++++++ drivers/clk/socfpga/clk-pll-s10.c | 68 +++++ drivers/clk/socfpga/stratix10-clk.h | 2 + 5 files changed, 528 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/socfpga/clk-agilex.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f4169cc2fd31..a178e4b6001f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -104,10 +104,11 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_ARCH_SIRF) += sirf/ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ +obj-$(CONFIG_ARCH_AGILEX) += socfpga/ +obj-$(CONFIG_ARCH_STRATIX10) += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_SPRD) += sprd/ obj-$(CONFIG_ARCH_STI) += st/ -obj-$(CONFIG_ARCH_STRATIX10) += socfpga/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_SUNXI_CCU) += sunxi-ng/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index ce5aa7802eb8..bf736f8d201a 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o +obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c new file mode 100644 index 000000000000..699527f7e764 --- /dev/null +++ b/drivers/clk/socfpga/clk-agilex.c @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Intel Corporation + */ +#include +#include +#include +#include +#include + +#include + +#include "stratix10-clk.h" + +static const struct clk_parent_data pll_mux[] = { + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data cntr_mux[] = { + { .fw_name = "main_pll", + .name = "main_pll", }, + { .fw_name = "periph_pll", + .name = "periph_pll", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data boot_mux[] = { + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, +}; + +static const struct clk_parent_data mpu_free_mux[] = { + { .fw_name = "main_pll_c0", + .name = "main_pll_c0", }, + { .fw_name = "peri_pll_c0", + .name = "peri_pll_c0", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data noc_free_mux[] = { + { .fw_name = "main_pll_c1", + .name = "main_pll_c1", }, + { .fw_name = "peri_pll_c1", + .name = "peri_pll_c1", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data emaca_free_mux[] = { + { .fw_name = "main_pll_c2", + .name = "main_pll_c2", }, + { .fw_name = "peri_pll_c2", + .name = "peri_pll_c2", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data emacb_free_mux[] = { + { .fw_name = "main_pll_c3", + .name = "main_pll_c3", }, + { .fw_name = "peri_pll_c3", + .name = "peri_pll_c3", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data emac_ptp_free_mux[] = { + { .fw_name = "main_pll_c3", + .name = "main_pll_c3", }, + { .fw_name = "peri_pll_c3", + .name = "peri_pll_c3", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data gpio_db_free_mux[] = { + { .fw_name = "main_pll_c3", + .name = "main_pll_c3", }, + { .fw_name = "peri_pll_c3", + .name = "peri_pll_c3", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data psi_ref_free_mux[] = { + { .fw_name = "main_pll_c3", + .name = "main_pll_c3", }, + { .fw_name = "peri_pll_c3", + .name = "peri_pll_c3", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data sdmmc_free_mux[] = { + { .fw_name = "main_pll_c3", + .name = "main_pll_c3", }, + { .fw_name = "peri_pll_c3", + .name = "peri_pll_c3", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data s2f_usr0_free_mux[] = { + { .fw_name = "main_pll_c2", + .name = "main_pll_c2", }, + { .fw_name = "peri_pll_c2", + .name = "peri_pll_c2", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data s2f_usr1_free_mux[] = { + { .fw_name = "main_pll_c2", + .name = "main_pll_c2", }, + { .fw_name = "peri_pll_c2", + .name = "peri_pll_c2", }, + { .fw_name = "osc1", + .name = "osc1", }, + { .fw_name = "cb-intosc-hs-div2-clk", + .name = "cb-intosc-hs-div2-clk", }, + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, +}; + +static const struct clk_parent_data mpu_mux[] = { + { .fw_name = "mpu_free_clk", + .name = "mpu_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data s2f_usr0_mux[] = { + { .fw_name = "f2s-free-clk", + .name = "f2s-free-clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +static const struct clk_parent_data emac_mux[] = { + { .fw_name = "emaca_free_clk", + .name = "emaca_free_clk", }, + { .fw_name = "emacb_free_clk", + .name = "emacb_free_clk", }, +}; + +static const struct clk_parent_data noc_mux[] = { + { .fw_name = "noc_free_clk", + .name = "noc_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + +/* clocks in AO (always on) controller */ +static const struct stratix10_pll_clock agilex_pll_clks[] = { + { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0, + 0x0}, + { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux), + 0, 0x48}, + { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux), + 0, 0x9c}, +}; + +static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = { + { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58}, + { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C}, + { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64}, + { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68}, + { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC}, + { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0}, + { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8}, + { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC}, +}; + +static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = { + { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux), + 0, 0x3C, 0, 0, 0}, + { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux), + 0, 0x40, 0, 0, 1}, + { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0, + 0, 4, 0, 0}, + { AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), + 0, 0, 0, 0x30, 1}, + { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux), + 0, 0xD4, 0, 0x88, 0}, + { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux), + 0, 0xD8, 0, 0x88, 1}, + { AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux, + ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2}, + { AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux, + ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3}, + { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux, + ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4}, + { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux, + ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0}, + { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux, + ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5}, + { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux, + ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6}, +}; + +static const struct stratix10_gate_clock agilex_gate_clks[] = { + { AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24, + 0, 0, 0, 0, 0x30, 0, 0}, + { AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24, + 0, 0, 0, 0, 0, 0, 4}, + { AGILEX_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x24, + 0, 0, 0, 0, 0, 0, 2}, + { AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24, + 1, 0x44, 0, 2, 0, 0, 0}, + { AGILEX_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x24, + 2, 0x44, 8, 2, 0, 0, 0}, + /* + * The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them + * being the SP timers, thus cannot get gated. + */ + { AGILEX_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x24, + 3, 0x44, 16, 2, 0, 0, 0}, + { AGILEX_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x24, + 4, 0x44, 24, 2, 0, 0, 0}, + { AGILEX_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x24, + 4, 0x44, 26, 2, 0, 0, 0}, + { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, + 4, 0x44, 28, 1, 0, 0, 0}, + { AGILEX_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x24, + 5, 0, 0, 0, 0, 0, 0}, + { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24, + 6, 0, 0, 0, 0, 0, 0}, + { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C, + 0, 0, 0, 0, 0x94, 26, 0}, + { AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C, + 1, 0, 0, 0, 0x94, 27, 0}, + { AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C, + 2, 0, 0, 0, 0x94, 28, 0}, + { AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0x7C, + 3, 0, 0, 0, 0, 0, 0}, + { AGILEX_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0x7C, + 4, 0x98, 0, 16, 0, 0, 0}, + { AGILEX_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0x7C, + 5, 0, 0, 0, 0, 0, 4}, + { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0x7C, + 6, 0, 0, 0, 0, 0, 0}, + { AGILEX_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0x7C, + 7, 0, 0, 0, 0, 0, 0}, + { AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, + 8, 0, 0, 0, 0, 0, 0}, + { AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, + 9, 0, 0, 0, 0, 0, 0}, + { AGILEX_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0x7C, + 10, 0, 0, 0, 0, 0, 0}, +}; + +static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks, + int nums, struct stratix10_clock_data *data) +{ + struct clk *clk; + void __iomem *base = data->base; + int i; + + for (i = 0; i < nums; i++) { + clk = s10_register_periph(&clks[i], base); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + continue; + } + data->clk_data.clks[clks[i].id] = clk; + } + return 0; +} + +static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks, + int nums, struct stratix10_clock_data *data) +{ + struct clk *clk; + void __iomem *base = data->base; + int i; + + for (i = 0; i < nums; i++) { + clk = s10_register_cnt_periph(&clks[i], base); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + continue; + } + data->clk_data.clks[clks[i].id] = clk; + } + + return 0; +} + +static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, int nums, struct stratix10_clock_data *data) +{ + struct clk *clk; + void __iomem *base = data->base; + int i; + + for (i = 0; i < nums; i++) { + clk = s10_register_gate(&clks[i], base); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + continue; + } + data->clk_data.clks[clks[i].id] = clk; + } + + return 0; +} + +static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks, + int nums, struct stratix10_clock_data *data) +{ + struct clk *clk; + void __iomem *base = data->base; + int i; + + for (i = 0; i < nums; i++) { + clk = agilex_register_pll(&clks[i], base); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + continue; + } + data->clk_data.clks[clks[i].id] = clk; + } + + return 0; +} + +static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev, + int nr_clks) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct stratix10_clock_data *clk_data; + struct clk **clk_table; + struct resource *res; + void __iomem *base; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return ERR_CAST(base); + + clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + clk_data->base = base; + clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL); + if (!clk_table) + return ERR_PTR(-ENOMEM); + + clk_data->clk_data.clks = clk_table; + clk_data->clk_data.clk_num = nr_clks; + ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + return ERR_PTR(ret); + + return clk_data; +} + +static int agilex_clkmgr_probe(struct platform_device *pdev) +{ + struct stratix10_clock_data *clk_data; + + clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS); + if (IS_ERR(clk_data)) + return PTR_ERR(clk_data); + + agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data); + + agilex_clk_register_c_perip(agilex_main_perip_c_clks, + ARRAY_SIZE(agilex_main_perip_c_clks), clk_data); + + agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks, + ARRAY_SIZE(agilex_main_perip_cnt_clks), + clk_data); + + agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks), + clk_data); + return 0; +} + +static const struct of_device_id agilex_clkmgr_match_table[] = { + { .compatible = "intel,agilex-clkmgr", + .data = agilex_clkmgr_probe }, + { } +}; + +static struct platform_driver agilex_clkmgr_driver = { + .probe = agilex_clkmgr_probe, + .driver = { + .name = "agilex-clkmgr", + .suppress_bind_attrs = true, + .of_match_table = agilex_clkmgr_match_table, + }, +}; + +static int __init agilex_clk_init(void) +{ + return platform_driver_register(&agilex_clkmgr_driver); +} +core_initcall(agilex_clk_init); diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index 5c3e1ee44f6b..4e268953b7da 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -18,8 +18,12 @@ #define SOCFPGA_PLL_RESET_MASK 0x2 #define SOCFPGA_PLL_REFDIV_MASK 0x00003F00 #define SOCFPGA_PLL_REFDIV_SHIFT 8 +#define SOCFPGA_PLL_AREFDIV_MASK 0x00000F00 +#define SOCFPGA_PLL_DREFDIV_MASK 0x00003000 +#define SOCFPGA_PLL_DREFDIV_SHIFT 12 #define SOCFPGA_PLL_MDIV_MASK 0xFF000000 #define SOCFPGA_PLL_MDIV_SHIFT 24 +#define SOCFPGA_AGILEX_PLL_MDIV_MASK 0x000003FF #define SWCTRLBTCLKSEL_MASK 0x200 #define SWCTRLBTCLKSEL_SHIFT 9 @@ -27,6 +31,27 @@ #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw) +static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk, + unsigned long parent_rate) +{ + struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); + unsigned long arefdiv, reg, mdiv; + unsigned long long vco_freq; + + /* read VCO1 reg for numerator and denominator */ + reg = readl(socfpgaclk->hw.reg); + arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT; + + vco_freq = (unsigned long long)parent_rate / arefdiv; + + /* Read mdiv and fdiv from the fdbck register */ + reg = readl(socfpgaclk->hw.reg + 0x24); + mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK; + + vco_freq = (unsigned long long)vco_freq * mdiv; + return (unsigned long)vco_freq; +} + static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) { @@ -98,6 +123,12 @@ static int clk_pll_prepare(struct clk_hw *hwclk) return 0; } +static const struct clk_ops agilex_clk_pll_ops = { + .recalc_rate = agilex_clk_pll_recalc_rate, + .get_parent = clk_pll_get_parent, + .prepare = clk_pll_prepare, +}; + static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, @@ -146,3 +177,40 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, } return clk; } + +struct clk *agilex_register_pll(const struct stratix10_pll_clock *clks, + void __iomem *reg) +{ + struct clk *clk; + struct socfpga_pll *pll_clk; + struct clk_init_data init; + const char *name = clks->name; + + pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); + if (WARN_ON(!pll_clk)) + return NULL; + + pll_clk->hw.reg = reg + clks->offset; + + if (streq(name, SOCFPGA_BOOT_CLK)) + init.ops = &clk_boot_ops; + else + init.ops = &agilex_clk_pll_ops; + + init.name = name; + init.flags = clks->flags; + + init.num_parents = clks->num_parents; + init.parent_names = NULL; + init.parent_data = clks->parent_data; + pll_clk->hw.hw.init = &init; + + pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; + + clk = clk_register(NULL, &pll_clk->hw.hw); + if (WARN_ON(IS_ERR(clk))) { + kfree(pll_clk); + return NULL; + } + return clk; +} diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h index ffbd1fb2c8ef..f9d5d724c694 100644 --- a/drivers/clk/socfpga/stratix10-clk.h +++ b/drivers/clk/socfpga/stratix10-clk.h @@ -62,6 +62,8 @@ struct stratix10_gate_clock { struct clk *s10_register_pll(const struct stratix10_pll_clock *, void __iomem *); +struct clk *agilex_register_pll(const struct stratix10_pll_clock *, + void __iomem *); struct clk *s10_register_periph(const struct stratix10_perip_c_clock *, void __iomem *); struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,