From patchwork Fri Mar 20 18:34:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450049 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 745771667 for ; Fri, 20 Mar 2020 18:35:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 52BD620784 for ; Fri, 20 Mar 2020 18:35:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hj0Gjr3w" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727279AbgCTSfF (ORCPT ); Fri, 20 Mar 2020 14:35:05 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:35005 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727178AbgCTSfF (ORCPT ); Fri, 20 Mar 2020 14:35:05 -0400 Received: by mail-ed1-f65.google.com with SMTP id a20so8339174edj.2; Fri, 20 Mar 2020 11:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=PjUrNIBTHiGRlXltBoWnInenBouwnlz0OaURyGduRc8=; b=hj0Gjr3w7oKqG+/bfA2jN473nqLzbMpQSum+y5Z1mOejc+pz4plw/F1SS2BcZJPin1 3hSggqTP+ZKnFEorHvTKwBJGC6D8k1fe3lMlhlWO+2edrUDp6pA4DxdGmDFa6YWp2ZwF PIn2YbAmk2uwlWE9sBGAJdkhdTPUQxPi6XtXdgjZ6QP5+rhGhBPpJsuQ7UYyWxVO5xQE yNi9T6f9F575tiLs0KnMRN71falp6acddOa3YP63mskZDGNGzTPlJ7OVRd/JwfMH7aYs YOXt/F81Or2DZUD4kotD8mSSK6xX1Fy4UV9u3qjEWjQOyhgPsmTL8MQRZ6luhDX5Cby1 Z6tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=PjUrNIBTHiGRlXltBoWnInenBouwnlz0OaURyGduRc8=; b=V//eSk71K+jJ0M1/9cIqbRYeYz1ReHdm/nG1efntCPLms48H66U9AlhCZqZXVwogur YoteZvx8qjlmVF4TbxG1nxK/CFezhyR+wcdqbBTF48c4yAcryDDaxikRjA7xRFfuM2+/ oe6EANzOl6D05Fz3hIVqWdWHvL2ODrevJqS+y2dEevbCA595XJ2WMQOqUP2sHOOkW6DZ 9SBIMIWIkaERxvJI5ARdmmYpR+4rCVfa1hHPwvve+CMiY5W40ovsZzfYFkAYYU5dW663 cbkl6HEpaeN0nbGqPd6kgmMiJAv0TIRu88l6u2KTc+0w+urBx1h4eM1LwxdZkUe70VwJ YRwQ== X-Gm-Message-State: ANhLgQ14xGU74G0MIYLKqQZbUVZE6IWltNkoag/2LwmBF2WK4jysqrE9 5AmCdCtaAAKmYIXnU4hTT5A= X-Google-Smtp-Source: ADFU+vvHAO5MesgNDreNBT9MSjyANUd4rdBiCnfzEigRlv0T/4Z7d4CGHTe31T+t2ccvEkSD2uqiZQ== X-Received: by 2002:a50:cdc7:: with SMTP id h7mr9669266edj.208.1584729302756; Fri, 20 Mar 2020 11:35:02 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:02 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Sham Muthayyan , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/12] pcie: qcom: add missing ipq806x clocks in pcie driver Date: Fri, 20 Mar 2020 19:34:43 +0100 Message-Id: <20200320183455.21311-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Aux and Ref clk are missing in pcie qcom driver. Add support in the driver to fix pcie inizialization in ipq806x Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 5ea527a6bd9f..f958c535de6e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 { struct clk *iface_clk; struct clk *core_clk; struct clk *phy_clk; + struct clk *aux_clk; + struct clk *ref_clk; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->phy_clk)) return PTR_ERR(res->phy_clk); + res->aux_clk = devm_clk_get(dev, "aux"); + if (IS_ERR(res->aux_clk)) + return PTR_ERR(res->aux_clk); + + res->ref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(res->ref_clk)) + return PTR_ERR(res->ref_clk); + res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) return PTR_ERR(res->pci_reset); @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); + clk_disable_unprepare(res->aux_clk); + clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_assert_ahb; } + ret = clk_prepare_enable(res->core_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable core clock\n"); + goto err_clk_core; + } + ret = clk_prepare_enable(res->phy_clk); if (ret) { dev_err(dev, "cannot prepare/enable phy clock\n"); goto err_clk_phy; } - ret = clk_prepare_enable(res->core_clk); + ret = clk_prepare_enable(res->aux_clk); if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; + dev_err(dev, "cannot prepare/enable aux clock\n"); + goto err_clk_aux; + } + + ret = clk_prepare_enable(res->ref_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable ref clock\n"); + goto err_clk_ref; } ret = reset_control_deassert(res->ahb_reset); @@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; err_deassert_ahb: - clk_disable_unprepare(res->core_clk); -err_clk_core: + clk_disable_unprepare(res->ref_clk); +err_clk_ref: + clk_disable_unprepare(res->aux_clk); +err_clk_aux: clk_disable_unprepare(res->phy_clk); err_clk_phy: + clk_disable_unprepare(res->core_clk); +err_clk_core: clk_disable_unprepare(res->iface_clk); err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); From patchwork Fri Mar 20 18:34:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450095 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 465261667 for ; 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:06 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/12] devicetree: bindings: pci: add missing clks to qcom,pcie Date: Fri, 20 Mar 2020 19:34:44 +0100 Message-Id: <20200320183455.21311-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document missing clks used in ipq806x soc Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 981b4de12807..becdbdc0fffa 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -90,6 +90,8 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "aux" Clocks the pcie AUX block + - "ref" Clocks the pcie ref block - clock-names: Usage: required for apq8084/ipq4019 Value type: @@ -277,8 +279,10 @@ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>; - clock-names = "core", "iface", "phy"; + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; resets = <&gcc PCIE_ACLK_RESET>, <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, From patchwork Fri Mar 20 18:34:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450091 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0171B17E6 for ; Fri, 20 Mar 2020 18:36:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D472C20781 for ; Fri, 20 Mar 2020 18:36:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KXlg6pGG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727413AbgCTSfO (ORCPT ); Fri, 20 Mar 2020 14:35:14 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:37987 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727178AbgCTSfN (ORCPT ); Fri, 20 Mar 2020 14:35:13 -0400 Received: by mail-ed1-f67.google.com with SMTP id h5so8305505edn.5; Fri, 20 Mar 2020 11:35:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yRo9nDnkvpVgGMO52y9SDq2QLhuKK/RpwLheS8dxEdo=; b=KXlg6pGGu7+fH+4J6SwTdmp3qRTOwbLeFyRc9llXU6NFZtCXG6y1ZL9UP42MReM4hK Gn/CMltyY5HsmEeAnqsYpo9Ip2LyDJJQEBBQAMVbxRKt4I97B6B57gFesIt5eNQ61w00 AkUauYmKgMfzt26t/5/AZ9GRZ/FbOTwD1W3YC5JuyxHuPhR11Y/NZRp6eFldsyERVl+7 hwsGD/XchuHDwV/bjzdD/Rfc0QAfnrY5MEqIK2hsPk3FNC14QwvYigVo3uGexIeceUkc 8uEeuY3QTRDvx1me//9PydnQaziaISGFo1jvXtIstLEbQmrFJGhjecRBlSEGWIhnYvLD MLew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yRo9nDnkvpVgGMO52y9SDq2QLhuKK/RpwLheS8dxEdo=; b=kAt7wOm9tsUCIE5axI+IDHX9uPGQmisaO06YdOkJxlK2Ikt7wOuEjQvrheb7Zi1dk4 Pn6CGyd0WwR2XPIgoquOZisBblf2fm7iH3C8dmT2XlBmKP7H56iOE1fP7yUwMvbu1WDg xiKbn9ty+DB5iJ9WDg6XeMEnqJXQVqUAgOuCcT593ewZCPSHmJn4NgNH5FW9su5sU34C 1zWnbM9SUPVwsCbTLxR+HMfWECj2KZbhivpKQhW0KrYf8dwlYhY0wNW2ATktOuI1KTyg oYW9aQLIbP4mR4s3cA4lm3qHSP3BIPV2D2l5p5ppDnG/x+srthHEhMBdZjLZDizY8GTL d4oQ== X-Gm-Message-State: ANhLgQ2KJ8lZhl79TvAmgjgASL8mGl3ugGrPEgkYnQFL/rmF20lqRSPL 5ISeAxxlNy9qbaNNB7QnJGA= X-Google-Smtp-Source: ADFU+vvNTp8sqzvhS1hnXVHuvIPBtK5wJsYEAeb0/JoRA6lZ9eu2HocXv6m9ZSeJEMfzrbSHH628gw== X-Received: by 2002:a50:a9a6:: with SMTP id n35mr671753edc.57.1584729310266; Fri, 20 Mar 2020 11:35:10 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:09 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Abhishek Sahu , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/12] pcie: qcom: change duplicate pci reset to phy reset Date: Fri, 20 Mar 2020 19:34:45 +0100 Message-Id: <20200320183455.21311-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Abhishek Sahu The deinit issues reset_control_assert for pci twice and does not contain phy reset. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f958c535de6e..1fcc7fed8443 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -284,7 +284,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); - reset_control_assert(res->pci_reset); + reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); From patchwork Fri Mar 20 18:34:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450089 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 49D141864 for ; Fri, 20 Mar 2020 18:36:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 28DD120842 for ; Fri, 20 Mar 2020 18:36:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="g9rdUihT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727441AbgCTSfP (ORCPT ); Fri, 20 Mar 2020 14:35:15 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:36074 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727411AbgCTSfP (ORCPT ); Fri, 20 Mar 2020 14:35:15 -0400 Received: by mail-ed1-f66.google.com with SMTP id b18so8337646edu.3; Fri, 20 Mar 2020 11:35:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QTJvUrUZh6Asz0TpkI0T8aoHyYL8TgG05bomTjzSOyM=; b=g9rdUihThyk73P8wLgLB9/dtJ7c1YiBnldNvV9so+qC4nsHi9lh0LbppH794U4VT5v hTaDpUpZf8eWS1bzyjnhxG4Z8aWizFPUb3xj0BnO84gyg19I+Wu5oh3Ny9as6sNLgUaA jGe7oqDk6xFKGtOIjkDYvWI8WCT82VCDW4vF0MnQhZiZV8E2WTKgavcar1DtRMaQT4A9 Vd/yzR/eXJls2bPqU0kyMYj098DlUf5E1U30qlGAkINvH/L7wj3ygwdpmUlPD8nuLmEU ZckL6BCB8dDIjUH7kIX/oqtrn3c8DYx7bWlmG8yHgRHFFICq86/5TY864wIGyd/l/jzV 74YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QTJvUrUZh6Asz0TpkI0T8aoHyYL8TgG05bomTjzSOyM=; b=WUB0A8e/DbtHtVMNtpVCgzaJRrwlLmwQt6ZrjR9k1zuTEJ3hrPYjNrOy+71/vS0kE9 94mfKSvaxfzLGsRbEqKL7X5Te9JCuPeQ2Q+8U76UR9QDq2Bkon81aT1FUuLuQ+nb2nEL 8AO4NhNQeCAP3Frkolvp4KxtET0XqZY205sC+PekM0l5nOxSyhJtrbFZS2RCGDPc4vNW Ll/9i7ZT5ruby89ozT9cYdHLCt2sU6yEUwJLm2V8ze9eyuVQZGDLNi8xl7oQh7SUxq9i nYAX9vqkyolJ6Bhk9NaYsq/OxPHls/HhoQzZmVgf0MR+SQ5b6K/1YN/OjMxftPJ7awS7 04Bg== X-Gm-Message-State: ANhLgQ0ghMZBDrwYzl6qaCPbrgiefa1+1Q75OuAoet7/6Iu+rCr6YRgQ LQRK1v2vxjbnNGwoKXVsuuM= X-Google-Smtp-Source: ADFU+vslcEfYS+a701OQE8C0wc0N89UVXf8ty5raYXpe2pQxadJpErSZ7aVEf2b+Kh2eOVhdLyGMMQ== X-Received: by 2002:a05:6402:369:: with SMTP id s9mr9384490edw.349.1584729313054; Fri, 20 Mar 2020 11:35:13 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:12 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Abhishek Sahu , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/12] pcie: qcom: Fixed pcie_phy_clk branch issue Date: Fri, 20 Mar 2020 19:34:46 +0100 Message-Id: <20200320183455.21311-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Following backtraces are observed in PCIe deinit operation. Hardware name: Qualcomm (Flattened Device Tree) (unwind_backtrace) from [] (show_stack+0x10/0x14) (show_stack) from [] (dump_stack+0x84/0x98) (dump_stack) from [] (warn_slowpath_common+0x9c/0xb8) (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) (warn_slowpath_fmt) from [] (clk_branch_wait+0x114/0x120) (clk_branch_wait) from [] (clk_core_disable+0xd0/0x1f4) (clk_core_disable) from [] (clk_disable+0x24/0x30) (clk_disable) from [] (qcom_pcie_deinit_v0+0x6c/0xb8) (qcom_pcie_deinit_v0) from [] (qcom_pcie_host_init+0xe0/0xe8) (qcom_pcie_host_init) from [] (dw_pcie_host_init+0x3b0/0x538) (dw_pcie_host_init) from [] (qcom_pcie_probe+0x20c/0x2e4) pcie_phy_clk is generated for PCIe controller itself and the GCC controls its branch operation. This error is coming since the assert operations turn off the parent clock before branch clock. Now this patch moves clk_disable_unprepare before assert operations. Similarly, during probe function, the clock branch operation should be done after dessert operation. Currently, it does not generate any error since bootloader enables the pcie_phy_clk but the same error is coming during probe, if bootloader disables pcie_phy_clk. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 1fcc7fed8443..596731b54728 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -280,6 +280,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + clk_disable_unprepare(res->phy_clk); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); @@ -287,7 +288,6 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); clk_disable_unprepare(res->aux_clk); clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_clk_core; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - ret = clk_prepare_enable(res->aux_clk); if (ret) { dev_err(dev, "cannot prepare/enable aux clock\n"); @@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } + ret = clk_prepare_enable(res->phy_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable phy clock\n"); + goto err_deassert_ahb; + } + /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) err_clk_ref: clk_disable_unprepare(res->aux_clk); err_clk_aux: - clk_disable_unprepare(res->phy_clk); -err_clk_phy: clk_disable_unprepare(res->core_clk); err_clk_core: clk_disable_unprepare(res->iface_clk); From patchwork Fri Mar 20 18:34:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450057 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC66A1864 for ; Fri, 20 Mar 2020 18:35:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8CF6820842 for ; Fri, 20 Mar 2020 18:35:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HpNpcc7q" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727411AbgCTSfS (ORCPT ); Fri, 20 Mar 2020 14:35:18 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:40258 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727456AbgCTSfR (ORCPT ); Fri, 20 Mar 2020 14:35:17 -0400 Received: by mail-ed1-f68.google.com with SMTP id w26so1961452edu.7; Fri, 20 Mar 2020 11:35:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QPvURtOImvg+Fq3I5SMUmHKPxQmmWBaUP6s2M4NwlZQ=; b=HpNpcc7qIwDoPMdGsc7NGbMImJD6DrdDaZK3Yy5xtHZ+QwAgWvRAW/eRcCFOqtuvuz dXk086IKz5GKIjErWGoYGuxjg3bFGyJiF0AhV4oUD+UrBImxrymFC3098ylRAoY1mGE+ sBrbaOOKqPVVckbBkMCmL0HtJ6xBJ4dIECM+HNPfJ5UA0HhplF6yLyoA6ANmnMt6xfD0 3gSU1aWAEmaaNaaobnhprPixS//fWvvlcF2In7L2PHkX4hNfp0mfYvX3X9unC4VV61Sd +SghZXK1iKCo8wiPfIY6+paNExGu9PF9sNVZGolUPvy7cd0mmkgUEFGO/B99iGcrq4xX 0akg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QPvURtOImvg+Fq3I5SMUmHKPxQmmWBaUP6s2M4NwlZQ=; b=XsxrCDewa3Mh5PMfgleBUsjaLpWv+sCsIYiKM+O5h2YlvYPJ0dIl2feWswyJGWvKqb ZRX9HBBJCZVHs8mFSJlliP0a6KwnYcBa6L3hiBb+exrKrQvtQdkapnK0j2BFk3x37WEd TO24eyvWPWzK1Bnvfj23seRzfdJm5n1oJS/yTENIh72JBGTrCnfq4Efi9bekOTn7shTn G67GwyqL91LZKxDfLqCfopVWIZC4VmiWk4hkUpFQ18m2yHbrCIDagsWBYnUWZcCyad25 WWc9w/9+tR75NtxcwuYP0bJKalS6E2XUWBIXiaH93L6foJyUORF4cE343EqcYIRvBKkB 5qEg== X-Gm-Message-State: ANhLgQ24MAWcZ1kvi3xP2c9zm4SQnAnourue5RAlDuETPvQKidbBQB5j uXKtp6tcTD5i5COGTfJn8nQ= X-Google-Smtp-Source: ADFU+vuXYF2hhGnUijVEzjlj+CFBaGaMl7Om2d8MHAJtuTemqOv3c30/xBnTBrDGKHk7vzi8VxgW9A== X-Received: by 2002:a17:906:34d3:: with SMTP id h19mr9707812ejb.22.1584729315572; Fri, 20 Mar 2020 11:35:15 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:15 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Sham Muthayyan , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/12] pcie: qcom: add missing reset for ipq806x Date: Fri, 20 Mar 2020 19:34:47 +0100 Message-Id: <20200320183455.21311-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing ext reset used by ipq806x soc in pcie qcom driver Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 596731b54728..ecc22fd27ea6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *ahb_reset; struct reset_control *por_reset; struct reset_control *phy_reset; + struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->por_reset)) return PTR_ERR(res->por_reset); + res->ext_reset = devm_reset_control_get(dev, "ext"); + if (IS_ERR(res->ext_reset)) + return PTR_ERR(res->ext_reset); + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); @@ -301,18 +307,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) u32 val; int ret; + ret = reset_control_assert(res->ahb_reset); + if (ret) { + dev_err(dev, "cannot assert ahb reset\n"); + return ret; + } + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); if (ret < 0) { dev_err(dev, "cannot enable regulators\n"); return ret; } - ret = reset_control_assert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); - goto err_assert_ahb; - } - ret = clk_prepare_enable(res->iface_clk); if (ret) { dev_err(dev, "cannot prepare/enable iface clock\n"); @@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } + ret = reset_control_deassert(res->ext_reset); + if (ret) { + dev_err(dev, "cannot assert ext reset\n"); + goto err_deassert_ahb; + } + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0); From patchwork Fri Mar 20 18:34:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450085 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B4D5317E6 for ; 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:17 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/12] devicetree: bindings: pci: add ext reset to qcom,pcie Date: Fri, 20 Mar 2020 19:34:48 +0100 Message-Id: <20200320183455.21311-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document ext reset used in ipq806x soc by qcom pcie driver Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index becdbdc0fffa..6efcef040741 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,7 @@ - "pwr" PWR reset - "ahb" AHB reset - "phy_ahb" PHY AHB reset + - "ext" EXT reset - reset-names: Usage: required for ipq8074 @@ -287,8 +288,9 @@ <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; }; From patchwork Fri Mar 20 18:34:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450059 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC0291667 for ; Fri, 20 Mar 2020 18:35:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7F21620782 for ; Fri, 20 Mar 2020 18:35:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Yr8IMgYk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727516AbgCTSf0 (ORCPT ); Fri, 20 Mar 2020 14:35:26 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:35068 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725446AbgCTSfX (ORCPT ); Fri, 20 Mar 2020 14:35:23 -0400 Received: by mail-ed1-f66.google.com with SMTP id a20so8340211edj.2; Fri, 20 Mar 2020 11:35:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WNYRUFULee31Lm1KjTnY4zWnox8RMFbDtxuR2OFtEzI=; b=Yr8IMgYk/OnIfQBt54c2/wu5QbUMQsW4KWuVelx32qiWM+p71p49krEnEI3faLzgNo T1CcLUikSCzQDVsWxrismxeWwBSBl0F2FjmttruqEgh5Wq0WH33EVpqyNWlSC14YwgDr skKYJO/CLYDZIhetBwCNNXsfyCOWqDHa54EAM5DDtW6gdtNNVYs+XaOOxOCoMh7P8fLK vHNT1iSae8VqX+2N0CuLRBQ+ulZ+oOgXMhERNIaLhXgWRPVe+rcNhS9S10udY7ZNbNhl Mkg/8LGglLDipNrve1h1pRvBk86x068vnRkj7Gsg6zaK7Tgkk+O4651hw8MsqyK9CQ9q HD5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WNYRUFULee31Lm1KjTnY4zWnox8RMFbDtxuR2OFtEzI=; b=W8a/uyud3y1w4UlQDV38g3TOctGm6OhMaCNXE4td7wZibxHnmgH49qCVpBAfI6qbzA 4s08XDvcYcwX4gKD9jIxIY/vWF6hXVyG/F6YiNy5L7AOO4cPQRtYh5OyLTe0EoEmoXnr gHFjTK5V5nS2mqZJuH/Uddyqm/Qm2oNaI/wLEjlw73SCdTjA9YZFZf044YK3LUpo/LCh K5cbYecKkU16GTCBFz/VyQqtDuRBAIa5+yqdCU1KO6eOZrd8JM4xLoFFILcg+naCxi2n ZyiPtL8d32tZIFxzhsMBL0aJd/w+55xRkxPHvlO1AMd4YlugwwVjUw2fjXxvU4GzzSdF f/OA== X-Gm-Message-State: ANhLgQ2E9PiFs+ZfS23NK0vW0aGHD1P2rP4MlaRmtldh82a4Lr+nJrqp kghLhl8DB287P6H+cZ5YsVQ= X-Google-Smtp-Source: ADFU+vu8AW19omtsz4p5v1SCcaJKz9JTMA/bUWMxKE9V/XgDOHgX/qFmo+Ue2EvEDxfBuDtHV6Nyvw== X-Received: by 2002:a50:cd5a:: with SMTP id d26mr9634264edj.65.1584729321016; Fri, 20 Mar 2020 11:35:21 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:20 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Sham Muthayyan , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/12] pcie: qcom: add tx term offset support Date: Fri, 20 Mar 2020 19:34:49 +0100 Message-Id: <20200320183455.21311-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Add tx term offset support to pcie qcom driver need in some revision of the ipq806x soc Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 61 ++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ecc22fd27ea6..8009e3117765 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -45,7 +45,13 @@ #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 #define PCIE20_PARF_PHY_CTRL 0x40 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16) + #define PCIE20_PARF_PHY_REFCLK 0x4C +#define REF_SSP_EN BIT(16) +#define REF_USE_PAD BIT(12) + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 @@ -77,6 +83,18 @@ #define DBI_RO_WR_EN 1 #define PERST_DELAY_US 1000 +/* PARF registers */ +#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0) + +#define PCIE20_PARF_PCS_SWING 0x38 +#define PCS_SWING_TX_SWING_FULL(x) (x << 8) +#define PCS_SWING_TX_SWING_LOW(x) (x << 0) + +#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PHY_RX0_EQ(x) (x << 24) #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 @@ -97,6 +115,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *phy_reset; struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; + uint8_t phy_tx0_term_offset; }; struct qcom_pcie_resources_1_0_0 { @@ -184,6 +203,16 @@ struct qcom_pcie { #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) +static inline void +writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask) +{ + u32 val = readl(addr); + + val &= ~clear_mask; + val |= set_mask; + writel(val, addr); +} + static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { gpiod_set_value_cansleep(pcie->reset, 1); @@ -277,6 +306,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->ext_reset)) return PTR_ERR(res->ext_reset); + if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset", + &res->phy_tx0_term_offset)) + res->phy_tx0_term_offset = 0; + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -304,7 +337,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - u32 val; int ret; ret = reset_control_assert(res->ahb_reset); @@ -355,15 +387,26 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); - val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); + + /* Set Tx termination offset */ + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, + PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, + PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset)); + + /* PARF programming */ + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) | + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) | + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22), + pcie->parf + PCIE20_PARF_PCS_DEEMPH); + writel(PCS_SWING_TX_SWING_FULL(0x78) | + PCS_SWING_TX_SWING_LOW(0x78), + pcie->parf + PCIE20_PARF_PCS_SWING); + writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS); - /* enable external reference clock */ - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); + /* Enable reference clock */ + writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, + REF_USE_PAD, REF_SSP_EN); ret = reset_control_deassert(res->phy_reset); if (ret) { From patchwork Fri Mar 20 18:34:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450081 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94FDB1667 for ; Fri, 20 Mar 2020 18:35:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7484B20870 for ; Fri, 20 Mar 2020 18:35:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IvtmddBb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727527AbgCTSfw (ORCPT ); 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:22 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/12] devicetree: bindings: pci: add phy-tx0-term-offset to qcom,pcie Date: Fri, 20 Mar 2020 19:34:50 +0100 Message-Id: <20200320183455.21311-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document phy-tx0-term-offset propriety to qcom pcie driver Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 6efcef040741..8c1d014f37b0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -254,6 +254,12 @@ - "perst-gpios" PCIe endpoint reset signal line - "wake-gpios" PCIe endpoint wake signal line +- phy-tx0-term-offset: + Usage: optional + Value type: + Definition: If not defined is 0. In ipq806x is set to 7. In newer + revision (v2.0) the offset is zero. + * Example for ipq/apq8064 pcie@1b500000 { compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; @@ -293,6 +299,7 @@ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; + phy-tx0-term-offset = <7>; }; * Example for apq8084 From patchwork Fri Mar 20 18:34:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450073 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C4B217E6 for ; Fri, 20 Mar 2020 18:35:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 107A820739 for ; Fri, 20 Mar 2020 18:35:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sBbFrg0z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727531AbgCTSfa (ORCPT ); Fri, 20 Mar 2020 14:35:30 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:39443 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727521AbgCTSf3 (ORCPT ); Fri, 20 Mar 2020 14:35:29 -0400 Received: by mail-ed1-f68.google.com with SMTP id a43so8311781edf.6; Fri, 20 Mar 2020 11:35:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8eK3e1PI+UmHz8Hye1maNufVhAlQwBW5fj1ru2/xppA=; b=sBbFrg0zbNZn74IeuNSoXSU6Y9Ofyq5BN2GbFCQXl9G1RaU95yjB1ZnZyv8AAJtwrn A4YGM+8QDWL6BA71j9jt7C9D2c4qH6q8brieLBfWztcwlGlAznnrhY+g+Fq7vSSmAdCG aH+A5d3Faz76PLzG9cMFpk/IUuJkaaFdpzEx3MnBrHa7vNy+4zJDUqLVjO0wfVZlN0o7 V6xUVCgIZ9W6EUpvu0WgLF/iKCDqTaxUbUirJcDWZqa6DT4AIX12+X3izpOBCAqSGj7K 7vdkv+bD8gZXidcwexThuXEJJauXAhWvJ/VcfxQHoBejwD85PKHkOybgZnRhgPiYFT0s uBVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8eK3e1PI+UmHz8Hye1maNufVhAlQwBW5fj1ru2/xppA=; b=EEHrKER8e2NOQ/jEsE4RJ7XxQiKN0zAbp8cpS/Um3XrjHk30+dIln7IpLOXzXTM+4S G2Jjn+Kn2p74bIXzyDWuCuO6WY/lamp1OY2PXSV7G14GwK4DnsngiqnhMM131zhKjMPl rWxMLxp8NlmI6Mfnm0/RY101N1vJ8zRXzAu7lIZe21AtrtxLnbkCH8svkWPqDWOec6+S uebyPZI6biLZyHyNScIsPYGU8wbvnTbZ20hZTbneFK+24CPvNnTgv73hOsniIKjTkS+D er4bWBJzGBJdO0JSSoKCyyezKSSt3TRfWdKRIvf9Op0a1Jiq8HUpCjiMupC8+qAUybkI ZZDg== X-Gm-Message-State: ANhLgQ3S12xiHYla348dqgq6fXWYF1U1rCneD+NhCsGiDGc37J/KAaPL 11uBH6GtvxIAZbQk5eXYVGM= X-Google-Smtp-Source: ADFU+vus817SAtCmyfU8vW8+j/gVz5a9XM2N41s6kR7OjTLOec8BOPOW4+naOkkgNjtoHKeFcJ76xQ== X-Received: by 2002:aa7:cd8f:: with SMTP id x15mr9317135edv.156.1584729326478; Fri, 20 Mar 2020 11:35:26 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:25 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Sham Muthayyan , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/12] pcie: qcom: Programming the PCIE iATU for IPQ806x Date: Fri, 20 Mar 2020 19:34:51 +0100 Message-Id: <20200320183455.21311-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Resolved PCIE EP detection errors caused due to missing iATU programming. Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 78 ++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8009e3117765..e26ba8f63d4f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -77,6 +77,30 @@ #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) #define PCIE_CAP_LINK1_VAL 0x2FD7F +#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) + +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c + +#define PCIE20_PLR_IATU_VIEWPORT 0x900 +#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0) + +#define PCIE20_PLR_IATU_CTRL1 0x904 +#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0) +#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0) + +#define PCIE20_PLR_IATU_CTRL2 0x908 +#define PCIE20_PLR_IATU_ENABLE BIT(31) + +#define PCIE20_PLR_IATU_LBAR 0x90C +#define PCIE20_PLR_IATU_UBAR 0x910 +#define PCIE20_PLR_IATU_LAR 0x914 +#define PCIE20_PLR_IATU_LTAR 0x918 +#define PCIE20_PLR_IATU_UTAR 0x91c + +#define MSM_PCIE_DEV_CFG_ADDR 0x01000000 + #define PCIE20_PARF_Q2A_FLUSH 0x1AC #define PCIE20_MISC_CONTROL_1_REG 0x8BC @@ -251,6 +275,57 @@ static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); } +static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev) +{ + struct pcie_port *pp = &pcie->pci->pp; + + /* + * program and enable address translation region 0 (device config + * address space); region type config; + * axi config address range to device config address range + */ + writel(PCIE20_PLR_IATU_REGION_OUTBOUND | + PCIE20_PLR_IATU_REGION_INDEX(0), + pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT); + + writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1); + writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2); + writel(pp->cfg0_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR); + writel((pp->cfg0_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR); + writel((pp->cfg0_base + pp->cfg0_size - 1), + pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR); + writel(busdev, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR); + writel(0, pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR); +} + +static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie) +{ + struct pcie_port *pp = &pcie->pci->pp; + + /* + * program and enable address translation region 2 (device resource + * address space); region type memory; + * axi device bar address range to device bar address range + */ + writel(PCIE20_PLR_IATU_REGION_OUTBOUND | + PCIE20_PLR_IATU_REGION_INDEX(2), + pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT); + + writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1); + writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2); + writel(pp->mem_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR); + writel((pp->mem_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR); + writel(pp->mem_base + pp->mem_size - 1, + pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR); + writel(pp->mem_bus_addr, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR); + writel(upper_32_bits(pp->mem_bus_addr), + pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR); + + /* 256B PCIE buffer setting */ + writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); +} + static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; @@ -448,6 +523,9 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) writel(CFG_BRIDGE_SB_INIT, pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); + qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR); + qcom_pcie_prog_viewport_mem2_outbound(pcie); + return 0; err_deassert_ahb: From patchwork Fri Mar 20 18:34:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450071 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 843161864 for ; Fri, 20 Mar 2020 18:35:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 611F920786 for ; Fri, 20 Mar 2020 18:35:50 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:28 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Sham Muthayyan , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/12] pcie: qcom: add Force GEN1 support Date: Fri, 20 Mar 2020 19:34:52 +0100 Message-Id: <20200320183455.21311-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Add Force GEN1 support needed in some ipq806x board that needs to limit some pcie line to gen1 for some hardware limitation Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e26ba8f63d4f..03130a3206b4 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -123,6 +123,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -223,6 +225,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + uint32_t force_gen1; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -515,6 +518,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->force_gen1) { + writel_relaxed((readl_relaxed( + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1), + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ @@ -1487,6 +1495,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct qcom_pcie *pcie; int ret; + uint32_t force_gen1 = 0; + struct device_node *np = pdev->dev.of_node; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -1517,6 +1527,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + of_property_read_u32(np, "force_gen1", &force_gen1); + pcie->force_gen1 = force_gen1; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); pcie->parf = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->parf)) { From patchwork Fri Mar 20 18:34:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450061 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 378C61667 for ; Fri, 20 Mar 2020 18:35:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1647320777 for ; Fri, 20 Mar 2020 18:35:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hCGk/jVY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727563AbgCTSff (ORCPT ); Fri, 20 Mar 2020 14:35:35 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:34667 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727547AbgCTSfe (ORCPT ); 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:31 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/12] devicetree: bindings: pci: add force_gen1 for qcom,pcie Date: Fri, 20 Mar 2020 19:34:53 +0100 Message-Id: <20200320183455.21311-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document force_gen1 optional definition to limit pcie line to GEN1 speed Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 8c1d014f37b0..766876465c42 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -260,6 +260,11 @@ Definition: If not defined is 0. In ipq806x is set to 7. In newer revision (v2.0) the offset is zero. +- force_gen1: + Usage: optional + Value type: + Definition: Set 1 to force the pcie line to GEN1 + * Example for ipq/apq8064 pcie@1b500000 { compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; From patchwork Fri Mar 20 18:34:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11450063 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A2341667 for ; Fri, 20 Mar 2020 18:35:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D93FF208CA for ; Fri, 20 Mar 2020 18:35:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="A91sMfRk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727547AbgCTSfh (ORCPT ); Fri, 20 Mar 2020 14:35:37 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:44498 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725446AbgCTSfh (ORCPT ); Fri, 20 Mar 2020 14:35:37 -0400 Received: by mail-ed1-f67.google.com with SMTP id z3so8266993edq.11; Fri, 20 Mar 2020 11:35:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R1yA09A2jj2GJ7mf6EWjnGj5car0+pFadneU5DRW1E0=; b=A91sMfRkl42TkFSWs9Q9IhP6ewbRQpGP3zvAHs4ixj8O0VAlwGf2XdqjxNkda42p+F rE1DdJYbgM+bE/7PhlMb0i8QNf6tNtciczvIyl6A7MvXq2tplBeeOIREacm5BF8C0Fw7 y9sLTfP6+k64lr6KcJIL291+2IO2htWpdYT/FRFBPULP7rUPSY7Xs/lPWCzsVEW5Mlsj yowqy//ObW7xPUz+y9oVin5RzgtlFn/PydNjEYt5Z8Em8x0mS+PiZ8NOY0CpQQH9Cr+W z4WnBLD8zAVDMWGGwLcnVIUyI8ISCr4mR0xjG5JGN4/hmdWAYWZWBu4vEvL2hovawwHJ akjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R1yA09A2jj2GJ7mf6EWjnGj5car0+pFadneU5DRW1E0=; b=U9kpaTOT0dc+MqPSsaRRcXngU1pgfjRXjlPnaOpCFyJ6HrvN+RZ004oNvipAZsFZk8 REIluxWus3h7k+hPtYUwyB2BXUlCTvfmBlNefd/+OUP9XaH0NagLhoeDPG8bGXrF5nh0 KYyHVzKUe8iYbhLAeLo5rEICQ6CR56WEjScZpHYILavL3sY/6FkOnXJeFRbgzZPawmJJ 6+e5TkANcd9QPWvYtVdHoU4DsbmyNMHY/hNfMV0FjKGw4HxVUNGieTBuEwdQCO6on3/0 /wvNFZbFaaNjEky5F6tKdfFOpid1o9cTLbpIOyfBw7EqRscBbXGPHYNiv/cPk+TkMmsm QXfg== X-Gm-Message-State: ANhLgQ3S0AIrlaJi6aF6H29dbzdW/yxNYJmVrVhgu0hoRYsQRtB6B1A3 hc+n2XcJzDi20biyTqbkhYo= X-Google-Smtp-Source: ADFU+vtC/hTDKXr5YBXEcAwc7n8EoSk1Q/19B2vYXfusmIsN1j9VwEZgjYrCe4aSdRDu42y4EE82hw== X-Received: by 2002:aa7:d9d8:: with SMTP id v24mr3531315eds.386.1584729334422; Fri, 20 Mar 2020 11:35:34 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:33 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Sriram Palanisamy , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/12] pcie: qcom: Set PCIE MRRS and MPS to 256B Date: Fri, 20 Mar 2020 19:34:54 +0100 Message-Id: <20200320183455.21311-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sriram Palanisamy Set Max Read Request Size and Max Payload Size to 256 bytes, per chip team recommendation. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 03130a3206b4..ad437c6f49a0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -125,6 +125,14 @@ #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 +#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b)) +#define __mask(a, b) (((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1)) +#define PCIE20_DEV_CAS 0x78 +#define PCIE20_MRRS_MASK __mask(14, 12) +#define PCIE20_MRRS(x) __set(x, 14, 12) +#define PCIE20_MPS_MASK __mask(7, 5) +#define PCIE20_MPS(x) __set(x, 7, 5) + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -1595,6 +1603,35 @@ static int qcom_pcie_probe(struct platform_device *pdev) return ret; } +static void qcom_pcie_fixup_final(struct pci_dev *pcidev) +{ + int cap, err; + u16 ctl, reg_val; + + cap = pci_pcie_cap(pcidev); + if (!cap) + return; + + err = pci_read_config_word(pcidev, cap + PCI_EXP_DEVCTL, &ctl); + + if (err) + return; + + reg_val = ctl; + + if (((reg_val & PCIE20_MRRS_MASK) >> 12) > 1) + reg_val = (reg_val & ~(PCIE20_MRRS_MASK)) | PCIE20_MRRS(0x1); + + if (((ctl & PCIE20_MPS_MASK) >> 5) > 1) + reg_val = (reg_val & ~(PCIE20_MPS_MASK)) | PCIE20_MPS(0x1); + + err = pci_write_config_word(pcidev, cap + PCI_EXP_DEVCTL, reg_val); + + if (err) + dev_err(&pcidev->dev, "pcie config write failed %d\n", err); +} +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final); + static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },