From patchwork Sat Mar 21 13:38:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sungbo Eo X-Patchwork-Id: 11451287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDB211392 for ; Sat, 21 Mar 2020 18:03:41 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7A60B2076E for ; Sat, 21 Mar 2020 18:03:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=groups.io header.i=@groups.io header.b="GhBG+4r9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7A60B2076E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gorani.run Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+16102+71+925526+2090324@groups.io X-Received: by 127.0.0.2 with SMTP id qCs9YY926861xINF6sw1iNa; Sat, 21 Mar 2020 11:03:41 -0700 X-Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [91.198.250.252]) by mx.groups.io with SMTP id smtpd.web12.7834.1584798038860762756 for ; Sat, 21 Mar 2020 06:40:39 -0700 X-Received: from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 48l1xJ4ySSzKpBh; Sat, 21 Mar 2020 14:40:36 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de X-Received: from smtp1.mailbox.org ([80.241.60.240]) by spamfilter06.heinlein-hosting.de (spamfilter06.heinlein-hosting.de [80.241.56.125]) (amavisd-new, port 10030) with ESMTP id Gpg7pxJw-UWe; Sat, 21 Mar 2020 14:40:33 +0100 (CET) From: Sungbo Eo To: linux-oxnas@groups.io, Linus Walleij , Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Sungbo Eo , Neil Armstrong , Daniel Golle Subject: [linux-oxnas] [PATCH] irqchip/versatile-fpga: Apply clear-mask earlier Date: Sat, 21 Mar 2020 22:38:42 +0900 Message-Id: <20200321133842.2408823-1-mans0n@gorani.run> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: linux-oxnas@groups.io List-Id: Mailing-List: list linux-oxnas@groups.io; contact linux-oxnas+owner@groups.io Delivered-To: mailing list linux-oxnas@groups.io Reply-To: linux-oxnas@groups.io,mans0n@gorani.run X-Gm-Message-State: eAE2gT3zpdyOu3NeOZ5PzZLsx925526AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1584813821; bh=As4EMR8tLEnq+VoeYilewrYpCOz8YOpKTNpd3WJs5G0=; h=Cc:Date:From:Reply-To:Subject:To; b=GhBG+4r940cm5X5j6hr1/YLhlCs1D/1JfFEd4zzeRcouknC6WyNyXsaYpcKiq8x1BzW WApMAuskx6L9kjjGB/SbPLN2dtGKUG9J3L050nI5iVVtsfzshsmf/SuOCWhrqDFxAXJj1 69Sbf69yW3pxq5xiERNtZDaFBuSgvHADAU0= Clear its own IRQs before the parent IRQ get enabled, so that the remaining IRQs do not accidentally interrupt the parent IRQ controller. This patch also fixes a reboot bug on OX820 SoC, where the remaining rps-timer IRQ raises a GIC interrupt that is left pending. After that, the rps-timer IRQ is cleared during driver initialization, and there's no IRQ left in rps-irq when local_irq_enable() is called, which evokes an error message "unexpected IRQ trap". Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded interrupts from DT") Signed-off-by: Sungbo Eo Cc: Neil Armstrong Cc: Daniel Golle Reviewed-by: Linus Walleij --- drivers/irqchip/irq-versatile-fpga.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c index 70e2cfff8175..f1386733d3bc 100644 --- a/drivers/irqchip/irq-versatile-fpga.c +++ b/drivers/irqchip/irq-versatile-fpga.c @@ -212,6 +212,9 @@ int __init fpga_irq_of_init(struct device_node *node, if (of_property_read_u32(node, "valid-mask", &valid_mask)) valid_mask = 0; + writel(clear_mask, base + IRQ_ENABLE_CLEAR); + writel(clear_mask, base + FIQ_ENABLE_CLEAR); + /* Some chips are cascaded from a parent IRQ */ parent_irq = irq_of_parse_and_map(node, 0); if (!parent_irq) { @@ -221,9 +224,6 @@ int __init fpga_irq_of_init(struct device_node *node, fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); - writel(clear_mask, base + IRQ_ENABLE_CLEAR); - writel(clear_mask, base + FIQ_ENABLE_CLEAR); - /* * On Versatile AB/PB, some secondary interrupts have a direct * pass-thru to the primary controller for IRQs 20 and 22-31 which need